Move 965 video setup to a separate function so we can move it around.

1 files changed, 174 insertions, 172 deletions

diff --git a/src/i965_video.c b/src/i965_video.c
index e9f5ced6..3c626ca4 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -714,6 +714,179 @@ i965_create_cc_state(ScrnInfoPtr scrn)
     return cc_bo;
 }
 
+static void
+i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
+{
+    I830Ptr pI830 = I830PTR(pScrn);
+    int urb_vs_start, urb_vs_size;
+    int urb_gs_start, urb_gs_size;
+    int urb_clip_start, urb_clip_size;
+    int urb_sf_start, urb_sf_size;
+    int urb_cs_start, urb_cs_size;
+
+    IntelEmitInvarientState(pScrn);
+    *pI830->last_3d = LAST_3D_VIDEO;
+
+    urb_vs_start = 0;
+    urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
+    urb_gs_start = urb_vs_start + urb_vs_size;
+    urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
+    urb_clip_start = urb_gs_start + urb_gs_size;
+    urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
+    urb_sf_start = urb_clip_start + urb_clip_size;
+    urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
+    urb_cs_start = urb_sf_start + urb_sf_size;
+    urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
+
+    BEGIN_BATCH(2);
+    OUT_BATCH(MI_FLUSH |
+	      MI_STATE_INSTRUCTION_CACHE_FLUSH |
+	      BRW_MI_GLOBAL_SNAPSHOT_RESET);
+    OUT_BATCH(MI_NOOP);
+    ADVANCE_BATCH();
+
+    /* brw_debug (pScrn, "before base address modify"); */
+    BEGIN_BATCH(12);
+    /* Match Mesa driver setup */
+    if (IS_G4X(pI830))
+	OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+    else
+	OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+
+    /* Mesa does this. Who knows... */
+    OUT_BATCH(BRW_CS_URB_STATE | 0);
+    OUT_BATCH((0 << 4) |	/* URB Entry Allocation Size */
+	      (0 << 0));	/* Number of URB Entries */
+
+    /* Zero out the two base address registers so all offsets are
+     * absolute
+     */
+    OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
+    OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Generate state base address */
+    OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Surface state base address */
+    OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* media base addr, don't care */
+    /* general state max addr, disabled */
+    OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+    /* media object state max addr, disabled */
+    OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+
+    /* Set system instruction pointer */
+    OUT_BATCH(BRW_STATE_SIP | 0);
+    /* system instruction pointer */
+    OUT_RELOC(pI830->video.gen4_sip_kernel_bo,
+	      I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+
+    OUT_BATCH(MI_NOOP);
+    ADVANCE_BATCH();
+
+    /* brw_debug (pScrn, "after base address modify"); */
+
+    BEGIN_BATCH(38);
+    /* Enable VF statistics */
+    OUT_BATCH(BRW_3DSTATE_VF_STATISTICS | 1);
+
+    /* Pipe control */
+    OUT_BATCH(BRW_PIPE_CONTROL |
+	      BRW_PIPE_CONTROL_NOWRITE |
+	      BRW_PIPE_CONTROL_IS_FLUSH |
+	      2);
+    OUT_BATCH(0);			/* Destination address */
+    OUT_BATCH(0);			/* Immediate data low DW */
+    OUT_BATCH(0);			/* Immediate data high DW */
+
+    /* Binding table pointers */
+    OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
+    OUT_BATCH(0); /* vs */
+    OUT_BATCH(0); /* gs */
+    OUT_BATCH(0); /* clip */
+    OUT_BATCH(0); /* sf */
+    /* Only the PS uses the binding table */
+    OUT_RELOC(bind_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+    drm_intel_bo_unreference(bind_bo);
+
+    /* Blend constant color (magenta is fun) */
+    OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
+    OUT_BATCH(float_to_uint (1.0));
+    OUT_BATCH(float_to_uint (0.0));
+    OUT_BATCH(float_to_uint (1.0));
+    OUT_BATCH(float_to_uint (1.0));
+
+    /* The drawing rectangle clipping is always on.  Set it to values that
+     * shouldn't do any clipping.
+     */
+    OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
+    OUT_BATCH(0x00000000);			/* ymin, xmin */
+    OUT_BATCH((pScrn->virtualX - 1) |
+	      (pScrn->virtualY - 1) << 16);	/* ymax, xmax */
+    OUT_BATCH(0x00000000);			/* yorigin, xorigin */
+
+    /* skip the depth buffer */
+    /* skip the polygon stipple */
+    /* skip the polygon stipple offset */
+    /* skip the line stipple */
+
+    /* Set the pointers to the 3d pipeline state */
+    OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
+    OUT_RELOC(pI830->video.gen4_vs_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+    /* disable GS, resulting in passthrough */
+    OUT_BATCH(BRW_GS_DISABLE);
+    /* disable CLIP, resulting in passthrough */
+    OUT_BATCH(BRW_CLIP_DISABLE);
+    OUT_RELOC(pI830->video.gen4_sf_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+    if (n_src_surf == 1)
+	OUT_RELOC(pI830->video.gen4_wm_packed_bo,
+		  I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+    else
+	OUT_RELOC(pI830->video.gen4_wm_planar_bo,
+		  I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+    OUT_RELOC(pI830->video.gen4_cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
+
+    /* URB fence */
+    OUT_BATCH(BRW_URB_FENCE |
+	      UF0_CS_REALLOC |
+	      UF0_SF_REALLOC |
+	      UF0_CLIP_REALLOC |
+	      UF0_GS_REALLOC |
+	      UF0_VS_REALLOC |
+	      1);
+    OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
+	      ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
+	      ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
+    OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
+	      ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
+
+    /* Constant buffer state */
+    OUT_BATCH(BRW_CS_URB_STATE | 0);
+    OUT_BATCH(((URB_CS_ENTRY_SIZE - 1) << 4) |
+	      (URB_CS_ENTRIES << 0));
+
+    /* Set up our vertex elements, sourced from the single vertex buffer. */
+    OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
+    /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
+    OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+	      VE0_VALID |
+	      (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+	      (0 << VE0_OFFSET_SHIFT));
+    OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+	      (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+	      (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+	      (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+	      (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+    /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
+    OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
+	      VE0_VALID |
+	      (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
+	      (8 << VE0_OFFSET_SHIFT));
+    OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
+	      (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
+	      (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
+	      (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
+	      (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
+
+    OUT_BATCH(MI_NOOP);			/* pad to quadword */
+    ADVANCE_BATCH();
+}
+
 void
 I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
 			 RegionPtr dstRegion,
@@ -726,11 +899,6 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
     I830Ptr pI830 = I830PTR(pScrn);
     BoxPtr pbox;
     int nbox, dxo, dyo, pix_xoff, pix_yoff;
-    int urb_vs_start, urb_vs_size;
-    int urb_gs_start, urb_gs_size;
-    int urb_clip_start, urb_clip_size;
-    int urb_sf_start, urb_sf_size;
-    int urb_cs_start, urb_cs_size;
     float src_scale_x, src_scale_y;
     int src_surf, i;
     int n_src_surf;
@@ -798,25 +966,11 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
 	return;
     }    
 
-    IntelEmitInvarientState(pScrn);
-    *pI830->last_3d = LAST_3D_VIDEO;
-
 #if 0
     ErrorF("dst surf:      0x%08x\n", state_base_offset + dest_surf_offset);
     ErrorF("src surf:      0x%08x\n", state_base_offset + src_surf_offset);
 #endif
 
-    urb_vs_start = 0;
-    urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
-    urb_gs_start = urb_vs_start + urb_vs_size;
-    urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
-    urb_clip_start = urb_gs_start + urb_gs_size;
-    urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
-    urb_sf_start = urb_clip_start + urb_clip_size;
-    urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
-    urb_cs_start = urb_sf_start + urb_sf_size;
-    urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
-
     /* We'll be poking the state buffers that could be in use by the 3d
      * hardware here, but we should have synced the 3D engine already in
      * I830PutImage.
@@ -903,159 +1057,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
 	}
     }
 
-    {
-	BEGIN_BATCH(2);
-	OUT_BATCH(MI_FLUSH |
-		  MI_STATE_INSTRUCTION_CACHE_FLUSH |
-		  BRW_MI_GLOBAL_SNAPSHOT_RESET);
-	OUT_BATCH(MI_NOOP);
-	ADVANCE_BATCH();
-    }
-
-    /* brw_debug (pScrn, "before base address modify"); */
-    {
-	BEGIN_BATCH(12);
-	/* Match Mesa driver setup */
-	if (IS_G4X(pI830))
-	    OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
-	else
-	    OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
-
-	/* Mesa does this. Who knows... */
-	OUT_BATCH(BRW_CS_URB_STATE | 0);
-	OUT_BATCH((0 << 4) |	/* URB Entry Allocation Size */
-		  (0 << 0));	/* Number of URB Entries */
-
-	/* Zero out the two base address registers so all offsets are
-	 * absolute
-	 */
-	OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Generate state base address */
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* Surface state base address */
-	OUT_BATCH(0 | BASE_ADDRESS_MODIFY);  /* media base addr, don't care */
-	/* general state max addr, disabled */
-	OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
-	/* media object state max addr, disabled */
-	OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
-
-	/* Set system instruction pointer */
-	OUT_BATCH(BRW_STATE_SIP | 0);
-	/* system instruction pointer */
-	OUT_RELOC(pI830->video.gen4_sip_kernel_bo,
-		  I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-
-	OUT_BATCH(MI_NOOP);
-	ADVANCE_BATCH();
-    }
-
-    /* brw_debug (pScrn, "after base address modify"); */
-
-    {
-       BEGIN_BATCH(38);
-       /* Enable VF statistics */
-       OUT_BATCH(BRW_3DSTATE_VF_STATISTICS | 1);
-
-       /* Pipe control */
-       OUT_BATCH(BRW_PIPE_CONTROL |
-		 BRW_PIPE_CONTROL_NOWRITE |
-		 BRW_PIPE_CONTROL_IS_FLUSH |
-		 2);
-       OUT_BATCH(0);			/* Destination address */
-       OUT_BATCH(0);			/* Immediate data low DW */
-       OUT_BATCH(0);			/* Immediate data high DW */
-
-       /* Binding table pointers */
-       OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
-       OUT_BATCH(0); /* vs */
-       OUT_BATCH(0); /* gs */
-       OUT_BATCH(0); /* clip */
-       OUT_BATCH(0); /* sf */
-       /* Only the PS uses the binding table */
-       OUT_RELOC(bind_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-       drm_intel_bo_unreference(bind_bo);
-
-       /* Blend constant color (magenta is fun) */
-       OUT_BATCH(BRW_3DSTATE_CONSTANT_COLOR | 3);
-       OUT_BATCH(float_to_uint (1.0));
-       OUT_BATCH(float_to_uint (0.0));
-       OUT_BATCH(float_to_uint (1.0));
-       OUT_BATCH(float_to_uint (1.0));
-
-       /* The drawing rectangle clipping is always on.  Set it to values that
-	* shouldn't do any clipping.
-	*/
-       OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
-       OUT_BATCH(0x00000000);			/* ymin, xmin */
-       OUT_BATCH((pScrn->virtualX - 1) |
-		 (pScrn->virtualY - 1) << 16);	/* ymax, xmax */
-       OUT_BATCH(0x00000000);			/* yorigin, xorigin */
-
-       /* skip the depth buffer */
-       /* skip the polygon stipple */
-       /* skip the polygon stipple offset */
-       /* skip the line stipple */
-
-       /* Set the pointers to the 3d pipeline state */
-       OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
-       OUT_RELOC(pI830->video.gen4_vs_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-       /* disable GS, resulting in passthrough */
-       OUT_BATCH(BRW_GS_DISABLE);
-       /* disable CLIP, resulting in passthrough */
-       OUT_BATCH(BRW_CLIP_DISABLE);
-       OUT_RELOC(pI830->video.gen4_sf_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-       if (n_src_surf == 1)
-	   OUT_RELOC(pI830->video.gen4_wm_packed_bo,
-		     I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-       else
-	   OUT_RELOC(pI830->video.gen4_wm_planar_bo,
-		     I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-       OUT_RELOC(pI830->video.gen4_cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
-
-       /* URB fence */
-       OUT_BATCH(BRW_URB_FENCE |
-		 UF0_CS_REALLOC |
-		 UF0_SF_REALLOC |
-		 UF0_CLIP_REALLOC |
-		 UF0_GS_REALLOC |
-		 UF0_VS_REALLOC |
-		 1);
-       OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
-		 ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
-		 ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
-       OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
-		 ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
-
-       /* Constant buffer state */
-       OUT_BATCH(BRW_CS_URB_STATE | 0);
-       OUT_BATCH(((URB_CS_ENTRY_SIZE - 1) << 4) |
-		 (URB_CS_ENTRIES << 0));
-
-       /* Set up our vertex elements, sourced from the single vertex buffer. */
-       OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
-       /* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
-       OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-		 VE0_VALID |
-		 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-		 (0 << VE0_OFFSET_SHIFT));
-       OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-		 (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
-		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
-		 (0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
-       /* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
-       OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
-		 VE0_VALID |
-		 (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
-		 (8 << VE0_OFFSET_SHIFT));
-       OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
-		 (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
-		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
-		 (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
-		 (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
-
-       OUT_BATCH(MI_NOOP);			/* pad to quadword */
-       ADVANCE_BATCH();
-    }
+    i965_emit_video_setup(pScrn, bind_bo, n_src_surf);
 
    /* Set up the offset for translating from the given region (in screen
     * coordinates) to the backing pixmap.