diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-11-21 12:56:32 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-11-21 13:02:34 +0000 |
| commit | 4a27dd287cdb85d80ceaf6b54e7de0c17e01c00d (patch) | |
| tree | bca0f93b3dd728beed686d6331e28a56b05993df /src/intel_uxa.c | |
| parent | b0d64a9567d9cb749568448e4ce090b187308028 (diff) | |
uxa: Make the glamor/uxa transition more verbose
And so hopefully make it clearer. In the process we restore the flushing
behaviour for UXA back to before the glamor intervention.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_uxa.c')
| -rw-r--r-- | src/intel_uxa.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/src/intel_uxa.c b/src/intel_uxa.c index 114a43ed..1aedae04 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -706,15 +706,19 @@ static Bool intel_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access) dri_bo *bo = priv->bo; int ret; - if (!list_is_empty(&priv->batch) && - ((access == UXA_ACCESS_RW || access == UXA_GLAMOR_ACCESS_RW) - || priv->batch_write)) - intel_batch_submit(scrn); - - if (access == UXA_GLAMOR_ACCESS_RW || access == UXA_GLAMOR_ACCESS_RO) + /* Transitioning to glamor acceleration, we need to flush all pending + * usage by UXA. */ + if (access == UXA_GLAMOR_ACCESS_RW || access == UXA_GLAMOR_ACCESS_RO) { + if (!list_is_empty(&priv->batch)) + intel_batch_submit(scrn); return TRUE; + } + /* When falling back to swrast, flush all pending operations */ intel_glamor_flush(intel); + if (!list_is_empty(&priv->batch) && + (access == UXA_ACCESS_RW || priv->batch_write)) + intel_batch_submit(scrn); if (priv->tiling || bo->size <= intel->max_gtt_map_size) ret = drm_intel_gem_bo_map_gtt(bo); @@ -722,8 +726,10 @@ static Bool intel_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access) ret = dri_bo_map(bo, access == UXA_ACCESS_RW); if (ret) { xf86DrvMsg(scrn->scrnIndex, X_WARNING, - "%s: bo map failed: %s\n", + "%s: bo map (use gtt? %d, access %d) failed: %s\n", __FUNCTION__, + priv->tiling || bo->size <= intel->max_gtt_map_size, + access, strerror(-ret)); return FALSE; } |