diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-14 19:47:00 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-14 19:47:00 +0000 |
| commit | cc930a37612341a1f2457adb339523c215879d82 (patch) | |
| tree | 14a8753a5eab49c0af3468a12e6cb86fb06771dd /src/intel_uxa.c | |
| parent | 3c5b1399e29ef577b8b91655b5e1c215d1b6dfbb (diff) | |
uxa: Relax fencing some more for gen3
Allow fenced allocations even for small pixmaps if the kernel supports
relaxing fencing (where only the used pages are allocated).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/intel_uxa.c')
| -rw-r--r-- | src/intel_uxa.c | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/src/intel_uxa.c b/src/intel_uxa.c index ee1247f4..8db0ef0d 100644 --- a/src/intel_uxa.c +++ b/src/intel_uxa.c @@ -146,18 +146,22 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap, pitch = ALIGN(pitch, 64); size = pitch * ALIGN (h, 2); if (INTEL_INFO(intel)->gen < 40) { - /* Older hardware requires fences to be pot size - * aligned with a minimum of 1 MiB, so causes - * massive overallocation for small textures. - */ - if (size < 1024*1024/2) - *tiling = I915_TILING_NONE; - /* Gen 2/3 has a maximum stride for tiling of * 8192 bytes. */ if (pitch > KB(8)) *tiling = I915_TILING_NONE; + + /* Narrower than half a tile? */ + if (pitch < 256) + *tiling = I915_TILING_NONE; + + /* Older hardware requires fences to be pot size + * aligned with a minimum of 1 MiB, so causes + * massive overallocation for small textures. + */ + if (size < 1024*1024/2 && !intel->has_relaxed_fencing) + *tiling = I915_TILING_NONE; } else if (!(usage & INTEL_CREATE_PIXMAP_DRI2) && size <= 4096) { /* Disable tiling beneath a page size, we will not see * any benefit from reducing TLB misses and instead |