diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2011-06-22 23:33:08 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2011-06-24 09:42:07 +0800 |
| commit | 3cf423bd3a9483181e59ee87376a9487fa1f923d (patch) | |
| tree | 8ba311bda2b25c96eee75ec02c1d73b099189091 /src/render_program/Makefile.am | |
| parent | 58d7a89b93ba4022f45465e479d2799b8903137a (diff) | |
Xv: separate fragments from M4 macros
It is to prepare for Xv on Ivybridge. The difference from Sandybridge
is that all message payload must be in GRF registers instead of MRF registers
on Ivybridge. We will only redefine some M4 macros for Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Diffstat (limited to 'src/render_program/Makefile.am')
| -rw-r--r-- | src/render_program/Makefile.am | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/render_program/Makefile.am b/src/render_program/Makefile.am index 1a194375..8e48d270 100644 --- a/src/render_program/Makefile.am +++ b/src/render_program/Makefile.am @@ -20,7 +20,9 @@ INTEL_G4A = \ INTEL_G4I = \ exa_wm.g4i \ exa_wm_affine.g4i \ - exa_wm_projective.g4i + exa_wm_projective.g4i \ + exa_wm_sample_planar.g4i \ + exa_wm_src_sample_argb.g4i INTEL_G4B = \ exa_sf.g4b \ @@ -61,6 +63,10 @@ INTEL_G4B_GEN5 = \ exa_wm_yuv_rgb.g4b.gen5 \ exa_wm_xy.g4b.gen5 +INTEL_G6I = \ + exa_wm_affine.g6i \ + exa_wm_write.g6i + INTEL_G6A = \ exa_wm_src_affine.g6a \ exa_wm_src_projective.g6a \ @@ -99,7 +105,8 @@ EXTRA_DIST = \ $(INTEL_G4B) \ $(INTEL_G4B_GEN5)\ $(INTEL_G6A) \ - $(INTEL_G6B) + $(INTEL_G6B) \ + $(INTEL_G6I) if HAVE_GEN4ASM @@ -111,7 +118,7 @@ SUFFIXES = .g4a .g4b .g6a .g6b m4 -I$(srcdir) -s $< > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m $(INTEL_G4B): $(INTEL_G4I) -$(INTEL_G6B): $(INTEL_G4I) +$(INTEL_G6B): $(INTEL_G4I) $(INTEL_G6I) BUILT_SOURCES= $(INTEL_G4B) $(INTEL_G6B) |