diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2011-06-22 23:33:08 +0800 |
|---|---|---|
| committer | Xiang, Haihao <haihao.xiang@intel.com> | 2011-06-24 09:42:07 +0800 |
| commit | 3cf423bd3a9483181e59ee87376a9487fa1f923d (patch) | |
| tree | 8ba311bda2b25c96eee75ec02c1d73b099189091 /src/render_program/exa_wm_mask_affine.g6a | |
| parent | 58d7a89b93ba4022f45465e479d2799b8903137a (diff) | |
Xv: separate fragments from M4 macros
It is to prepare for Xv on Ivybridge. The difference from Sandybridge
is that all message payload must be in GRF registers instead of MRF registers
on Ivybridge. We will only redefine some M4 macros for Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Diffstat (limited to 'src/render_program/exa_wm_mask_affine.g6a')
| -rw-r--r-- | src/render_program/exa_wm_mask_affine.g6a | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/src/render_program/exa_wm_mask_affine.g6a b/src/render_program/exa_wm_mask_affine.g6a index 2daf4e24..04ad2a23 100644 --- a/src/render_program/exa_wm_mask_affine.g6a +++ b/src/render_program/exa_wm_mask_affine.g6a @@ -38,10 +38,4 @@ define(`bh', `g4.0<8,8,1>F') define(`a0_a_x',`g8.0<0,1,0>F') define(`a0_a_y',`g8.16<0,1,0>F') -/* U */ -pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ -pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ - -/* V */ -pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ -pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ +include(`exa_wm_affine.g6i') |