Xv: separate fragments from M4 macros

It is to prepare for Xv on Ivybridge. The difference from Sandybridge
is that all message payload must be in GRF registers instead of MRF registers
on Ivybridge. We will only redefine some M4 macros for Ivybridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

1 files changed, 61 insertions, 0 deletions

diff --git a/src/render_program/exa_wm_write.g6i b/src/render_program/exa_wm_write.g6i
new file mode 100644
index 00000000..7be1db29
--- /dev/null
+++ b/src/render_program/exa_wm_write.g6i
@@ -0,0 +1,61 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+mov (8) slot_r_00<1>F     src_sample_r_01<8,8,1>F { align1 };
+mov (8) slot_r_01<1>F     src_sample_r_23<8,8,1>F { align1 };
+
+mov (8) slot_g_00<1>F     src_sample_g_01<8,8,1>F { align1 };
+mov (8) slot_g_01<1>F     src_sample_g_23<8,8,1>F { align1 };
+
+mov (8) slot_b_00<1>F     src_sample_b_01<8,8,1>F { align1 };
+mov (8) slot_b_01<1>F     src_sample_b_23<8,8,1>F { align1 };
+
+mov (8) slot_a_00<1>F     src_sample_a_01<8,8,1>F { align1 };
+mov (8) slot_a_01<1>F     src_sample_a_23<8,8,1>F { align1 };
+
+/* write */
+send (16) 
+	data_port_msg_2_ind 
+	acc0<1>UW 
+	null
+	write (
+	       0,  /* binding_table */
+	       16,  /* pixel scordboard clear, msg type simd16 single source */
+	       12,  /* render target write */
+	       0,   /* no write commit message */
+	       0  /* headerless render target write */
+	) 
+	mlen 8
+	rlen 0
+	{ align1 EOT };
+
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+nop;
+