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| author | Edward Sheldrake <ejsheldrake@gmail.com> | 2014-02-03 09:34:33 +0000 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2014-02-03 10:04:15 +0000 |
| commit | 1cbc59a917e7352fc68aa0e26b1575cbd0ceab0d (patch) | |
| tree | d0d2aabad9ae331f620968a07198003836825b6d /src/sna/gen4_render.h | |
| parent | 7f08250a8960f90f6bd34de8c4a17870703bfa60 (diff) | |
sna/gen4,5: Fix setting pipe control cache flush bits
Cache flush bits are on dword 0, not 1, on gen4 and gen5. Also texture
cache invalidate is only available from Cantiga onwards.
Diffstat (limited to 'src/sna/gen4_render.h')
| -rw-r--r-- | src/sna/gen4_render.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/sna/gen4_render.h b/src/sna/gen4_render.h index 53c7fc2f..64d11e66 100644 --- a/src/sna/gen4_render.h +++ b/src/sna/gen4_render.h @@ -112,7 +112,7 @@ #define GEN4_PIPE_CONTROL_DEPTH_STALL (1 << 13) #define GEN4_PIPE_CONTROL_WC_FLUSH (1 << 12) #define GEN4_PIPE_CONTROL_IS_FLUSH (1 << 11) -#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) +#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) /* ctg+ */ #define GEN4_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) #define GEN4_PIPE_CONTROL_GLOBAL_GTT (1 << 2) #define GEN4_PIPE_CONTROL_LOCAL_PGTT (0 << 2) |