diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-22 21:28:34 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-04-22 22:48:54 +0100 |
| commit | cac8e1ee74fa8704a42a5c5ebe65d5ec777cbd67 (patch) | |
| tree | 951c405f3b582a8b5413992188804bc9fae11fde /src/uxa/intel_batchbuffer.h | |
| parent | 46caee86db0fb32b16213893c79d9c1a21ed0883 (diff) | |
uxa: Enable Y-tiling BLT support
Mesa wants to pass Y-tiled framebuffers onto scanout. Admittedly, this
isn't quite that but it does prevent them being jumbled up.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'src/uxa/intel_batchbuffer.h')
| -rw-r--r-- | src/uxa/intel_batchbuffer.h | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/uxa/intel_batchbuffer.h b/src/uxa/intel_batchbuffer.h index e5fb8d08..e71ffd19 100644 --- a/src/uxa/intel_batchbuffer.h +++ b/src/uxa/intel_batchbuffer.h @@ -30,7 +30,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #ifndef _INTEL_BATCHBUFFER_H #define _INTEL_BATCHBUFFER_H -#define BATCH_RESERVED 16 +#define BATCH_RESERVED 64 void intel_batch_init(ScrnInfoPtr scrn); @@ -202,6 +202,23 @@ do { \ #define BEGIN_BATCH(n) __BEGIN_BATCH(n,RENDER_BATCH) #define BEGIN_BATCH_BLT(n) __BEGIN_BATCH(n,BLT_BATCH) +#define BEGIN_BATCH_BLT_TILED(n) \ +do { \ + if (INTEL_INFO(intel)->gen < 060) { \ + __BEGIN_BATCH(n, BLT_BATCH); \ + } else { \ + __BEGIN_BATCH(n+7, BLT_BATCH); \ + OUT_BATCH(MI_FLUSH_DW); \ + OUT_BATCH(0); \ + OUT_BATCH(0); \ + OUT_BATCH(0); \ + OUT_BATCH(MI_LOAD_REGISTER_IMM); \ + OUT_BATCH(BCS_SWCTRL); \ + OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 | \ + ((intel->BR_tiling[0] == I915_TILING_Y) ? BCS_SWCTRL_DST_Y : 0) | \ + ((intel->BR_tiling[1] == I915_TILING_Y) ? BCS_SWCTRL_SRC_Y : 0)); \ + } \ +} while (0) #define ADVANCE_BATCH() do { \ if (intel->batch_emitting == 0) \ |