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authorChris Wilson <chris@chris-wilson.co.uk>2013-07-26 09:35:06 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2013-07-28 14:49:07 +0100
commit45d4e8dcf9aee37015b1ee026997ed4dabdf112e (patch)
treec140efa6a28d80266849d08d5ea368419e95c977 /xvmc/shader/vld/read_field_x0y1_uv.g4i
parentab28526ea43728fb675448515e1519a970fb5f56 (diff)
uxa: Clear up the common intel directory
Move all the UXA backend specifc files into their own subdirectory. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'xvmc/shader/vld/read_field_x0y1_uv.g4i')
-rw-r--r--xvmc/shader/vld/read_field_x0y1_uv.g4i28
1 files changed, 28 insertions, 0 deletions
diff --git a/xvmc/shader/vld/read_field_x0y1_uv.g4i b/xvmc/shader/vld/read_field_x0y1_uv.g4i
new file mode 100644
index 00000000..ac8030b8
--- /dev/null
+++ b/xvmc/shader/vld/read_field_x0y1_uv.g4i
@@ -0,0 +1,28 @@
+/* GRF allocation:
+ g1~g30: constant buffer
+ g1~g2:intra IQ matrix
+ g3~g4:non intra IQ matrix
+ g5~g20:IDCT table
+ g31: thread payload
+ g58~g81:reference data
+ g82: thread payload backup
+ g83~g106:IDCT data
+ g115: message descriptor for reading reference data */
+
+mov (1) g115.8<1>UD 0x07000FUD {align1}; // 8*16/32=4
+send (16) 0 g40.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 4 {align1};//U
+send (16) 0 g45.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 4 {align1};//V
+mov (1) g115.8<1>UD 0xFUD {align1};
+add (1) g115.4<1>UD g115.4<1,1,1>UD 8UD {align1};
+send (16) 0 g44.0<1>UW g115<8,8,1>UW read(surface_u, 2, 0, 2) mlen 1 rlen 1 {align1};//U
+send (16) 0 g49.0<1>UW g115<8,8,1>UW read(surface_v, 2, 0, 2) mlen 1 rlen 1 {align1};//V
+
+avg (16) g32.0<1>UW g40.0<16,8,1>UB g41.0<16,8,1>UB {align1};
+avg (16) g33.0<1>UW g41.0<16,8,1>UB g42.0<16,8,1>UB {align1};
+avg (16) g34.0<1>UW g42.0<16,8,1>UB g43.0<16,8,1>UB {align1};
+avg (16) g35.0<1>UW g43.0<16,8,1>UB g44.0<16,8,1>UB {align1};
+
+avg (16) g36.0<1>UW g45.0<16,8,1>UB g46.0<16,8,1>UB {align1};
+avg (16) g37.0<1>UW g46.0<16,8,1>UB g47.0<16,8,1>UB {align1};
+avg (16) g38.0<1>UW g47.0<16,8,1>UB g48.0<16,8,1>UB {align1};
+avg (16) g39.0<1>UW g48.0<16,8,1>UB g49.0<16,8,1>UB {align1};