diff options
| -rw-r--r-- | src/uxa/intel_batchbuffer.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/uxa/intel_batchbuffer.c b/src/uxa/intel_batchbuffer.c index 4aabe48b..dedf7f87 100644 --- a/src/uxa/intel_batchbuffer.c +++ b/src/uxa/intel_batchbuffer.c @@ -183,16 +183,23 @@ void intel_batch_emit_flush(ScrnInfoPtr scrn) int flags; assert (!intel->in_batch_atomic); - assert (INTEL_INFO(intel)->gen < 0100); /* Big hammer, look to the pipelined flushes in future. */ - if ((INTEL_INFO(intel)->gen >= 060)) { + if ((INTEL_INFO(intel)->gen >= 0100)) { + /* Only BLT supported */ + BEGIN_BATCH_BLT(4); + OUT_BATCH(MI_FLUSH_DW | 2); + OUT_BATCH(0); /* address low */ + OUT_BATCH(0); /* address high */ + OUT_BATCH(0); /* dword data */ + ADVANCE_BATCH(); + } else if ((INTEL_INFO(intel)->gen >= 060)) { if (intel->current_batch == BLT_BATCH) { BEGIN_BATCH_BLT(4); OUT_BATCH(MI_FLUSH_DW | 2); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); + OUT_BATCH(0); /* address */ + OUT_BATCH(0); /* qword low */ + OUT_BATCH(0); /* qword high */ ADVANCE_BATCH(); } else { if ((INTEL_INFO(intel)->gen == 060)) { |