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AgeCommit message (Expand)Author
2011-05-30Whitespacing cleanup for intel_module.cChris Wilson
2011-05-30Add support for Ivybridge chipset.Eric Anholt
2011-05-30Remove the static list of PciChipset and construct it from SymTabRec instead.Eric Anholt
2011-05-30Use the existing deviceID -> name mapping in SymTabRec instead of duping it.Eric Anholt
2011-05-30Store the chipset info struct in the PCI match struct, instead of a switch().Eric Anholt
2011-05-29Ensure that the partial batch is flushed upon the blockhandlerChris Wilson
2011-05-29Add basic 30 bit depth supportJesse Barnes
2011-05-29i965/video: We need 150 dwords of space for video state emissionChris Wilson
2011-05-29intel: Beware the unsigned promotion when checking for batch overflowsChris Wilson
2011-05-29gen6: Invalidate texture cacheChris Wilson
2011-05-29i965: Avoid transform overheads for vertex emit where possibleChris Wilson
2011-05-29i965: Refactor to use constant sampler_state offsetsChris Wilson
2011-05-29i965: Reset vertex_id after every batchChris Wilson
2011-05-29i965: Always update last_floats_per_vertexChris Wilson
2011-05-29Take advantage of the kernel flush for dirty bo in the busy ioctlChris Wilson
2011-05-29Remove unused function 'intel_bo_alloc_for_data'Chris Wilson
2011-05-29Remove the unnecessary MI_FLUSH from the flush handlerChris Wilson
2011-05-29i965: segregate each vertex element into its own bufferChris Wilson
2011-05-29i965: Convert to relative relocations for stateChris Wilson
2011-05-29MI_LOAD_SCAN_LINES_INCL are inclusive and range [0, display height-1]Chris Wilson
2011-05-29946GZ is a 965G!Chris Wilson
2011-05-29Add a DRI2SwapEventPtr typedef for retro xserversChris Wilson
2011-05-29Cleanup gen2 tiling confusionDaniel Vetter
2011-05-29Use the per-generation batch context switch for atomic sequencesChris Wilson
2011-05-29dri: Disable page-flip between a tiled buffer and a linear scanoutChris Wilson
2011-05-29Give each user of tiling separate xorg.conf optionsChris Wilson
2011-05-29Fix relaxed tiling on gen2Daniel Vetter
2011-05-29i965: Fix off-by-one in assertChris Wilson
2011-05-29If the crtc is not enabled, then it can't be onChris Wilson
2011-05-29dri: Don't wait upon a NULL current modeChris Wilson
2011-05-29i830: amalgamate consecutive composites into a single primitiveChris Wilson
2011-05-29Remove the deprecated function 'XNFprintf'Chris Wilson
2011-05-29Undo: Disable BLT for i830 and 845GChris Wilson
2011-05-29i965: Mark sure we mark reused render targets as dirtyChris Wilson
2011-05-29snb: Only emit CC and DepthStencil bos once per batchChris Wilson
2011-05-29snb: Restore drawrect, we need the implicit flushChris Wilson
2011-05-29snb: Cache pixmap binding locationsChris Wilson
2011-05-29snb: Cache state between composite opsChris Wilson
2011-05-29snb: Emit more invariants only onceChris Wilson
2011-05-29Don't use hardware acceleration on Sandybridge rev 07 hardware or earlier.Matthias Hopf
2011-05-29Wait on the current buffer to complete when running synchronously.Chris Wilson
2011-04-04don't do batch_submits in uxa block handler if vtswitchedOwain G. Ainsworth
2011-04-04Move batch and render state initialisation to init/close screen instead ofOwain G. Ainsworth
2011-03-16i965: Amalgamate surface binding tablesChris Wilson
2011-03-16Disable BLT for i830 and 845GOwain G. Ainsworth
2011-03-16uxa: Relax fencing some more for gen3Chris Wilson
2011-03-16Fallback to shadow for Sandybridge if we don't have access to the BLTOwain G. Ainsworth
2011-03-16Flush BLT batches before starting an atomic RENDER batchChris Wilson
2011-03-16Fix build. oops.Owain G. Ainsworth
2011-03-16Support BLT acceleration on gen6Owain G. Ainsworth
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