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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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The compiler was simply warning that we defined the name prior to
including the original definition, so reorder.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Matthias Hopf <mhopf@suse.de>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
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To enable DRI we create GEM buffers for the client to render into with
hardware acceleration. In order to maintain coherency between any 2D
render operations with the independent 3D clients (this includes the
reading of 2D rasterisation by the direct rendering client, e.g.
compiz using texture_from_pixmap) we need to replace the shadow pixmap
with the GTT mapping. Therefore 2D rendering to a DRI buffer will be to
uncached memory and thus penalised -- but the direct rendering clients
will have full hardware acceleration.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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The driver is still built but is no longer under active development so
move it and supporting files to a new directory.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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The presumption is that we wish to keep the target hot, so
copy to a new bo and move that to the CPU in preference to
causing ping-pong of the original.
Also the gpu is much faster at detiling.
Before (PineView):
400000 trep @ 0.1128 msec ( 8860.0/sec): GetImage 10x10 square
18000 trep @ 1.3839 msec ( 723.0/sec): GetImage 100x100 square
800 trep @ 30.0987 msec ( 33.2/sec): GetImage 500x500 square
After: (PineView)
180000 trep @ 0.1478 msec ( 6770.0/sec): GetImage 10x10 square
60000 trep @ 0.4545 msec ( 2200.0/sec): GetImage 100x100 square
4000 trep @ 8.0739 msec ( 124.0/sec): GetImage 500x500 square
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This reverts commit 3f11bbec420080151406c203af292e55177e77d1.
For unknown reasons, enabling tiling for the glyph cache is causing
glyph corruption both across suspend and resume and VT switching, on a
wide range of chipsets (reports include both i8xx and gm45)
This strongly suggests that we are handling tiling, or updates to tiled
buffers, incorrectly across i915_gem_idle(). However, until we can find
the root cause, we want to fix this regression before the next stable
release, so simply revert this patch. :(
Fixes:
[Bug 25406] fonts garbled after resuming from suspend since 6729b508
http://bugs.freedesktop.org/show_bug.cgi?id=25406
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
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This is the beginning of the campaign to remove some of the absurd use of
Hungarian in the driver. Not that I don't like Hungarian, but I don't need
to know that pI830 is a pPointer.
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At this point, the only remaining feature regressions should be the lack of
overlay support (about to land), and the need to update the XVMC code to work
in the presence of KMS.
Acked-by: Keith Packard <keithp@keithp.com> (in principle)
Acked-by: Carl Worth <cworth@cworth.org> (in principle)
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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Desktop and mobile version of new chipsets are added.
Also do memory config like Intel 4 series chipset.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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CVS keywords, comments about how the source was once reformatted,
and the ad-hoc changelog comment in in i830_driver.c
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Depending on new server means these are always present.
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Signed-off-by: Alan Coopersmith <alan.coopersmith@sun.com>
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This is the intel video driver patch for a new chip, which is G33-like
and has some clocking setting related register changes. This patch adds
the pci id and DPLx/FPx register changes.
The gtt tool should just work to me, as the chip hasn't any changes
against G33 on this side.
Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Oops, my bad. Reverted 8d4bc36fae50b09a73ba2cfab920adb32141a358
since my kernel doesn't yet have the new param, committed
the revert by accident.
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Set alignments, tile settings and flags correctly in the 2D driver to support
tiled rendering. UXA's create pixmap function currently assumes the worst
about the alignment constraints; that should probably be fixed. Some of the
1M alignment fixes could probably be done more cleanly as well.
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Conflicts:
src/common.h
src/i830_hwmc.c
src/i830_video.c
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Those are identical that using one define is much clear.
And it can also apply fixes for GM45 too, which is missing with
origin define.
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libpciaccess (and the old X server PCI code as well) provides a function to
get the ROM contents. Code to use that was already present in the driver and
used if the INT10 function failed. Skip the INT10 and just use libpciaccess
as that eliminates several module loads and scary use of vm86.
Signed-off-by: Keith Packard <keithp@keithp.com>
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G41 is another 4 series chipset like G45/43.
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Thanks airlied!
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On new chip, DSPARB is controlled by hardware only.
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As xvmc rendering result has already been in fb, we shouldn't
do extra copy on it. Although special care is required for i915
xvmc surface pitch alignment, which must be at least 1KB aligned.
So video display function should take it into acount instead of
always setting Y pitch to be double of U/V pitch.
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Now, SDVO is only probed if the SDVO detected bit is set. If the SDVO probe
fails, but the detect bit is set, assume that it's an HDMI output.
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I want to hack on i830 for changing it into a compat path for batchbuffer
without having to worry about the i810 stuff getting broken.
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Several uses are actually left, which are determined by the X Server
interfaces we're implementing.
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Based on Maxim Levitsky's patch for the same. Many thanks to Maxim for
discovering that this features still works in recent hardware!
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Also add support on new chipset.
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libpciaccess has a new structure that holds the PCI identifier data; borrow
macros from the mga driver to work with either the old xf86-specific
structure or the new libpciaccess structure.
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which do have new host bridge ids
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Which have to use gfx vm offset fot setup overlay regs.
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