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path: root/src/i965_video.c
AgeCommit message (Expand)Author
2012-08-03uxa: fix 3DSTATE_PS to fill in number of samples for HaswellGwenole Beauchesne
2012-08-03uxa: set "Shader Channel Select" fields in surface state for HaswellGwenole Beauchesne
2012-08-03uxa: fix max PS threads shift value for HaswellGwenole Beauchesne
2012-07-26Reduce maximum thread count for IVB GT1 to avoid spontaneous combustionChris Wilson
2012-06-04uxa/i965: Silence static analyser by asserting the bo exists for the videoChris Wilson
2011-12-31uxa/video: Clear all state structures before uploadingChris Wilson
2011-12-31uxa: the video destination should be in the render write domainChris Wilson
2011-12-11uxa/video: Correct the offset of the binding table in the surface bufferChris Wilson
2011-12-09uxa/video: Use the common bo allocations and uploadChris Wilson
2011-11-14uxa/gen4+: Re-emit composite invariant after videoChris Wilson
2011-07-28render: Refactor to use newly shared pipeline setup code in i965_3d.c.Kenneth Graunke
2011-07-28Xv: Refactor out pipeline setup functions for future reuse in render.Kenneth Graunke
2011-06-24Xv: set up pipeline for Xv on IvybridgeXiang, Haihao
2011-06-24Xv: upload new shaders to GEM objects for Xv on IvybridgeXiang, Haihao
2011-06-24Xv: update SURFACE_STATE & SAMPLER_STATE for Xv on IvybridgeXiang, Haihao
2011-04-17i965/video: We need 150 dwords of space for video state emissionChris Wilson
2011-04-04Take advantage of the kernel flush for dirty bo in the busy ioctlChris Wilson
2011-02-17Fix IGD and IGDNG constants to be comprehensibleAdam Jackson
2011-02-12i965: Remove broken maximum base addresses from videoChris Wilson
2011-01-17Fix textured video when destination is larger than screenSimon Farnsworth
2010-11-01Xv: setup pipeline for Xv on SandybridgeXiang, Haihao
2010-11-01Xv: set the surface state base addressXiang, Haihao
2010-10-07Include a chipset generation number to clarify device specific paths.Chris Wilson
2010-06-25Rename common infrastructure to the intel namespace.Chris Wilson
2010-06-25i810: Move into a legacy directory.Chris Wilson
2010-06-21Emit the flush after a potential draw from the BlockHandler.Chris Wilson
2010-06-09Revert "xp:trapezoids"Chris Wilson
2010-06-08xp:trapezoidsChris Wilson
2010-05-24Kill paranoid assertions on every write into the batchbuffer.Chris Wilson
2010-05-17i830: Remove vestigal debugging ALWAYS_FLUSH and ALWAYS_SYNCChris Wilson
2010-04-08i965 Xv: fix chroma pitchDaniel Vetter
2010-03-04Xv: fixup relocation in i965_video.cDaniel Vetter
2010-01-07Xv: kill unnecessary parameters for hw PutImage functionsDaniel Vetter
2009-12-07batch: Ensure we send a MI_FLUSH in the block handler for TFPChris Wilson
2009-12-02Remove flush parameter from intel_batch_flush()Chris Wilson
2009-12-02Rename I830Sync() to intel_sync()Chris Wilson
2009-11-10Check that batch buffers are atomic.Chris Wilson
2009-10-14conf: Add debugging flush optionsChris Wilson
2009-10-08Rename the xv pPriv to adaptor_priv to reflect whose private it is.Eric Anholt
2009-10-08Call pPixmaps plain old pixmaps.Eric Anholt
2009-10-08Rename the xf86 screen private from pScrn to scrn.Eric Anholt
2009-10-08Rename the screen private from I830Ptr pI830 to intel_screen_private *intel.Eric Anholt
2009-10-06Move to kernel coding style.Eric Anholt
2009-10-05Remove error state dumping code.Eric Anholt
2009-10-05Xv: kill hw double buffering logicDaniel Vetter
2009-10-05Xv: use is_planar_fourcc helper some moreDaniel Vetter
2009-08-07Align tiled pixmap height so we don't address beyond the end of our buffers.Eric Anholt
2009-06-30Xv: fix domain usage for binding table on i965+ chipsZhenyu Wang
2009-06-30Add XV support on IGDNGZhenyu Wang
2009-05-01Hold reference to video binding table until all rects are painted.Keith Packard
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