RADEON: Implement proper (hopefully) BIOS/DRIVER interaction for COM bios

Tested on my M10-based laptop.

8 files changed, 368 insertions, 99 deletions

diff --git a/src/atombios_output.c b/src/atombios_output.c
index 6eb8776..921a386 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -428,28 +428,6 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
 {
     RADEONOutputPrivatePtr radeon_output = output->driver_private;
     RADEONInfoPtr info       = RADEONPTR(output->scrn);
-    unsigned char *RADEONMMIO = info->MMIO;
-    int tmp, count;
-
-#if 1
-    /* try to grab card lock or at least somethings that looks like a lock
-     * if it fails more than 5 times with 1000ms wait btw each try than we
-     * assume we can process.
-     */
-    count = 0;
-    tmp = INREG(RADEON_BIOS_6_SCRATCH);
-    while((tmp & 0x100) && (count < 5)) {
-        tmp = INREG(RADEON_BIOS_6_SCRATCH);
-        count++;
-        usleep(1000);
-    }
-    if (count >= 5) {
-        xf86DrvMsg(output->scrn->scrnIndex, X_INFO,
-                   "%s (WARNING) failed to grab card lock process anyway.\n",
-                   __func__);
-    }
-    OUTREG(RADEON_BIOS_6_SCRATCH, tmp | 0x100);
-#endif
 
     ErrorF("AGD: output dpms %d\n", mode);
 
@@ -479,11 +457,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
        if (radeon_output->devices & ATOM_DEVICE_TV1_SUPPORT)
 	   atombios_device_dpms(output, ATOM_DEVICE_TV1_SUPPORT, mode);
    }
-#if 1
-    /* release card lock */
-    tmp = INREG(RADEON_BIOS_6_SCRATCH);
-    OUTREG(RADEON_BIOS_6_SCRATCH, tmp & (~0x100));
-#endif
+
 }
 
 static void
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 53f0374..06ad60c 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -491,17 +491,6 @@ RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
     save->grph2_buffer_cntl  = INREG(RADEON_GRPH2_BUFFER_CNTL);
 }
 
-void
-RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
-
-    save->bios_4_scratch       = INREG(RADEON_BIOS_4_SCRATCH);
-    save->bios_5_scratch       = INREG(RADEON_BIOS_5_SCRATCH);
-    save->bios_6_scratch       = INREG(RADEON_BIOS_6_SCRATCH);
-}
-
 /* Read CRTC registers */
 void
 RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
@@ -1304,18 +1293,6 @@ RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save,
 }
 
 static void
-RADEONInitBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
-{
-    RADEONInfoPtr  info      = RADEONPTR(pScrn);
-
-    /* tell the bios not to muck with the hardware on events */
-    save->bios_4_scratch = 0x4; /* 0x4 needed for backlight */
-    save->bios_5_scratch = (info->SavedReg->bios_5_scratch & 0xff) | 0xff00; /* bits 0-3 keep backlight level */
-    save->bios_6_scratch = info->SavedReg->bios_6_scratch | 0x40000000;
-
-}
-
-static void
 radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore)
 {
     /* pixclks_cntl controls tv clock routing */
@@ -1715,8 +1692,6 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 	}
     }
 
-    if (info->IsMobility)
-	RADEONInitBIOSRegisters(pScrn, info->ModeReg);
 
     ErrorF("init memmap\n");
     RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
@@ -1773,9 +1748,6 @@ legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
 	}
     }
 
-    if (info->IsMobility)
-	RADEONRestoreBIOSRegisters(pScrn, info->ModeReg);
-
     ErrorF("restore memmap\n");
     RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
     ErrorF("restore common\n");
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 7ade772..bac1b67 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -160,26 +160,6 @@ RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
 }
 
 void
-RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
-{
-    RADEONInfoPtr  info       = RADEONPTR(pScrn);
-    unsigned char *RADEONMMIO = info->MMIO;
-    CARD32 bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
-    CARD32 bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH);
-
-    OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
-    bios_5_scratch &= 0xF;
-    bios_5_scratch |= (restore->bios_5_scratch & ~0xF);
-    OUTREG(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
-    if (restore->bios_6_scratch & 0x40000000)
-	bios_6_scratch |= 0x40000000;
-    else
-	bios_6_scratch &= ~0x40000000;
-    OUTREG(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
-
-}
-
-void
 RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
 {
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
diff --git a/src/radeon.h b/src/radeon.h
index 7950ac8..7d63f28 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -829,8 +829,6 @@ extern void        RADEONRestoreFP2Registers(ScrnInfoPtr pScrn,
 					     RADEONSavePtr restore);
 extern void        RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn,
 					      RADEONSavePtr restore);
-extern void        RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn,
-					      RADEONSavePtr restore);
 extern void        RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn,
 					     RADEONSavePtr restore);
 extern void        RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index cf32d40..764f01f 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -131,8 +131,6 @@ RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, DisplayModePtr pMode);
 extern void
 RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 extern void
-RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
-extern void
 RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 extern void
 RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save);
@@ -2978,6 +2976,40 @@ RADEONPointerMoved(int index, int x, int y)
     (*info->PointerMoved)(index, newX, newY);
 }
 
+static void
+RADEONInitBIOSRegisters(ScrnInfoPtr pScrn)
+{
+    RADEONInfoPtr  info  = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONSavePtr save = info->ModeReg;
+
+    save->bios_0_scratch = info->SavedReg->bios_0_scratch;
+    save->bios_1_scratch = info->SavedReg->bios_1_scratch;
+    save->bios_2_scratch = info->SavedReg->bios_2_scratch;
+    save->bios_3_scratch = info->SavedReg->bios_3_scratch;
+    save->bios_4_scratch = info->SavedReg->bios_4_scratch;
+    save->bios_5_scratch = info->SavedReg->bios_5_scratch;
+    save->bios_6_scratch = info->SavedReg->bios_6_scratch;
+    save->bios_7_scratch = info->SavedReg->bios_7_scratch;
+
+    if (info->IsAtomBios) {
+	
+    } else {
+	/* let the bios control the backlight */
+	save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
+	/* tell the bios not to handle mode switching */
+	save->bios_6_scratch |= RADEON_DISPLAY_SWITCHING_DIS;
+	/* tell the bios a driver is loaded */
+	save->bios_7_scratch |= RADEON_DRV_LOADED;
+
+	OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch);
+	OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
+	//OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch);
+    }
+
+}
+
+
 /* Called at the start of each server generation. */
 Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
                                 int argc, char **argv)
@@ -3025,6 +3057,9 @@ Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
 
     RADEONSave(pScrn);
 
+    /* set initial bios scratch reg state */
+    RADEONInitBIOSRegisters(pScrn);
+
     /* blank the outputs/crtcs */
     RADEONBlank(pScrn);
 
@@ -4304,6 +4339,38 @@ void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore)
     OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl);
 }
 
+static void
+RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
+{
+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+
+    OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch);
+    OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch);
+    OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch);
+    OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch);
+    OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
+    OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
+    OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch);
+    OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch);
+}
+
+static void
+RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
+{
+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+
+    save->bios_0_scratch       = INREG(RADEON_BIOS_0_SCRATCH);
+    save->bios_1_scratch       = INREG(RADEON_BIOS_1_SCRATCH);
+    save->bios_2_scratch       = INREG(RADEON_BIOS_2_SCRATCH);
+    save->bios_3_scratch       = INREG(RADEON_BIOS_3_SCRATCH);
+    save->bios_4_scratch       = INREG(RADEON_BIOS_4_SCRATCH);
+    save->bios_5_scratch       = INREG(RADEON_BIOS_5_SCRATCH);
+    save->bios_6_scratch       = INREG(RADEON_BIOS_6_SCRATCH);
+    save->bios_7_scratch       = INREG(RADEON_BIOS_7_SCRATCH);
+}
+
 /* Save everything needed to restore the original VC state */
 static void RADEONSave(ScrnInfoPtr pScrn)
 {
@@ -4349,7 +4416,6 @@ static void RADEONSave(ScrnInfoPtr pScrn)
 	RADEONSavePLLRegisters(pScrn, save);
 	RADEONSaveCrtcRegisters(pScrn, save);
 	RADEONSaveFPRegisters(pScrn, save);
-	RADEONSaveBIOSRegisters(pScrn, save);
 	RADEONSaveDACRegisters(pScrn, save);
 	if (pRADEONEnt->HasCRTC2) {
 	    RADEONSaveCrtc2Registers(pScrn, save);
@@ -4359,7 +4425,8 @@ static void RADEONSave(ScrnInfoPtr pScrn)
 	    RADEONSaveTVRegisters(pScrn, save);
     }
 
-	RADEONSaveSurfaces(pScrn, save);
+    RADEONSaveBIOSRegisters(pScrn, save);
+    RADEONSaveSurfaces(pScrn, save);
 
 }
 
@@ -4394,27 +4461,27 @@ void RADEONRestore(ScrnInfoPtr pScrn)
 	OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
 	OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl);
 
-    if (!info->IsSecondary) {
-	RADEONRestoreMemMapRegisters(pScrn, restore);
-	RADEONRestoreCommonRegisters(pScrn, restore);
+	if (!info->IsSecondary) {
+	    RADEONRestoreMemMapRegisters(pScrn, restore);
+	    RADEONRestoreCommonRegisters(pScrn, restore);
 
-	if (pRADEONEnt->HasCRTC2) {
-	    RADEONRestoreCrtc2Registers(pScrn, restore);
-	    RADEONRestorePLL2Registers(pScrn, restore);
-	}
+	    if (pRADEONEnt->HasCRTC2) {
+		RADEONRestoreCrtc2Registers(pScrn, restore);
+		RADEONRestorePLL2Registers(pScrn, restore);
+	    }
 
-	RADEONRestoreBIOSRegisters(pScrn, restore);
-	RADEONRestoreCrtcRegisters(pScrn, restore);
-	RADEONRestorePLLRegisters(pScrn, restore);
-	RADEONRestoreRMXRegisters(pScrn, restore);
-	RADEONRestoreFPRegisters(pScrn, restore);
-	RADEONRestoreFP2Registers(pScrn, restore);
-	RADEONRestoreLVDSRegisters(pScrn, restore);
+	    RADEONRestoreCrtcRegisters(pScrn, restore);
+	    RADEONRestorePLLRegisters(pScrn, restore);
+	    RADEONRestoreRMXRegisters(pScrn, restore);
+	    RADEONRestoreFPRegisters(pScrn, restore);
+	    RADEONRestoreFP2Registers(pScrn, restore);
+	    RADEONRestoreLVDSRegisters(pScrn, restore);
 
-	if (info->InternalTVOut)
-	    RADEONRestoreTVRegisters(pScrn, restore);
-    }
+	    if (info->InternalTVOut)
+		RADEONRestoreTVRegisters(pScrn, restore);
+	}
 
+	RADEONRestoreBIOSRegisters(pScrn, restore);
 	RADEONRestoreSurfaces(pScrn, restore);
     }
 
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 248f94a..4fcfb2f 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -186,7 +186,12 @@ extern RADEONMonitorType atombios_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr ou
 extern RADEONMonitorType legacy_dac_detect(ScrnInfoPtr pScrn, xf86OutputPtr output);
 extern int atombios_external_tmds_setup(xf86OutputPtr output, DisplayModePtr mode);
 extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr);
-
+static void
+radeon_bios_output_dpms(xf86OutputPtr output, int mode);
+static void
+radeon_bios_output_crtc(xf86OutputPtr output);
+static void
+radeon_bios_output_lock(xf86OutputPtr output, Bool lock);
 
 void RADEONPrintPortMap(ScrnInfoPtr pScrn)
 {
@@ -480,6 +485,8 @@ radeon_dpms(xf86OutputPtr output, int mode)
     } else {
 	legacy_output_dpms(output, mode);
     }
+    radeon_bios_output_dpms(output, mode);
+
 }
 
 static void
@@ -625,6 +632,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
 static void
 radeon_mode_prepare(xf86OutputPtr output)
 {
+    radeon_bios_output_lock(output, TRUE);
 }
 
 static void
@@ -637,6 +645,7 @@ radeon_mode_set(xf86OutputPtr output, DisplayModePtr mode,
 	atombios_output_mode_set(output, mode, adjusted_mode);
     else
 	legacy_output_mode_set(output, mode, adjusted_mode);
+    radeon_bios_output_crtc(output);
 
 }
 
@@ -644,6 +653,207 @@ static void
 radeon_mode_commit(xf86OutputPtr output)
 {
     radeon_dpms(output, DPMSModeOn);
+    radeon_bios_output_lock(output, FALSE);
+}
+
+static void
+radeon_bios_output_lock(xf86OutputPtr output, Bool lock)
+{
+    ScrnInfoPtr	    pScrn = output->scrn;
+    RADEONInfoPtr info = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONSavePtr save = info->ModeReg;
+
+    if (info->IsAtomBios) {
+	int tmp, count;
+
+	if (lock) {
+	    /* try to grab card lock or at least somethings that looks like a lock
+	     * if it fails more than 5 times with 1000ms wait btw each try than we
+	     * assume we can process.
+	     */
+	    count = 0;
+	    tmp = INREG(RADEON_BIOS_6_SCRATCH);
+	    while((tmp & 0x100) && (count < 5)) {
+		tmp = INREG(RADEON_BIOS_6_SCRATCH);
+		count++;
+		usleep(1000);
+	    }
+	    if (count >= 5) {
+		xf86DrvMsg(output->scrn->scrnIndex, X_INFO,
+			   "%s (WARNING) failed to grab card lock process anyway.\n",
+			   __func__);
+	    }
+	    OUTREG(RADEON_BIOS_6_SCRATCH, tmp | 0x100);
+	} else {
+	    /* release card lock */
+	    tmp = INREG(RADEON_BIOS_6_SCRATCH);
+	    OUTREG(RADEON_BIOS_6_SCRATCH, tmp & (~0x100));
+	}
+    } else {
+	if (lock) {
+	    save->bios_6_scratch |= (RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE);
+	} else {
+	    save->bios_6_scratch &= ~(RADEON_DRIVER_CRITICAL | RADEON_ACC_MODE_CHANGE);
+	}
+	OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
+    }
+
+}
+
+static void
+radeon_bios_output_dpms(xf86OutputPtr output, int mode)
+{
+    ScrnInfoPtr	    pScrn = output->scrn;
+    RADEONInfoPtr info = RADEONPTR(pScrn);
+    RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONSavePtr save = info->ModeReg;
+
+    if (info->IsAtomBios) {
+
+    } else {
+	if (mode == DPMSModeOn) {
+	    save->bios_6_scratch &= ~(RADEON_DPMS_MASK | RADEON_SCREEN_BLANKING);
+	    save->bios_6_scratch |= RADEON_DPMS_ON;
+	    if (radeon_output->MonType == MT_STV ||
+		radeon_output->MonType == MT_CTV) {
+		save->bios_5_scratch |= RADEON_TV1_ON;
+		save->bios_6_scratch |= RADEON_TV_DPMS_ON;
+	    } else if (radeon_output->MonType == MT_CRT) {
+		if (radeon_output->DACType == DAC_PRIMARY)
+		    save->bios_5_scratch |= RADEON_CRT1_ON;
+		else
+		    save->bios_5_scratch |= RADEON_CRT2_ON;
+		save->bios_6_scratch |= RADEON_CRT_DPMS_ON;
+	    } else if (radeon_output->MonType == MT_LCD) {
+		save->bios_5_scratch |= RADEON_LCD1_ON;
+		save->bios_6_scratch |= RADEON_LCD_DPMS_ON;
+	    } else if (radeon_output->MonType == MT_DFP) {
+		if (radeon_output->TMDSType == TMDS_INT)
+		    save->bios_5_scratch |= RADEON_DFP1_ON;
+		else
+		    save->bios_5_scratch |= RADEON_DFP2_ON;
+		save->bios_6_scratch |= RADEON_DFP_DPMS_ON;
+	    }
+	} else {
+	    save->bios_6_scratch &= ~RADEON_DPMS_MASK;
+	    save->bios_6_scratch |= (RADEON_DPMS_OFF | RADEON_SCREEN_BLANKING);
+	    if (radeon_output->MonType == MT_STV ||
+		radeon_output->MonType == MT_CTV) {
+		save->bios_5_scratch &= ~RADEON_TV1_ON;
+		save->bios_6_scratch &= ~RADEON_TV_DPMS_ON;
+	    } else if (radeon_output->MonType == MT_CRT) {
+		if (radeon_output->DACType == DAC_PRIMARY)
+		    save->bios_5_scratch &= ~RADEON_CRT1_ON;
+		else
+		    save->bios_5_scratch &= ~RADEON_CRT2_ON;
+		save->bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
+	    } else if (radeon_output->MonType == MT_LCD) {
+		save->bios_5_scratch &= ~RADEON_LCD1_ON;
+		save->bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
+	    } else if (radeon_output->MonType == MT_DFP) {
+		if (radeon_output->TMDSType == TMDS_INT)
+		    save->bios_5_scratch &= ~RADEON_DFP1_ON;
+		else
+		    save->bios_5_scratch &= ~RADEON_DFP2_ON;
+		save->bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
+	    }
+	}
+	OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch);
+	OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
+    }
+}
+
+static void
+radeon_bios_output_crtc(xf86OutputPtr output)
+{
+    ScrnInfoPtr	    pScrn = output->scrn;
+    RADEONInfoPtr info = RADEONPTR(pScrn);
+    RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONSavePtr save = info->ModeReg;
+    xf86CrtcPtr crtc = output->crtc;
+    RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+
+    if (info->IsAtomBios) {
+
+    } else {
+	if (radeon_output->MonType == MT_STV ||
+	    radeon_output->MonType == MT_CTV) {
+	    save->bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
+	    save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_TV1_CRTC_SHIFT);
+	} else if (radeon_output->MonType == MT_CRT) {
+	    if (radeon_output->DACType == DAC_PRIMARY) {
+		save->bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
+		save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT1_CRTC_SHIFT);
+	    } else {
+		save->bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
+		save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT2_CRTC_SHIFT);
+	    }
+	} else if (radeon_output->MonType == MT_LCD) {
+	    save->bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
+	    save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_LCD1_CRTC_SHIFT);
+	} else if (radeon_output->MonType == MT_DFP) {
+	    if (radeon_output->TMDSType == TMDS_INT) {
+		save->bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
+		save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP1_CRTC_SHIFT);
+	    } else {
+		save->bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
+		save->bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP2_CRTC_SHIFT);
+	    }
+	}
+	OUTREG(RADEON_BIOS_5_SCRATCH, save->bios_5_scratch);
+    }
+}
+
+static void
+radeon_bios_output_connected(xf86OutputPtr output, Bool connected)
+{
+    ScrnInfoPtr	    pScrn = output->scrn;
+    RADEONInfoPtr info = RADEONPTR(pScrn);
+    RADEONOutputPrivatePtr radeon_output = output->driver_private;
+    unsigned char *RADEONMMIO = info->MMIO;
+    RADEONSavePtr save = info->ModeReg;
+
+    if (info->IsAtomBios) {
+
+    } else {
+	if (connected) {
+	    if (radeon_output->MonType == MT_STV)
+		save->bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
+	    else if (radeon_output->MonType == MT_CTV)
+		save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP;
+	    else if (radeon_output->MonType == MT_CRT) {
+		if (radeon_output->DACType == DAC_PRIMARY)
+		    save->bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
+		else
+		    save->bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
+	    } else if (radeon_output->MonType == MT_LCD)
+		save->bios_4_scratch |= RADEON_LCD1_ATTACHED;
+	    else if (radeon_output->MonType == MT_DFP) {
+		if (radeon_output->TMDSType == TMDS_INT)
+		    save->bios_4_scratch |= RADEON_DFP1_ATTACHED;
+		else
+		    save->bios_4_scratch |= RADEON_DFP2_ATTACHED;
+	    }
+	} else {
+	    if (OUTPUT_IS_TV)
+		save->bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
+	    else if (radeon_output->DACType == DAC_TVDAC)
+		save->bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
+	    if (radeon_output->DACType == DAC_PRIMARY)
+		save->bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
+	    if (radeon_output->type == OUTPUT_LVDS)
+		save->bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
+	    if (radeon_output->TMDSType == TMDS_INT)
+		save->bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
+	    if (radeon_output->TMDSType == TMDS_EXT)
+		save->bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
+	}
+	OUTREG(RADEON_BIOS_4_SCRATCH, save->bios_4_scratch);
+    }
+
 }
 
 static xf86OutputStatus
@@ -655,6 +865,7 @@ radeon_detect(xf86OutputPtr output)
     Bool connected = TRUE;
 
     radeon_output->MonType = MT_UNKNOWN;
+    radeon_bios_output_connected(output, FALSE);
     RADEONConnectorFindMonitor(pScrn, output);
 
     /* nothing connected, light up some defaults so the server comes up */
@@ -680,6 +891,8 @@ radeon_detect(xf86OutputPtr output)
 	}
     }
 
+    radeon_bios_output_connected(output, TRUE);
+
     /* set montype so users can force outputs on even if detection fails */
     if (radeon_output->MonType == MT_NONE) {
 	connected = FALSE;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index df87dab..a3cf1fc 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -385,9 +385,16 @@ typedef struct {
     CARD32            cap0_trig_cntl;
     CARD32            cap1_trig_cntl;
     CARD32            bus_cntl;
+
+    CARD32            bios_0_scratch;
+    CARD32            bios_1_scratch;
+    CARD32            bios_2_scratch;
+    CARD32            bios_3_scratch;
     CARD32            bios_4_scratch;
     CARD32            bios_5_scratch;
     CARD32            bios_6_scratch;
+    CARD32            bios_7_scratch;
+
     CARD32            surface_cntl;
     CARD32            surfaces[8][3];
     CARD32            mc_agp_location;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 8d45d7b..ec2a5ac 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -130,13 +130,71 @@
 
 #define RADEON_BASE_CODE                    0x0f0b
 #define RADEON_BIOS_0_SCRATCH               0x0010
+#       define RADEON_FP_PANEL_SCALABLE     (1 << 16)
+#       define RADEON_FP_PANEL_SCALE_EN     (1 << 17)
+#       define RADEON_FP_CHIP_SCALE_EN      (1 << 18)
+#       define RADEON_DRIVER_BRIGHTNESS_EN  (1 << 26)
+#       define RADEON_DISPLAY_ROT_MASK      (3 << 28)
+#       define RADEON_DISPLAY_ROT_00        (0 << 28)
+#       define RADEON_DISPLAY_ROT_90        (1 << 28)
+#       define RADEON_DISPLAY_ROT_180       (2 << 28)
+#       define RADEON_DISPLAY_ROT_270       (3 << 28)
 #define RADEON_BIOS_1_SCRATCH               0x0014
 #define RADEON_BIOS_2_SCRATCH               0x0018
 #define RADEON_BIOS_3_SCRATCH               0x001c
 #define RADEON_BIOS_4_SCRATCH               0x0020
+#       define RADEON_CRT1_ATTACHED_MASK    (3 << 0)
+#       define RADEON_CRT1_ATTACHED_MONO    (1 << 0)
+#       define RADEON_CRT1_ATTACHED_COLOR   (2 << 0)
+#       define RADEON_LCD1_ATTACHED         (1 << 2)
+#       define RADEON_DFP1_ATTACHED         (1 << 3)
+#       define RADEON_TV1_ATTACHED_MASK     (3 << 4)
+#       define RADEON_TV1_ATTACHED_COMP     (1 << 4)
+#       define RADEON_TV1_ATTACHED_SVIDEO   (2 << 4)
+#       define RADEON_CRT2_ATTACHED_MASK    (3 << 8)
+#       define RADEON_CRT2_ATTACHED_MONO    (1 << 8)
+#       define RADEON_CRT2_ATTACHED_COLOR   (2 << 8)
+#       define RADEON_DFP2_ATTACHED         (1 << 11)
 #define RADEON_BIOS_5_SCRATCH               0x0024
+#       define RADEON_LCD1_ON               (1 << 0)
+#       define RADEON_CRT1_ON               (1 << 1)
+#       define RADEON_TV1_ON                (1 << 2)
+#       define RADEON_DFP1_ON               (1 << 3)
+#       define RADEON_CRT2_ON               (1 << 5)
+#       define RADEON_CV1_ON                (1 << 6)
+#       define RADEON_DFP2_ON               (1 << 7)
+#       define RADEON_LCD1_CRTC_MASK        (1 << 8)
+#       define RADEON_LCD1_CRTC_SHIFT       8
+#       define RADEON_CRT1_CRTC_MASK        (1 << 9)
+#       define RADEON_CRT1_CRTC_SHIFT       9
+#       define RADEON_TV1_CRTC_MASK         (1 << 10)
+#       define RADEON_TV1_CRTC_SHIFT        10
+#       define RADEON_DFP1_CRTC_MASK        (1 << 11)
+#       define RADEON_DFP1_CRTC_SHIFT       11
+#       define RADEON_CRT2_CRTC_MASK        (1 << 12)
+#       define RADEON_CRT2_CRTC_SHIFT       12
+#       define RADEON_CV1_CRTC_MASK         (1 << 13)
+#       define RADEON_CV1_CRTC_SHIFT        13
+#       define RADEON_DFP2_CRTC_MASK        (1 << 14)
+#       define RADEON_DFP2_CRTC_SHIFT       14
 #define RADEON_BIOS_6_SCRATCH               0x0028
+#       define RADEON_ACC_MODE_CHANGE       (1 << 2)
+#       define RADEON_EXT_DESKTOP_MODE      (1 << 3)
+#       define RADEON_LCD_DPMS_ON           (1 << 20)
+#       define RADEON_CRT_DPMS_ON           (1 << 21)
+#       define RADEON_TV_DPMS_ON            (1 << 22)
+#       define RADEON_DFP_DPMS_ON           (1 << 23)
+#       define RADEON_DPMS_MASK             (3 << 24)
+#       define RADEON_DPMS_ON               (0 << 24)
+#       define RADEON_DPMS_STANDBY          (1 << 24)
+#       define RADEON_DPMS_SUSPEND          (2 << 24)
+#       define RADEON_DPMS_OFF              (3 << 24)
+#       define RADEON_SCREEN_BLANKING       (1 << 26)
+#       define RADEON_DRIVER_CRITICAL       (1 << 27)
+#       define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
 #define RADEON_BIOS_7_SCRATCH               0x002c
+#       define RADEON_SYS_HOTKEY            (1 << 10)
+#       define RADEON_DRV_LOADED            (1 << 12)
 #define RADEON_BIOS_ROM                     0x0f30 /* PCI */
 #define RADEON_BIST                         0x0f0f /* PCI */
 #define RADEON_BRUSH_DATA0                  0x1480