diff options
| author | Alex Deucher <alex@botch2.(none)> | 2007-10-03 22:19:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alex@botch2.(none)> | 2007-10-03 22:19:16 -0400 |
| commit | bfede412b3a3cd11769a580b167c528734146096 (patch) | |
| tree | c449c30e0d11d8f1bcc3adeb19dcc05f0baf4080 /src | |
| parent | 597dffce9bdc200003d0be880235258386a0bdd7 (diff) | |
RADEON: minor fixes for external TMDS
Diffstat (limited to 'src')
| -rw-r--r-- | src/radeon_output.c | 12 | ||||
| -rw-r--r-- | src/radeon_reg.h | 4 |
2 files changed, 10 insertions, 6 deletions
diff --git a/src/radeon_output.c b/src/radeon_output.c index 3f8b772..a6da78e 100644 --- a/src/radeon_output.c +++ b/src/radeon_output.c @@ -865,13 +865,15 @@ static void RADEONInitFP2Registers(xf86OutputPtr output, RADEONSavePtr save, RADEON_FP2_DVO_EN | RADEON_FP2_DVO_RATE_SEL_SDR); -#if 0 - /* XXX: these may be chip specific */ - save->fp2_gen_cntl |= (1 << 22) | R200_FP2_DVO_CLOCK_MODE_SINGLE; - if (mode->Clock > 165000) - save->fp2_gen_cntl |= R200_FP2_DVO_DUAL_CHANNEL_EN; + /* XXX: these may be oem specific */ + if (IS_R300_VARIANT) { + save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; +#if 0 + if (mode->Clock > 165000) + save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN; #endif + } if (IsPrimary) { if ((info->ChipFamily == CHIP_FAMILY_R200) || IS_R300_VARIANT) { diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 96adb22..2653339 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -780,7 +780,7 @@ # define RADEON_FP2_PANEL_FORMAT (1 << 3) # define RADEON_FP2_DETECT_SENSE (1 << 8) # define R200_FP2_SOURCE_SEL_MASK (3 << 10) -# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) # define R200_FP2_SOURCE_SEL_RMX (2 << 10) # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) @@ -796,6 +796,8 @@ # define RADEON_FP2_DVO_EN (1 << 25) # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) +# define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) +# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 #define RADEON_FP_HORZ_STRETCH 0x028c |