diff options
| -rw-r--r-- | src/AtomBios/CD_Operations.c | 954 | ||||
| -rw-r--r-- | src/AtomBios/Decoder.c | 235 | ||||
| -rw-r--r-- | src/AtomBios/hwserv_drv.c | 348 | ||||
| -rw-r--r-- | src/AtomBios/includes/CD_Common_Types.h | 154 | ||||
| -rw-r--r-- | src/AtomBios/includes/CD_Definitions.h | 49 | ||||
| -rw-r--r-- | src/AtomBios/includes/CD_Opcodes.h | 181 | ||||
| -rw-r--r-- | src/AtomBios/includes/CD_Structs.h | 464 | ||||
| -rw-r--r-- | src/AtomBios/includes/CD_binding.h | 46 | ||||
| -rw-r--r-- | src/AtomBios/includes/CD_hw_services.h | 318 | ||||
| -rw-r--r-- | src/AtomBios/includes/Decoder.h | 86 | ||||
| -rw-r--r-- | src/AtomBios/includes/ObjectID.h | 484 | ||||
| -rw-r--r-- | src/AtomBios/includes/atombios.h | 4436 | ||||
| -rw-r--r-- | src/AtomBios/includes/regsdef.h | 25 | ||||
| -rw-r--r-- | src/ati_pciids_gen.h | 358 | ||||
| -rw-r--r-- | src/pcidb/ati_pciids.csv | 359 | ||||
| -rwxr-xr-x | src/pcidb/parse_pci_ids.pl | 102 | ||||
| -rw-r--r-- | src/radeon_chipinfo_gen.h | 279 | ||||
| -rw-r--r-- | src/radeon_chipset_gen.h | 280 | ||||
| -rw-r--r-- | src/radeon_pci_chipset_gen.h | 280 | ||||
| -rw-r--r-- | src/radeon_pci_device_match_gen.h | 280 |
20 files changed, 0 insertions, 9718 deletions
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c deleted file mode 100644 index 1e48f81..0000000 --- a/src/AtomBios/CD_Operations.c +++ /dev/null @@ -1,954 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - -Module Name: - - CD_Operations.c - -Abstract: - - Functions Implementing Command Operations and other common functions - -Revision History: - - NEG:27.09.2002 Initiated. ---*/ -#define __SW_4 - -#include "Decoder.h" -#include "atombios.h" - - - -VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData); -UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable); - - -WRITE_IO_FUNCTION WritePCIFunctions[8] = { - WritePCIReg32, - WritePCIReg16, WritePCIReg16, WritePCIReg16, - WritePCIReg8,WritePCIReg8,WritePCIReg8,WritePCIReg8 -}; -WRITE_IO_FUNCTION WriteIOFunctions[8] = { - WriteSysIOReg32, - WriteSysIOReg16,WriteSysIOReg16,WriteSysIOReg16, - WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8,WriteSysIOReg8 -}; -READ_IO_FUNCTION ReadPCIFunctions[8] = { - (READ_IO_FUNCTION)ReadPCIReg32, - (READ_IO_FUNCTION)ReadPCIReg16, - (READ_IO_FUNCTION)ReadPCIReg16, - (READ_IO_FUNCTION)ReadPCIReg16, - (READ_IO_FUNCTION)ReadPCIReg8, - (READ_IO_FUNCTION)ReadPCIReg8, - (READ_IO_FUNCTION)ReadPCIReg8, - (READ_IO_FUNCTION)ReadPCIReg8 -}; -READ_IO_FUNCTION ReadIOFunctions[8] = { - (READ_IO_FUNCTION)ReadSysIOReg32, - (READ_IO_FUNCTION)ReadSysIOReg16, - (READ_IO_FUNCTION)ReadSysIOReg16, - (READ_IO_FUNCTION)ReadSysIOReg16, - (READ_IO_FUNCTION)ReadSysIOReg8, - (READ_IO_FUNCTION)ReadSysIOReg8, - (READ_IO_FUNCTION)ReadSysIOReg8, - (READ_IO_FUNCTION)ReadSysIOReg8 -}; -READ_IO_FUNCTION GetParametersDirectArray[8]={ - GetParametersDirect32, - GetParametersDirect16,GetParametersDirect16,GetParametersDirect16, - GetParametersDirect8,GetParametersDirect8,GetParametersDirect8, - GetParametersDirect8 -}; - -COMMANDS_DECODER PutDataFunctions[6] = { - PutDataRegister, - PutDataPS, - PutDataWS, - PutDataFB, - PutDataPLL, - PutDataMC -}; -CD_GET_PARAMETERS GetDestination[6] = { - GetParametersRegister, - GetParametersPS, - GetParametersWS, - GetParametersFB, - GetParametersPLL, - GetParametersMC -}; - -COMMANDS_DECODER SkipDestination[6] = { - SkipParameters16, - SkipParameters8, - SkipParameters8, - SkipParameters8, - SkipParameters8, - SkipParameters8 -}; - -CD_GET_PARAMETERS GetSource[8] = { - GetParametersRegister, - GetParametersPS, - GetParametersWS, - GetParametersFB, - GetParametersIndirect, - GetParametersDirect, - GetParametersPLL, - GetParametersMC -}; - -UINT32 AlignmentMask[8] = {0xFFFFFFFF,0xFFFF,0xFFFF,0xFFFF,0xFF,0xFF,0xFF,0xFF}; -UINT8 SourceAlignmentShift[8] = {0,0,8,16,0,8,16,24}; -UINT8 DestinationAlignmentShift[4] = {0,8,16,24}; - -#define INDIRECTIO_ID 1 -#define INDIRECTIO_END_OF_ID 9 - -VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_MOVE(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT32 temp); -VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - -INDIRECT_IO_PARSER_COMMANDS IndirectIOParserCommands[10]={ - {IndirectIOCommand,1}, - {IndirectIOCommand,2}, - {ReadIndReg32,3}, - {WriteIndReg32,3}, - {IndirectIOCommand_CLEAR,3}, - {IndirectIOCommand_SET,3}, - {IndirectIOCommand_MOVE_INDEX,4}, - {IndirectIOCommand_MOVE_ATTR,4}, - {IndirectIOCommand_MOVE_DATA,4}, - {IndirectIOCommand,3} -}; - - -VOID IndirectIOCommand(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - - -VOID IndirectIOCommand_MOVE_INDEX(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); - pParserTempData->IndirectData |=(((pParserTempData->Index >> pParserTempData->IndirectIOTablePointer[2]) & - (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); -} - -VOID IndirectIOCommand_MOVE_ATTR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); - pParserTempData->IndirectData |=(((pParserTempData->AttributesData >> pParserTempData->IndirectIOTablePointer[2]) - & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); -} - -VOID IndirectIOCommand_MOVE_DATA(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[3]); - pParserTempData->IndirectData |=(((pParserTempData->DestData32 >> pParserTempData->IndirectIOTablePointer[2]) - & (0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1]))) << pParserTempData->IndirectIOTablePointer[3]); -} - - -VOID IndirectIOCommand_SET(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData |= ((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); -} - -VOID IndirectIOCommand_CLEAR(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->IndirectData &= ~((0xFFFFFFFF >> (32-pParserTempData->IndirectIOTablePointer[1])) << pParserTempData->IndirectIOTablePointer[2]); -} - - -UINT32 IndirectInputOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - // if ((pParserTempData->IndirectData & 0x7f)==INDIRECT_IO_MM) pParserTempData->IndirectData|=pParserTempData->CurrentPortID; -// pParserTempData->IndirectIOTablePointer=pParserTempData->IndirectIOTable; - while (*pParserTempData->IndirectIOTablePointer) - { - if ((pParserTempData->IndirectIOTablePointer[0] == INDIRECTIO_ID) && - (pParserTempData->IndirectIOTablePointer[1] == pParserTempData->IndirectData)) - { - pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; - while (*pParserTempData->IndirectIOTablePointer != INDIRECTIO_END_OF_ID) - { - IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].func(pParserTempData); - pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; - } - pParserTempData->IndirectIOTablePointer-=*(UINT16*)(pParserTempData->IndirectIOTablePointer+1); - pParserTempData->IndirectIOTablePointer++; - return pParserTempData->IndirectData; - } else pParserTempData->IndirectIOTablePointer+=IndirectIOParserCommands[*pParserTempData->IndirectIOTablePointer].csize; - } - return 0; -} - - - -VOID PutDataRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.WordXX.PA_Destination; - pParserTempData->Index+=pParserTempData->CurrentRegBlock; - switch(pParserTempData->Multipurpose.CurrentPort){ - case ATI_RegsPort: - if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) - { - if (pParserTempData->Index==0) pParserTempData->DestData32 <<= 2; - WriteReg32( pParserTempData); - } else - { - pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_WRITE; - IndirectInputOutput(pParserTempData); - } - break; - case PCI_Port: - WritePCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - break; - case SystemIO_Port: - WriteIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - break; - } -} - -VOID PutDataPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination)= - pParserTempData->DestData32; -} - -VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination < WS_QUOTIENT_C) - *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) = pParserTempData->DestData32; - else - switch (pParserTempData->pCmd->Parameters.ByteXX.PA_Destination) - { - case WS_REMINDER_C: - pParserTempData->MultiplicationOrDivision.Division.Reminder32=pParserTempData->DestData32; - break; - case WS_QUOTIENT_C: - pParserTempData->MultiplicationOrDivision.Division.Quotient32=pParserTempData->DestData32; - break; - case WS_DATAPTR_C: -#ifndef UEFI_BUILD - pParserTempData->CurrentDataBlock=(UINT16)pParserTempData->DestData32; -#else - pParserTempData->CurrentDataBlock=(UINTN)pParserTempData->DestData32; -#endif - break; - case WS_SHIFT_C: - pParserTempData->Shift2MaskConverter=(UINT8)pParserTempData->DestData32; - break; - case WS_FB_WINDOW_C: - pParserTempData->CurrentFB_Window=pParserTempData->DestData32; - break; - case WS_ATTRIBUTES_C: - pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32; - break; - } - -} - -VOID PutDataFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; - //Make an Index from address first, then add to the Index - pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); - WriteFrameBuffer32(pParserTempData); -} - -VOID PutDataPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; - WritePLL32( pParserTempData ); -} - -VOID PutDataMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=(UINT32)pParserTempData->pCmd->Parameters.ByteXX.PA_Destination; - WriteMC32( pParserTempData ); -} - - -VOID SkipParameters8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); -} - -VOID SkipParameters16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); -} - - -UINT32 GetParametersRegister(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - pParserTempData->Index+=pParserTempData->CurrentRegBlock; - switch(pParserTempData->Multipurpose.CurrentPort) - { - case PCI_Port: - return ReadPCIFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - case SystemIO_Port: - return ReadIOFunctions[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); - case ATI_RegsPort: - default: - if (pParserTempData->CurrentPortID == INDIRECT_IO_MM) return ReadReg32( pParserTempData ); - else - { - pParserTempData->IndirectData=pParserTempData->CurrentPortID+INDIRECT_IO_READ; - return IndirectInputOutput(pParserTempData); - } - } -} - -UINT32 GetParametersPS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - return *(pParserTempData->pDeviceData->pParameterSpace+pParserTempData->Index); -} - -UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - if (pParserTempData->Index < WS_QUOTIENT_C) - return *(pParserTempData->pWorkingTableData->pWorkSpace+pParserTempData->Index); - else - switch (pParserTempData->Index) - { - case WS_REMINDER_C: - return pParserTempData->MultiplicationOrDivision.Division.Reminder32; - case WS_QUOTIENT_C: - return pParserTempData->MultiplicationOrDivision.Division.Quotient32; - case WS_DATAPTR_C: - return (UINT32)pParserTempData->CurrentDataBlock; - case WS_OR_MASK_C: - return ((UINT32)1) << pParserTempData->Shift2MaskConverter; - case WS_AND_MASK_C: - return ~(((UINT32)1) << pParserTempData->Shift2MaskConverter); - case WS_FB_WINDOW_C: - return pParserTempData->CurrentFB_Window; - case WS_ATTRIBUTES_C: - return pParserTempData->AttributesData; - } - return 0; - -} - -UINT32 GetParametersFB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - pParserTempData->Index+=(pParserTempData->CurrentFB_Window>>2); - return ReadFrameBuffer32(pParserTempData); -} - -UINT32 GetParametersPLL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - return ReadPLL32( pParserTempData ); -} - -UINT32 GetParametersMC(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - return ReadMC32( pParserTempData ); -} - - -UINT32 GetParametersIndirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - return *(UINT32*)(RELATIVE_TO_BIOS_IMAGE(pParserTempData->Index)+pParserTempData->CurrentDataBlock); -} - -UINT32 GetParametersDirect8(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CD_Mask.SrcAlignment=alignmentByte0; - pParserTempData->Index=*(UINT8*)pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT8); - return pParserTempData->Index; -} - -UINT32 GetParametersDirect16(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CD_Mask.SrcAlignment=alignmentLowerWord; - pParserTempData->Index=*(UINT16*)pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); - return pParserTempData->Index; -} - -UINT32 GetParametersDirect32(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CD_Mask.SrcAlignment=alignmentDword; - pParserTempData->Index=*(UINT32*)pParserTempData->pWorkingTableData->IP; - pParserTempData->pWorkingTableData->IP+=sizeof(UINT32); - return pParserTempData->Index; -} - - -UINT32 GetParametersDirect(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - return GetParametersDirectArray[pParserTempData->pCmd->Header.Attribute.SourceAlignment](pParserTempData); -} - - -VOID CommonSourceDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; -} - -VOID CommonOperationDataTransformation(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->DestData32 >>= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->DestData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; -} - -VOID ProcessMove(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) - { - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - } else - { - SkipDestination[pParserTempData->ParametersType.Destination](pParserTempData); - } - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - - if (pParserTempData->CD_Mask.SrcAlignment!=alignmentDword) - { - pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 |= pParserTempData->SourceData32; - } else - { - pParserTempData->DestData32=pParserTempData->SourceData32; - } - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetParametersDirect(pParserTempData); - pParserTempData->Index=GetParametersDirect(pParserTempData); - pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); - pParserTempData->DestData32 &= pParserTempData->SourceData32; - pParserTempData->Index &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->Index <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->DestData32 |= pParserTempData->Index; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessAnd(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]; - pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]); - pParserTempData->DestData32 &= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessOr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 |= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessXor(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 ^= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessShl(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 <<= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessShr(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 >>= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - - -VOID ProcessADD(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 += pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessSUB(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonSourceDataTransformation(pParserTempData); - pParserTempData->DestData32 -= pParserTempData->SourceData32; - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessMUL(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonOperationDataTransformation(pParserTempData); - pParserTempData->MultiplicationOrDivision.Multiplication.Low32Bit=pParserTempData->DestData32 * pParserTempData->SourceData32; -} - -VOID ProcessDIV(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - - CommonOperationDataTransformation(pParserTempData); - pParserTempData->MultiplicationOrDivision.Division.Quotient32= - pParserTempData->DestData32 / pParserTempData->SourceData32; - pParserTempData->MultiplicationOrDivision.Division.Reminder32= - pParserTempData->DestData32 % pParserTempData->SourceData32; -} - - -VOID ProcessCompare(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - - CommonOperationDataTransformation(pParserTempData); - - // Here we just set flags based on evaluation - if (pParserTempData->DestData32==pParserTempData->SourceData32) - pParserTempData->CompareFlags = Equal; - else - pParserTempData->CompareFlags = - (UINT8)((pParserTempData->DestData32<pParserTempData->SourceData32) ? Below : Above); - -} - -VOID ProcessClear(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->DestData32 &= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]); - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); - -} - -VOID ProcessShift(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT32 mask = AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetParametersDirect8(pParserTempData); - - // save original value of the destination - pParserTempData->Index = pParserTempData->DestData32 & ~mask; - pParserTempData->DestData32 &= mask; - - if (pParserTempData->pCmd->Header.Opcode < SHIFT_RIGHT_REG_OPCODE) - pParserTempData->DestData32 <<= pParserTempData->SourceData32; else - pParserTempData->DestData32 >>= pParserTempData->SourceData32; - - // Clear any bits shifted out of masked area... - pParserTempData->DestData32 &= mask; - // ... and restore the area outside of masked with original values - pParserTempData->DestData32 |= pParserTempData->Index; - - // write data back - PutDataFunctions[pParserTempData->ParametersType.Destination](pParserTempData); -} - -VOID ProcessTest(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData); - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - CommonOperationDataTransformation(pParserTempData); - pParserTempData->CompareFlags = - (UINT8)((pParserTempData->DestData32 & pParserTempData->SourceData32) ? NotEqual : Equal); - -} - -VOID ProcessSetFB_Base(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->CurrentFB_Window=pParserTempData->SourceData32; -} - -VOID ProcessSwitch(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->SourceData32=GetSource[pParserTempData->ParametersType.Source](pParserTempData); - pParserTempData->SourceData32 >>= SourceAlignmentShift[pParserTempData->CD_Mask.SrcAlignment]; - pParserTempData->SourceData32 &= AlignmentMask[pParserTempData->CD_Mask.SrcAlignment]; - while ( *(UINT16*)pParserTempData->pWorkingTableData->IP != (((UINT16)NOP_OPCODE << 8)+NOP_OPCODE)) - { - if (*pParserTempData->pWorkingTableData->IP == 'c') - { - pParserTempData->pWorkingTableData->IP++; - pParserTempData->DestData32=GetParametersDirect(pParserTempData); - pParserTempData->Index=GetParametersDirect16(pParserTempData); - if (pParserTempData->SourceData32 == pParserTempData->DestData32) - { - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(pParserTempData->Index); - return; - } - } - } - pParserTempData->pWorkingTableData->IP+=sizeof(UINT16); -} - - -VOID cmdSetDataBlock(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT8 value; - UINT16* pMasterDataTable; - value=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - if (value == 0) pParserTempData->CurrentDataBlock=0; else - { - if (value == DB_CURRENT_COMMAND_TABLE) - { - pParserTempData->CurrentDataBlock= (UINT16)(pParserTempData->pWorkingTableData->pTableHead-pParserTempData->pDeviceData->pBIOS_Image); - } else - { - pMasterDataTable = GetDataMasterTablePointer(pParserTempData->pDeviceData); - pParserTempData->CurrentDataBlock= (TABLE_UNIT_TYPE)((PTABLE_UNIT_TYPE)pMasterDataTable)[value]; - } - } - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - -VOID cmdSet_ATI_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Multipurpose.CurrentPort=ATI_RegsPort; - pParserTempData->CurrentPortID = (UINT8)((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -} - -VOID cmdSet_Reg_Block(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->CurrentRegBlock = ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination; - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -} - - -//Atavism!!! Review!!! -VOID cmdSet_X_Port(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->Multipurpose.CurrentPort=pParserTempData->ParametersType.Destination; - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_ONLY); - -} - -VOID cmdDelay_Millisec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - DelayMilliseconds(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} -VOID cmdDelay_Microsec(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - DelayMicroseconds(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - -VOID ProcessPostChar(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - PostCharOutput(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - -VOID ProcessDebug(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->SourceData32 = - ((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.ByteXX.PA_Destination; - CallerDebugFunc(pParserTempData); - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); -} - - -VOID ProcessDS(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->pWorkingTableData->IP+=((COMMAND_TYPE_1*)pParserTempData->pWorkingTableData->IP)->Parameters.WordXX.PA_Destination+sizeof(COMMAND_TYPE_OPCODE_OFFSET16); -} - - -VOID cmdCall_Table(PARSER_TEMP_DATA STACK_BASED * pParserTempData){ - UINT16* MasterTableOffset; - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_VALUE_BYTE); - MasterTableOffset = GetCommandMasterTablePointer(pParserTempData->pDeviceData); - if(((PTABLE_UNIT_TYPE)MasterTableOffset)[((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value]!=0 ) // if the offset is not ZERO - { - pParserTempData->CommandSpecific.IndexInMasterTable=GetTrueIndexInMasterTable(pParserTempData,((COMMAND_TYPE_OPCODE_VALUE_BYTE*)pParserTempData->pCmd)->Value); - pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable = - (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER *)pParserTempData->pWorkingTableData->pTableHead)->TableAttribute.PS_SizeInBytes>>2); - pParserTempData->pDeviceData->pParameterSpace+= - pParserTempData->Multipurpose.PS_SizeInDwordsUsedByCallingTable; - pParserTempData->Status=CD_CALL_TABLE; - pParserTempData->pCmd=(GENERIC_ATTRIBUTE_COMMAND*)MasterTableOffset; - } -} - - -VOID cmdNOP_(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - - -static VOID NotImplemented(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - pParserTempData->Status = CD_NOT_IMPLEMENTED; -} - - -VOID ProcessJump(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if ((pParserTempData->ParametersType.Destination == NoCondition) || - (pParserTempData->ParametersType.Destination == pParserTempData->CompareFlags )) - { - - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } -} - -VOID ProcessJumpE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if ((pParserTempData->CompareFlags == Equal) || - (pParserTempData->CompareFlags == pParserTempData->ParametersType.Destination)) - { - - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } -} - -VOID ProcessJumpNE(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - if (pParserTempData->CompareFlags != Equal) - { - - pParserTempData->pWorkingTableData->IP= RELATIVE_TO_TABLE(((COMMAND_TYPE_OPCODE_OFFSET16*)pParserTempData->pWorkingTableData->IP)->CD_Offset16); - } else - { - pParserTempData->pWorkingTableData->IP+=sizeof(COMMAND_TYPE_OPCODE_OFFSET16); - } -} - - - -COMMANDS_PROPERTIES CallTable[] = -{ - { NULL, 0,0}, - { ProcessMove, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessMove, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessMove, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessMove, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessMove, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessMove, destMC, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessAnd, destMC, sizeof(COMMAND_HEADER)}, - { ProcessOr, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessOr, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessOr, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessOr, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessOr, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessOr, destMC, sizeof(COMMAND_HEADER)}, - { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, - { ProcessShift, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShift, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShift, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShift, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShift, destMC, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessMUL, destMC, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessDIV, destMC, sizeof(COMMAND_HEADER)}, - { ProcessADD, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessADD, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessADD, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessADD, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessADD, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessADD, destMC, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessSUB, destMC, sizeof(COMMAND_HEADER)}, - { cmdSet_ATI_Port, ATI_RegsPort, 0}, - { cmdSet_X_Port, PCI_Port, 0}, - { cmdSet_X_Port, SystemIO_Port, 0}, - { cmdSet_Reg_Block, 0, 0}, - { ProcessSetFB_Base,0, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessCompare, destMC, sizeof(COMMAND_HEADER)}, - { ProcessSwitch, 0, sizeof(COMMAND_HEADER)}, - { ProcessJump, NoCondition, 0}, - { ProcessJump, Equal, 0}, - { ProcessJump, Below, 0}, - { ProcessJump, Above, 0}, - { ProcessJumpE, Below, 0}, - { ProcessJumpE, Above, 0}, - { ProcessJumpNE, 0, 0}, - { ProcessTest, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessTest, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessTest, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessTest, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessTest, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessTest, destMC, sizeof(COMMAND_HEADER)}, - { cmdDelay_Millisec,0, 0}, - { cmdDelay_Microsec,0, 0}, - { cmdCall_Table, 0, 0}, - /*cmdRepeat*/ { NotImplemented, 0, 0}, - { ProcessClear, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessClear, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessClear, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessClear, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessClear, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessClear, destMC, sizeof(COMMAND_HEADER)}, - { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, - /*cmdEOT*/ { cmdNOP_, 0, sizeof(COMMAND_TYPE_OPCODE_ONLY)}, - { ProcessMask, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessMask, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessMask, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessMask, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessMask, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessMask, destMC, sizeof(COMMAND_HEADER)}, - /*cmdPost_Card*/ { ProcessPostChar, 0, 0}, - /*cmdBeep*/ { NotImplemented, 0, 0}, - /*cmdSave_Reg*/ { NotImplemented, 0, 0}, - /*cmdRestore_Reg*/{ NotImplemented, 0, 0}, - { cmdSetDataBlock, 0, 0}, - { ProcessXor, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessXor, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessXor, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessXor, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessXor, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessXor, destMC, sizeof(COMMAND_HEADER)}, - - { ProcessShl, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShl, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShl, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShl, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShl, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShl, destMC, sizeof(COMMAND_HEADER)}, - - { ProcessShr, destRegister, sizeof(COMMAND_HEADER)}, - { ProcessShr, destParamSpace, sizeof(COMMAND_HEADER)}, - { ProcessShr, destWorkSpace, sizeof(COMMAND_HEADER)}, - { ProcessShr, destFrameBuffer, sizeof(COMMAND_HEADER)}, - { ProcessShr, destPLL, sizeof(COMMAND_HEADER)}, - { ProcessShr, destMC, sizeof(COMMAND_HEADER)}, - /*cmdDebug*/ { ProcessDebug, 0, 0}, - { ProcessDS, 0, 0}, - -}; - -// EOF diff --git a/src/AtomBios/Decoder.c b/src/AtomBios/Decoder.c deleted file mode 100644 index cdaa9ef..0000000 --- a/src/AtomBios/Decoder.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - -Module Name: - - Decoder.c - -Abstract: - - Commands Decoder - -Revision History: - - NEG:24.09.2002 Initiated. ---*/ -//#include "AtomBios.h" -#include "Decoder.h" -#include "atombios.h" -#include "CD_binding.h" -#include "CD_Common_Types.h" - -#ifndef DISABLE_EASF - #include "easf.h" -#endif - - - -#define INDIRECT_IO_TABLE (((UINT16)(ULONG_PTR)&((ATOM_MASTER_LIST_OF_DATA_TABLES*)0)->IndirectIOAccess)/sizeof(TABLE_UNIT_TYPE) ) -extern COMMANDS_PROPERTIES CallTable[]; - - -UINT8 ProcessCommandProperties(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ - UINT8 opcode=((COMMAND_HEADER*)pParserTempData->pWorkingTableData->IP)->Opcode; - pParserTempData->pWorkingTableData->IP+=CallTable[opcode].headersize; - pParserTempData->ParametersType.Destination=CallTable[opcode].destination; - pParserTempData->ParametersType.Source = pParserTempData->pCmd->Header.Attribute.Source; - pParserTempData->CD_Mask.SrcAlignment=pParserTempData->pCmd->Header.Attribute.SourceAlignment; - pParserTempData->CD_Mask.DestAlignment=pParserTempData->pCmd->Header.Attribute.DestinationAlignment; - return opcode; -} - -UINT16* GetCommandMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) -{ - UINT16 *MasterTableOffset; -#ifndef DISABLE_EASF - if (pDeviceData->format == TABLE_FORMAT_EASF) - { - /* - make MasterTableOffset point to EASF_ASIC_SETUP_TABLE structure, including usSize. - */ - MasterTableOffset = (UINT16 *) (pDeviceData->pBIOS_Image+((EASF_ASIC_DESCRIPTOR*)pDeviceData->pBIOS_Image)->usAsicSetupTable_Offset); - } else -#endif - { -#ifndef UEFI_BUILD - MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); - MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterCommandTableOffset + pDeviceData->pBIOS_Image ); - MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_COMMAND_TABLE *)MasterTableOffset)->ListOfCommandTables); -#else - MasterTableOffset = (UINT16 *)(&(GetCommandMasterTable( )->ListOfCommandTables)); -#endif - } - return MasterTableOffset; -} - -UINT16* GetDataMasterTablePointer(DEVICE_DATA STACK_BASED* pDeviceData) -{ - UINT16 *MasterTableOffset; - -#ifndef UEFI_BUILD - MasterTableOffset = (UINT16 *)(*(UINT16 *)(pDeviceData->pBIOS_Image+OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER) + pDeviceData->pBIOS_Image); - MasterTableOffset = (UINT16 *)((ULONG)((ATOM_ROM_HEADER *)MasterTableOffset)->usMasterDataTableOffset + pDeviceData->pBIOS_Image ); - MasterTableOffset =(UINT16 *) &(((ATOM_MASTER_DATA_TABLE *)MasterTableOffset)->ListOfDataTables); -#else - MasterTableOffset = (UINT16 *)(&(GetDataMasterTable( )->ListOfDataTables)); -#endif - return MasterTableOffset; -} - - -UINT8 GetTrueIndexInMasterTable(PARSER_TEMP_DATA STACK_BASED * pParserTempData, UINT8 IndexInMasterTable) -{ -#ifndef DISABLE_EASF - UINT16 i; - if ( pParserTempData->pDeviceData->format == TABLE_FORMAT_EASF) - { -/* - Consider EASF_ASIC_SETUP_TABLE structure pointed by pParserTempData->pCmd as UINT16[] - ((UINT16*)pParserTempData->pCmd)[0] = EASF_ASIC_SETUP_TABLE.usSize; - ((UINT16*)pParserTempData->pCmd)[1+n*4] = usFunctionID; - usFunctionID has to be shifted left by 2 before compare it to the value provided by caller. -*/ - for (i=1; (i < ((UINT16*)pParserTempData->pCmd)[0] >> 1);i+=4) - if ((UINT8)(((UINT16*)pParserTempData->pCmd)[i] << 2)==(IndexInMasterTable & EASF_TABLE_INDEX_MASK)) return (i+1+(IndexInMasterTable & EASF_TABLE_ATTR_MASK)); - return 1; - } else -#endif - { - return IndexInMasterTable; - } -} - -CD_STATUS ParseTable(DEVICE_DATA STACK_BASED* pDeviceData, UINT8 IndexInMasterTable) -{ - PARSER_TEMP_DATA ParserTempData; - WORKING_TABLE_DATA STACK_BASED* prevWorkingTableData; - - ParserTempData.pDeviceData=(DEVICE_DATA*)pDeviceData; -#ifndef DISABLE_EASF - if (pDeviceData->format == TABLE_FORMAT_EASF) - { - ParserTempData.IndirectIOTablePointer = 0; - } else -#endif - { - ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetDataMasterTablePointer(pDeviceData); - ParserTempData.IndirectIOTablePointer=(UINT8*)((ULONG)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[INDIRECT_IO_TABLE]) + pDeviceData->pBIOS_Image); - ParserTempData.IndirectIOTablePointer+=sizeof(ATOM_COMMON_TABLE_HEADER); - } - - ParserTempData.pCmd=(GENERIC_ATTRIBUTE_COMMAND*)GetCommandMasterTablePointer(pDeviceData); - IndexInMasterTable=GetTrueIndexInMasterTable((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData,IndexInMasterTable); - if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0 ) // if the offset is not ZERO - { - ParserTempData.CommandSpecific.IndexInMasterTable=IndexInMasterTable; - ParserTempData.Multipurpose.CurrentPort=ATI_RegsPort; - ParserTempData.CurrentPortID=INDIRECT_IO_MM; - ParserTempData.CurrentRegBlock=0; - ParserTempData.CurrentFB_Window=0; - prevWorkingTableData=NULL; - ParserTempData.Status=CD_CALL_TABLE; - - do{ - - if (ParserTempData.Status==CD_CALL_TABLE) - { - IndexInMasterTable=ParserTempData.CommandSpecific.IndexInMasterTable; - if(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]!=0) // if the offset is not ZERO - { -#ifndef UEFI_BUILD - ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, - ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); -#else - ParserTempData.pWorkingTableData =(WORKING_TABLE_DATA STACK_BASED*) AllocateWorkSpace(pDeviceData, - ((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]))->TableAttribute.WS_SizeInBytes+sizeof(WORKING_TABLE_DATA)); -#endif - if (ParserTempData.pWorkingTableData!=NULL) - { - ParserTempData.pWorkingTableData->pWorkSpace=(WORKSPACE_POINTER STACK_BASED*)((UINT8*)ParserTempData.pWorkingTableData+sizeof(WORKING_TABLE_DATA)); -#ifndef UEFI_BUILD - ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]+pDeviceData->pBIOS_Image); -#else - ParserTempData.pWorkingTableData->pTableHead = (UINT8 *)(((PTABLE_UNIT_TYPE)ParserTempData.pCmd)[IndexInMasterTable]); -#endif - ParserTempData.pWorkingTableData->IP=((UINT8*)ParserTempData.pWorkingTableData->pTableHead)+sizeof(ATOM_COMMON_ROM_COMMAND_TABLE_HEADER); - ParserTempData.pWorkingTableData->prevWorkingTableData=prevWorkingTableData; - prevWorkingTableData=ParserTempData.pWorkingTableData; - ParserTempData.Status = CD_SUCCESS; - } else ParserTempData.Status = CD_UNEXPECTED_BEHAVIOR; - } else ParserTempData.Status = CD_EXEC_TABLE_NOT_FOUND; - } - if (!CD_ERROR(ParserTempData.Status)) - { - ParserTempData.Status = CD_SUCCESS; - while (!CD_ERROR_OR_COMPLETED(ParserTempData.Status)) - { - - if (IS_COMMAND_VALID(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) - { - ParserTempData.pCmd = (GENERIC_ATTRIBUTE_COMMAND*)ParserTempData.pWorkingTableData->IP; - - if (IS_END_OF_TABLE(((COMMAND_HEADER*)ParserTempData.pWorkingTableData->IP)->Opcode)) - { - ParserTempData.Status=CD_COMPLETED; - prevWorkingTableData=ParserTempData.pWorkingTableData->prevWorkingTableData; - - FreeWorkSpace(pDeviceData, ParserTempData.pWorkingTableData); - ParserTempData.pWorkingTableData=prevWorkingTableData; - if (prevWorkingTableData!=NULL) - { - ParserTempData.pDeviceData->pParameterSpace-= - (((ATOM_COMMON_ROM_COMMAND_TABLE_HEADER*)ParserTempData.pWorkingTableData-> - pTableHead)->TableAttribute.PS_SizeInBytes>>2); - } - // if there is a parent table where to return, then restore PS_pointer to the original state - } - else - { - IndexInMasterTable=ProcessCommandProperties((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); - (*CallTable[IndexInMasterTable].function)((PARSER_TEMP_DATA STACK_BASED *)&ParserTempData); -#if (PARSER_TYPE!=DRIVER_TYPE_PARSER) - BIOS_STACK_MODIFIER(); -#endif - } - } - else - { - ParserTempData.Status=CD_INVALID_OPCODE; - break; - } - - } // while - } // if - else - break; - } while (prevWorkingTableData!=NULL); - if (ParserTempData.Status == CD_COMPLETED) return CD_SUCCESS; - return ParserTempData.Status; - } else return CD_SUCCESS; -} - -// EOF - diff --git a/src/AtomBios/hwserv_drv.c b/src/AtomBios/hwserv_drv.c deleted file mode 100644 index a5f5a5b..0000000 --- a/src/AtomBios/hwserv_drv.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/** - -Module Name: - - hwserv_drv.c - -Abstract: - - Functions defined in the Command Decoder Specification document - -Revision History: - - NEG:27.09.2002 Initiated. ---*/ -#include "CD_binding.h" -#include "CD_hw_services.h" - -//trace settings -#if DEBUG_OUTPUT_DEVICE & 1 - #define TRACE_USING_STDERR //define it to use stderr as trace output, -#endif -#if DEBUG_OUTPUT_DEVICE & 2 - #define TRACE_USING_RS232 -#endif -#if DEBUG_OUTPUT_DEVICE & 4 - #define TRACE_USING_LPT -#endif - - -#if DEBUG_PARSER == 4 - #define IO_TRACE //IO access trace switch, undefine it to turn off - #define PCI_TRACE //PCI access trace switch, undefine it to turn off - #define MEM_TRACE //MEM access trace switch, undefine it to turn off -#endif - -UINT32 CailReadATIRegister(VOID*,UINT32); -VOID CailWriteATIRegister(VOID*,UINT32,UINT32); -VOID* CailAllocateMemory(VOID*,UINT16); -VOID CailReleaseMemory(VOID *,VOID *); -VOID CailDelayMicroSeconds(VOID *,UINT32 ); -VOID CailReadPCIConfigData(VOID*,VOID*,UINT32,UINT16); -VOID CailWritePCIConfigData(VOID*,VOID*,UINT32,UINT16); -UINT32 CailReadFBData(VOID*,UINT32); -VOID CailWriteFBData(VOID*,UINT32,UINT32); -ULONG CailReadPLL(VOID *Context ,ULONG Address); -VOID CailWritePLL(VOID *Context,ULONG Address,ULONG Data); -ULONG CailReadMC(VOID *Context ,ULONG Address); -VOID CailWriteMC(VOID *Context ,ULONG Address,ULONG Data); - - -#if DEBUG_PARSER>0 -VOID CailVideoDebugPrint(VOID*,ULONG_PTR, UINT16); -#endif -// Delay function -#if ( defined ENABLE_PARSER_DELAY || defined ENABLE_ALL_SERVICE_FUNCTIONS ) - -VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32*1000); -} - -VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailDelayMicroSeconds(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->SourceData32); -} -#endif - -VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - -VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData) -{ -} - - -// PCI READ Access - -#if ( defined ENABLE_PARSER_PCIREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT8 rvl; - CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT8)); - return rvl; -} -#endif - - -#if ( defined ENABLE_PARSER_PCIREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT16 rvl; - CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT16)); - return rvl; - -} -#endif - - - -#if ( defined ENABLE_PARSER_PCIREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT32 ReadPCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT32 rvl; - CailReadPCIConfigData(pWorkingTableData->pDeviceData->CAIL,&rvl,pWorkingTableData->Index,sizeof(UINT32)); - return rvl; -} -#endif - - -// PCI WRITE Access - -#if ( defined ENABLE_PARSER_PCIWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WritePCIReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT8)); - -} - -#endif - - -#if ( defined ENABLE_PARSER_PCIWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WritePCIReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT16)); -} - -#endif - - -#if ( defined ENABLE_PARSER_PCIWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WritePCIReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWritePCIConfigData(pWorkingTableData->pDeviceData->CAIL,&(pWorkingTableData->DestData32),pWorkingTableData->Index,sizeof(UINT32)); -} -#endif - - - - -// System IO Access -#if ( defined ENABLE_PARSER_SYS_IOREAD8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT8 ReadSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT8 rvl; - rvl=0; - //rvl= (UINT8) ReadGenericPciCfg(dev,reg,sizeof(UINT8)); - return rvl; -} -#endif - - -#if ( defined ENABLE_PARSER_SYS_IOREAD16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT16 rvl; - rvl=0; - //rvl= (UINT16) ReadGenericPciCfg(dev,reg,sizeof(UINT16)); - return rvl; - -} -#endif - - - -#if ( defined ENABLE_PARSER_SYS_IOREAD32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT32 ReadSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - UINT32 rvl; - rvl=0; - //rvl= (UINT32) ReadGenericPciCfg(dev,reg,sizeof(UINT32)); - return rvl; -} -#endif - - -// PCI WRITE Access - -#if ( defined ENABLE_PARSER_SYS_IOWRITE8 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WriteSysIOReg8 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - //WriteGenericPciCfg(dev,reg,sizeof(UINT8),(UINT32)value); -} - -#endif - - -#if ( defined ENABLE_PARSER_SYS_IOWRITE16 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WriteSysIOReg16 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - //WriteGenericPciCfg(dev,reg,sizeof(UINT16),(UINT32)value); -} - -#endif - - -#if ( defined ENABLE_PARSER_SYS_IOWRITE32 || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -VOID WriteSysIOReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - //WriteGenericPciCfg(dev,reg,sizeof(UINT32),(UINT32)value); -} -#endif - -// ATI Registers Memory Mapped Access - -#if ( defined ENABLE_PARSER_REGISTERS_MEMORY_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS) - -UINT32 ReadReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); -} - -VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,(UINT16)pWorkingTableData->Index,pWorkingTableData->DestData32 ); -} - - -VOID ReadIndReg32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - pWorkingTableData->IndirectData = CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1)); -} - -VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,*(UINT16*)(pWorkingTableData->IndirectIOTablePointer+1),pWorkingTableData->IndirectData ); -} - -#endif - -// ATI Registers IO Mapped Access - -#if ( defined ENABLE_PARSER_REGISTERS_IO_ACCESS || defined ENABLE_ALL_SERVICE_FUNCTIONS ) -UINT32 ReadRegIO (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - //return CailReadATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); - return 0; -} -VOID WriteRegIO(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - // return CailWriteATIRegister(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32 ); -} -#endif - -// access to Frame buffer, dummy function, need more information to implement it -UINT32 ReadFrameBuffer32 (PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - - return CailReadFBData(pWorkingTableData->pDeviceData->CAIL, (pWorkingTableData->Index <<2 )); - -} - -VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteFBData(pWorkingTableData->pDeviceData->CAIL,(pWorkingTableData->Index <<2), pWorkingTableData->DestData32); - -} - - -VOID *AllocateMemory(DEVICE_DATA *pDeviceData , UINT16 MemSize) -{ - if(MemSize) - return(CailAllocateMemory(pDeviceData->CAIL,MemSize)); - else - return NULL; -} - - -VOID ReleaseMemory(DEVICE_DATA *pDeviceData , WORKING_TABLE_DATA* pWorkingTableData) -{ - if( pWorkingTableData) - CailReleaseMemory(pDeviceData->CAIL, pWorkingTableData); -} - - -UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT32 ReadData; - ReadData=(UINT32)CailReadMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); - return ReadData; -} - -VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWriteMC(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); -} - -UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - UINT32 ReadData; - ReadData=(UINT32)CailReadPLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index); - return ReadData; - -} - -VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pWorkingTableData) -{ - CailWritePLL(pWorkingTableData->pDeviceData->CAIL,pWorkingTableData->Index,pWorkingTableData->DestData32); - -} - - - -#if DEBUG_PARSER>0 -VOID CD_print_string (DEVICE_DATA *pDeviceData, UINT8 *str) -{ - CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR) str, PARSER_STRINGS); -} - -VOID CD_print_value (DEVICE_DATA *pDeviceData, ULONG_PTR value, UINT16 value_type ) -{ - CailVideoDebugPrint( pDeviceData->CAIL, (ULONG_PTR)value, value_type); -} - -#endif - -// EOF diff --git a/src/AtomBios/includes/CD_Common_Types.h b/src/AtomBios/includes/CD_Common_Types.h deleted file mode 100644 index 44a0b35..0000000 --- a/src/AtomBios/includes/CD_Common_Types.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - - CD_Common_Types.h - -Abstract: - - Defines common data types to use across platforms/SW components - -Revision History: - - NEG:17.09.2002 Initiated. ---*/ -#ifndef _COMMON_TYPES_H_ - #define _COMMON_TYPES_H_ - - #ifndef LINUX - #if _MSC_EXTENSIONS - - // - // use Microsoft* C complier dependent interger width types - // - // typedef unsigned __int64 uint64_t; - // typedef __int64 int64_t; - typedef unsigned __int32 uint32_t; - typedef __int32 int32_t; -#elif defined (__linux__) || defined (__NetBSD__) || defined(__sun) || defined(__OpenBSD__) || defined (__FreeBSD__) - typedef unsigned int uint32_t; - typedef int int32_t; - #else - typedef unsigned long uint32_t; - typedef signed long int32_t; - #endif - typedef unsigned char uint8_t; -#if (defined(__sun) && defined(_CHAR_IS_SIGNED)) - typedef char int8_t; -#else - typedef signed char int8_t; -#endif - typedef unsigned short uint16_t; - typedef signed short int16_t; - #endif -#ifndef UEFI_BUILD - typedef signed int intn_t; - typedef unsigned int uintn_t; -#else -#ifndef EFIX64 - typedef signed int intn_t; - typedef unsigned int uintn_t; -#endif -#endif -#ifndef FGL_LINUX -#pragma warning ( disable : 4142 ) -#endif - - -#ifndef VOID -typedef void VOID; -#endif -#ifndef UEFI_BUILD - typedef intn_t INTN; - typedef uintn_t UINTN; -#else -#ifndef EFIX64 - typedef intn_t INTN; - typedef uintn_t UINTN; -#endif -#endif -#ifndef BOOLEAN -typedef uint8_t BOOLEAN; -#endif -#ifndef INT8 -typedef int8_t INT8; -#endif -#ifndef UINT8 -typedef uint8_t UINT8; -#endif -#ifndef INT16 -typedef int16_t INT16; -#endif -#ifndef UINT16 -typedef uint16_t UINT16; -#endif -#ifndef INT32 -typedef int32_t INT32; -#endif -#ifndef UINT32 -typedef uint32_t UINT32; -#endif -//typedef int64_t INT64; -//typedef uint64_t UINT64; -typedef uint8_t CHAR8; -typedef uint16_t CHAR16; -#ifndef USHORT -typedef UINT16 USHORT; -#endif -#ifndef UCHAR -typedef UINT8 UCHAR; -#endif -#ifndef ULONG -typedef UINT32 ULONG; -#endif - -#ifndef _WIN64 -#ifndef ULONG_PTR -typedef unsigned long ULONG_PTR; -#endif // ULONG_PTR -#endif // _WIN64 - -//#define FAR __far -#ifndef TRUE - #define TRUE ((BOOLEAN) 1 == 1) -#endif - -#ifndef FALSE - #define FALSE ((BOOLEAN) 0 == 1) -#endif - -#ifndef NULL - #define NULL ((VOID *) 0) -#endif - -//typedef UINTN CD_STATUS; - - -#ifndef FGL_LINUX -#pragma warning ( default : 4142 ) -#endif -#endif // _COMMON_TYPES_H_ - -// EOF diff --git a/src/AtomBios/includes/CD_Definitions.h b/src/AtomBios/includes/CD_Definitions.h deleted file mode 100644 index 98fd495..0000000 --- a/src/AtomBios/includes/CD_Definitions.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -CD_Definitions.h - -Abstract: - -Defines Script Language commands - -Revision History: - -NEG:27.08.2002 Initiated. ---*/ - -#include "CD_Structs.h" -#ifndef _CD_DEFINITIONS_H -#define _CD_DEFINITIONS_H_ -#ifdef DRIVER_PARSER -VOID *AllocateMemory(VOID *, UINT16); -VOID ReleaseMemory(DEVICE_DATA * , WORKING_TABLE_DATA* ); -#endif -CD_STATUS ParseTable(DEVICE_DATA* pDeviceData, UINT8 IndexInMasterTable); -//CD_STATUS CD_MainLoop(PARSER_TEMP_DATA_POINTER pParserTempData); -CD_STATUS Main_Loop(DEVICE_DATA* pDeviceData,UINT16 *MasterTableOffset,UINT8 IndexInMasterTable); -UINT16* GetCommandMasterTablePointer(DEVICE_DATA* pDeviceData); -#endif //CD_DEFINITIONS diff --git a/src/AtomBios/includes/CD_Opcodes.h b/src/AtomBios/includes/CD_Opcodes.h deleted file mode 100644 index 2f3bec5..0000000 --- a/src/AtomBios/includes/CD_Opcodes.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -CD_OPCODEs.h - -Abstract: - -Defines Command Decoder OPCODEs - -Revision History: - -NEG:24.09.2002 Initiated. ---*/ -#ifndef _CD_OPCODES_H_ -#define _CD_OPCODES_H_ - -typedef enum _OPCODE { - Reserved_00= 0, // 0 = 0x00 - // MOVE_ group - MOVE_REG_OPCODE, // 1 = 0x01 - FirstValidCommand=MOVE_REG_OPCODE, - MOVE_PS_OPCODE, // 2 = 0x02 - MOVE_WS_OPCODE, // 3 = 0x03 - MOVE_FB_OPCODE, // 4 = 0x04 - MOVE_PLL_OPCODE, // 5 = 0x05 - MOVE_MC_OPCODE, // 6 = 0x06 - // Logic group - AND_REG_OPCODE, // 7 = 0x07 - AND_PS_OPCODE, // 8 = 0x08 - AND_WS_OPCODE, // 9 = 0x09 - AND_FB_OPCODE, // 10 = 0x0A - AND_PLL_OPCODE, // 11 = 0x0B - AND_MC_OPCODE, // 12 = 0x0C - OR_REG_OPCODE, // 13 = 0x0D - OR_PS_OPCODE, // 14 = 0x0E - OR_WS_OPCODE, // 15 = 0x0F - OR_FB_OPCODE, // 16 = 0x10 - OR_PLL_OPCODE, // 17 = 0x11 - OR_MC_OPCODE, // 18 = 0x12 - SHIFT_LEFT_REG_OPCODE, // 19 = 0x13 - SHIFT_LEFT_PS_OPCODE, // 20 = 0x14 - SHIFT_LEFT_WS_OPCODE, // 21 = 0x15 - SHIFT_LEFT_FB_OPCODE, // 22 = 0x16 - SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17 - SHIFT_LEFT_MC_OPCODE, // 24 = 0x18 - SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19 - SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A - SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B - SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C - SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D - SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E - // Arithmetic group - MUL_REG_OPCODE, // 31 = 0x1F - MUL_PS_OPCODE, // 32 = 0x20 - MUL_WS_OPCODE, // 33 = 0x21 - MUL_FB_OPCODE, // 34 = 0x22 - MUL_PLL_OPCODE, // 35 = 0x23 - MUL_MC_OPCODE, // 36 = 0x24 - DIV_REG_OPCODE, // 37 = 0x25 - DIV_PS_OPCODE, // 38 = 0x26 - DIV_WS_OPCODE, // 39 = 0x27 - DIV_FB_OPCODE, // 40 = 0x28 - DIV_PLL_OPCODE, // 41 = 0x29 - DIV_MC_OPCODE, // 42 = 0x2A - ADD_REG_OPCODE, // 43 = 0x2B - ADD_PS_OPCODE, // 44 = 0x2C - ADD_WS_OPCODE, // 45 = 0x2D - ADD_FB_OPCODE, // 46 = 0x2E - ADD_PLL_OPCODE, // 47 = 0x2F - ADD_MC_OPCODE, // 48 = 0x30 - SUB_REG_OPCODE, // 49 = 0x31 - SUB_PS_OPCODE, // 50 = 0x32 - SUB_WS_OPCODE, // 51 = 0x33 - SUB_FB_OPCODE, // 52 = 0x34 - SUB_PLL_OPCODE, // 53 = 0x35 - SUB_MC_OPCODE, // 54 = 0x36 - // Control grouop - SET_ATI_PORT_OPCODE, // 55 = 0x37 - SET_PCI_PORT_OPCODE, // 56 = 0x38 - SET_SYS_IO_PORT_OPCODE, // 57 = 0x39 - SET_REG_BLOCK_OPCODE, // 58 = 0x3A - SET_FB_BASE_OPCODE, // 59 = 0x3B - COMPARE_REG_OPCODE, // 60 = 0x3C - COMPARE_PS_OPCODE, // 61 = 0x3D - COMPARE_WS_OPCODE, // 62 = 0x3E - COMPARE_FB_OPCODE, // 63 = 0x3F - COMPARE_PLL_OPCODE, // 64 = 0x40 - COMPARE_MC_OPCODE, // 65 = 0x41 - SWITCH_OPCODE, // 66 = 0x42 - JUMP__OPCODE, // 67 = 0x43 - JUMP_EQUAL_OPCODE, // 68 = 0x44 - JUMP_BELOW_OPCODE, // 69 = 0x45 - JUMP_ABOVE_OPCODE, // 70 = 0x46 - JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47 - JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48 - JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49 - TEST_REG_OPCODE, // 74 = 0x4A - TEST_PS_OPCODE, // 75 = 0x4B - TEST_WS_OPCODE, // 76 = 0x4C - TEST_FB_OPCODE, // 77 = 0x4D - TEST_PLL_OPCODE, // 78 = 0x4E - TEST_MC_OPCODE, // 79 = 0x4F - DELAY_MILLISEC_OPCODE, // 80 = 0x50 - DELAY_MICROSEC_OPCODE, // 81 = 0x51 - CALL_TABLE_OPCODE, // 82 = 0x52 - REPEAT_OPCODE, // 83 = 0x53 - // Miscellaneous group - CLEAR_REG_OPCODE, // 84 = 0x54 - CLEAR_PS_OPCODE, // 85 = 0x55 - CLEAR_WS_OPCODE, // 86 = 0x56 - CLEAR_FB_OPCODE, // 87 = 0x57 - CLEAR_PLL_OPCODE, // 88 = 0x58 - CLEAR_MC_OPCODE, // 89 = 0x59 - NOP_OPCODE, // 90 = 0x5A - EOT_OPCODE, // 91 = 0x5B - MASK_REG_OPCODE, // 92 = 0x5C - MASK_PS_OPCODE, // 93 = 0x5D - MASK_WS_OPCODE, // 94 = 0x5E - MASK_FB_OPCODE, // 95 = 0x5F - MASK_PLL_OPCODE, // 96 = 0x60 - MASK_MC_OPCODE, // 97 = 0x61 - // BIOS dedicated group - POST_CARD_OPCODE, // 98 = 0x62 - BEEP_OPCODE, // 99 = 0x63 - SAVE_REG_OPCODE, // 100 = 0x64 - RESTORE_REG_OPCODE, // 101 = 0x65 - SET_DATA_BLOCK_OPCODE, // 102 = 0x66 - - XOR_REG_OPCODE, // 103 = 0x67 - XOR_PS_OPCODE, // 104 = 0x68 - XOR_WS_OPCODE, // 105 = 0x69 - XOR_FB_OPCODE, // 106 = 0x6a - XOR_PLL_OPCODE, // 107 = 0x6b - XOR_MC_OPCODE, // 108 = 0x6c - - SHL_REG_OPCODE, // 109 = 0x6d - SHL_PS_OPCODE, // 110 = 0x6e - SHL_WS_OPCODE, // 111 = 0x6f - SHL_FB_OPCODE, // 112 = 0x70 - SHL_PLL_OPCODE, // 113 = 0x71 - SHL_MC_OPCODE, // 114 = 0x72 - - SHR_REG_OPCODE, // 115 = 0x73 - SHR_PS_OPCODE, // 116 = 0x74 - SHR_WS_OPCODE, // 117 = 0x75 - SHR_FB_OPCODE, // 118 = 0x76 - SHR_PLL_OPCODE, // 119 = 0x77 - SHR_MC_OPCODE, // 120 = 0x78 - - DEBUG_OPCODE, // 121 = 0x79 - CTB_DS_OPCODE, // 122 = 0x7A - - LastValidCommand = CTB_DS_OPCODE, - // Extension specificaTOR - Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well - Reserved_FF = 255 // 255 = 0xFF -}OPCODE; -#endif // _CD_OPCODES_H_ diff --git a/src/AtomBios/includes/CD_Structs.h b/src/AtomBios/includes/CD_Structs.h deleted file mode 100644 index c43f81d..0000000 --- a/src/AtomBios/includes/CD_Structs.h +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -CD_Struct.h - -Abstract: - -Defines Script Language commands - -Revision History: - -NEG:26.08.2002 Initiated. ---*/ - -#include "CD_binding.h" -#ifndef _CD_STRUCTS_H_ -#define _CD_STRUCTS_H_ - -#ifdef UEFI_BUILD -typedef UINT16** PTABLE_UNIT_TYPE; -typedef UINTN TABLE_UNIT_TYPE; -#else -typedef UINT16* PTABLE_UNIT_TYPE; -typedef UINT16 TABLE_UNIT_TYPE; -#endif - -#include <regsdef.h> //This important file is dynamically generated based on the ASIC!!!! - -#define PARSER_MAJOR_REVISION 5 -#define PARSER_MINOR_REVISION 0 - -//#include "atombios.h" -#if (PARSER_TYPE==DRIVER_TYPE_PARSER) -#ifdef FGL_LINUX -#pragma pack(push,1) -#else -#pragma pack(push) -#pragma pack(1) -#endif -#endif - -#include "CD_Common_Types.h" -#include "CD_Opcodes.h" -typedef UINT16 WORK_SPACE_SIZE; -typedef enum _CD_STATUS{ - CD_SUCCESS, - CD_CALL_TABLE, - CD_COMPLETED=0x10, - CD_GENERAL_ERROR=0x80, - CD_INVALID_OPCODE, - CD_NOT_IMPLEMENTED, - CD_EXEC_TABLE_NOT_FOUND, - CD_EXEC_PARAMETER_ERROR, - CD_EXEC_PARSER_ERROR, - CD_INVALID_DESTINATION_TYPE, - CD_UNEXPECTED_BEHAVIOR, - CD_INVALID_SWITCH_OPERAND_SIZE -}CD_STATUS; - -#define PARSER_STRINGS 0 -#define PARSER_DEC 1 -#define PARSER_HEX 2 - -#define DB_CURRENT_COMMAND_TABLE 0xFF - -#define TABLE_FORMAT_BIOS 0 -#define TABLE_FORMAT_EASF 1 - -#define EASF_TABLE_INDEX_MASK 0xfc -#define EASF_TABLE_ATTR_MASK 0x03 - -#define CD_ERROR(a) (((INTN) (a)) > CD_COMPLETED) -#define CD_ERROR_OR_COMPLETED(a) (((INTN) (a)) > CD_SUCCESS) - - -#if (BIOS_PARSER==1) -#ifdef _H2INC -#define STACK_BASED -#else -extern __segment farstack; -#define STACK_BASED __based(farstack) -#endif -#else -#define STACK_BASED -#endif - -typedef enum _COMPARE_FLAGS{ - Below, - Equal, - Above, - NotEqual, - Overflow, - NoCondition -}COMPARE_FLAGS; - -typedef UINT16 IO_BASE_ADDR; - -typedef struct _BUS_DEV_FUNC_PCI_ADDR{ - UINT8 Register; - UINT8 Function; - UINT8 Device; - UINT8 Bus; -} BUS_DEV_FUNC_PCI_ADDR; - -typedef struct _BUS_DEV_FUNC{ - UINT8 Function : 3; - UINT8 Device : 5; - UINT8 Bus; -} BUS_DEV_FUNC; - -#ifndef UEFI_BUILD -typedef struct _PCI_CONFIG_ACCESS_CF8{ - UINT32 Reg : 8; - UINT32 Func : 3; - UINT32 Dev : 5; - UINT32 Bus : 8; - UINT32 Reserved: 7; - UINT32 Enable : 1; -} PCI_CONFIG_ACCESS_CF8; -#endif - -typedef enum _MEM_RESOURCE { - Stack_Resource, - FrameBuffer_Resource, - BIOS_Image_Resource -}MEM_RESOURCE; - -typedef enum _PORTS{ - ATI_RegsPort, - PCI_Port, - SystemIO_Port -}PORTS; - -typedef enum _OPERAND_TYPE { - typeRegister, - typeParamSpace, - typeWorkSpace, - typeFrameBuffer, - typeIndirect, - typeDirect, - typePLL, - typeMC -}OPERAND_TYPE; - -typedef enum _DESTINATION_OPERAND_TYPE { - destRegister, - destParamSpace, - destWorkSpace, - destFrameBuffer, - destPLL, - destMC -}DESTINATION_OPERAND_TYPE; - -typedef enum _SOURCE_OPERAND_TYPE { - sourceRegister, - sourceParamSpace, - sourceWorkSpace, - sourceFrameBuffer, - sourceIndirect, - sourceDirect, - sourcePLL, - sourceMC -}SOURCE_OPERAND_TYPE; - -typedef enum _ALIGNMENT_TYPE { - alignmentDword, - alignmentLowerWord, - alignmentMiddleWord, - alignmentUpperWord, - alignmentByte0, - alignmentByte1, - alignmentByte2, - alignmentByte3 -}ALIGNMENT_TYPE; - - -#define INDIRECT_IO_READ 0 -#define INDIRECT_IO_WRITE 0x80 -#define INDIRECT_IO_MM 0 -#define INDIRECT_IO_PLL 1 -#define INDIRECT_IO_MC 2 - -typedef struct _PARAMETERS_TYPE{ - UINT8 Destination; - UINT8 Source; -}PARAMETERS_TYPE; -/* The following structures don't used to allocate any type of objects(variables). - they are serve the only purpose: Get proper access to data(commands), found in the tables*/ -typedef struct _PA_BYTE_BYTE{ - UINT8 PA_Destination; - UINT8 PA_Source; - UINT8 PA_Padding[8]; -}PA_BYTE_BYTE; -typedef struct _PA_BYTE_WORD{ - UINT8 PA_Destination; - UINT16 PA_Source; - UINT8 PA_Padding[7]; -}PA_BYTE_WORD; -typedef struct _PA_BYTE_DWORD{ - UINT8 PA_Destination; - UINT32 PA_Source; - UINT8 PA_Padding[5]; -}PA_BYTE_DWORD; -typedef struct _PA_WORD_BYTE{ - UINT16 PA_Destination; - UINT8 PA_Source; - UINT8 PA_Padding[7]; -}PA_WORD_BYTE; -typedef struct _PA_WORD_WORD{ - UINT16 PA_Destination; - UINT16 PA_Source; - UINT8 PA_Padding[6]; -}PA_WORD_WORD; -typedef struct _PA_WORD_DWORD{ - UINT16 PA_Destination; - UINT32 PA_Source; - UINT8 PA_Padding[4]; -}PA_WORD_DWORD; -typedef struct _PA_WORD_XX{ - UINT16 PA_Destination; - UINT8 PA_Padding[8]; -}PA_WORD_XX; -typedef struct _PA_BYTE_XX{ - UINT8 PA_Destination; - UINT8 PA_Padding[9]; -}PA_BYTE_XX; -/*The following 6 definitions used for Mask operation*/ -typedef struct _PA_BYTE_BYTE_BYTE{ - UINT8 PA_Destination; - UINT8 PA_AndMaskByte; - UINT8 PA_OrMaskByte; - UINT8 PA_Padding[7]; -}PA_BYTE_BYTE_BYTE; -typedef struct _PA_BYTE_WORD_WORD{ - UINT8 PA_Destination; - UINT16 PA_AndMaskWord; - UINT16 PA_OrMaskWord; - UINT8 PA_Padding[5]; -}PA_BYTE_WORD_WORD; -typedef struct _PA_BYTE_DWORD_DWORD{ - UINT8 PA_Destination; - UINT32 PA_AndMaskDword; - UINT32 PA_OrMaskDword; - UINT8 PA_Padding; -}PA_BYTE_DWORD_DWORD; -typedef struct _PA_WORD_BYTE_BYTE{ - UINT16 PA_Destination; - UINT8 PA_AndMaskByte; - UINT8 PA_OrMaskByte; - UINT8 PA_Padding[6]; -}PA_WORD_BYTE_BYTE; -typedef struct _PA_WORD_WORD_WORD{ - UINT16 PA_Destination; - UINT16 PA_AndMaskWord; - UINT16 PA_OrMaskWord; - UINT8 PA_Padding[4]; -}PA_WORD_WORD_WORD; -typedef struct _PA_WORD_DWORD_DWORD{ - UINT16 PA_Destination; - UINT32 PA_AndMaskDword; - UINT32 PA_OrMaskDword; -}PA_WORD_DWORD_DWORD; - - -typedef union _PARAMETER_ACCESS { - PA_BYTE_XX ByteXX; - PA_BYTE_BYTE ByteByte; - PA_BYTE_WORD ByteWord; - PA_BYTE_DWORD ByteDword; - PA_WORD_BYTE WordByte; - PA_WORD_WORD WordWord; - PA_WORD_DWORD WordDword; - PA_WORD_XX WordXX; -/*The following 6 definitions used for Mask operation*/ - PA_BYTE_BYTE_BYTE ByteByteAndByteOr; - PA_BYTE_WORD_WORD ByteWordAndWordOr; - PA_BYTE_DWORD_DWORD ByteDwordAndDwordOr; - PA_WORD_BYTE_BYTE WordByteAndByteOr; - PA_WORD_WORD_WORD WordWordAndWordOr; - PA_WORD_DWORD_DWORD WordDwordAndDwordOr; -}PARAMETER_ACCESS; - -typedef struct _COMMAND_ATTRIBUTE { - UINT8 Source:3; - UINT8 SourceAlignment:3; - UINT8 DestinationAlignment:2; -}COMMAND_ATTRIBUTE; - -typedef struct _SOURCE_DESTINATION_ALIGNMENT{ - UINT8 DestAlignment; - UINT8 SrcAlignment; -}SOURCE_DESTINATION_ALIGNMENT; -typedef struct _MULTIPLICATION_RESULT{ - UINT32 Low32Bit; - UINT32 High32Bit; -}MULTIPLICATION_RESULT; -typedef struct _DIVISION_RESULT{ - UINT32 Quotient32; - UINT32 Reminder32; -}DIVISION_RESULT; -typedef union _DIVISION_MULTIPLICATION_RESULT{ - MULTIPLICATION_RESULT Multiplication; - DIVISION_RESULT Division; -}DIVISION_MULTIPLICATION_RESULT; -typedef struct _COMMAND_HEADER { - UINT8 Opcode; - COMMAND_ATTRIBUTE Attribute; -}COMMAND_HEADER; - -typedef struct _GENERIC_ATTRIBUTE_COMMAND{ - COMMAND_HEADER Header; - PARAMETER_ACCESS Parameters; -} GENERIC_ATTRIBUTE_COMMAND; - -typedef struct _COMMAND_TYPE_1{ - UINT8 Opcode; - PARAMETER_ACCESS Parameters; -} COMMAND_TYPE_1; - -typedef struct _COMMAND_TYPE_OPCODE_OFFSET16{ - UINT8 Opcode; - UINT16 CD_Offset16; -} COMMAND_TYPE_OPCODE_OFFSET16; - -typedef struct _COMMAND_TYPE_OPCODE_OFFSET32{ - UINT8 Opcode; - UINT32 CD_Offset32; -} COMMAND_TYPE_OPCODE_OFFSET32; - -typedef struct _COMMAND_TYPE_OPCODE_VALUE_BYTE{ - UINT8 Opcode; - UINT8 Value; -} COMMAND_TYPE_OPCODE_VALUE_BYTE; - -typedef union _COMMAND_SPECIFIC_UNION{ - UINT8 ContinueSwitch; - UINT8 ControlOperandSourcePosition; - UINT8 IndexInMasterTable; -} COMMAND_SPECIFIC_UNION; - - -typedef struct _CD_GENERIC_BYTE{ - UINT16 CommandType:3; - UINT16 CurrentParameterSize:3; - UINT16 CommandAccessType:3; - UINT16 CurrentPort:2; - UINT16 PS_SizeInDwordsUsedByCallingTable:5; -}CD_GENERIC_BYTE; - -typedef UINT8 COMMAND_TYPE_OPCODE_ONLY; - -typedef UINT8 COMMAND_HEADER_POINTER; - - -#if (PARSER_TYPE==BIOS_TYPE_PARSER) - -typedef struct _DEVICE_DATA { - UINT32 STACK_BASED *pParameterSpace; - UINT8 *pBIOS_Image; - UINT8 format; -#if (IO_INTERFACE==PARSER_INTERFACE) - IO_BASE_ADDR IOBase; -#endif -} DEVICE_DATA; - -#else - -typedef struct _DEVICE_DATA { - UINT32 *pParameterSpace; - VOID *CAIL; - UINT8 *pBIOS_Image; - UINT32 format; -} DEVICE_DATA; - -#endif - -struct _PARSER_TEMP_DATA; -typedef UINT32 WORKSPACE_POINTER; - -struct _WORKING_TABLE_DATA{ - UINT8 * pTableHead; - COMMAND_HEADER_POINTER * IP; // Commands pointer - WORKSPACE_POINTER STACK_BASED * pWorkSpace; - struct _WORKING_TABLE_DATA STACK_BASED * prevWorkingTableData; -}; - - - -typedef struct _PARSER_TEMP_DATA{ - DEVICE_DATA STACK_BASED *pDeviceData; - struct _WORKING_TABLE_DATA STACK_BASED *pWorkingTableData; - UINT32 SourceData32; - UINT32 DestData32; - DIVISION_MULTIPLICATION_RESULT MultiplicationOrDivision; - UINT32 Index; - UINT32 CurrentFB_Window; - UINT32 IndirectData; - UINT16 CurrentRegBlock; - TABLE_UNIT_TYPE CurrentDataBlock; - UINT16 AttributesData; -// UINT8 *IndirectIOTable; - UINT8 *IndirectIOTablePointer; - GENERIC_ATTRIBUTE_COMMAND *pCmd; //CurrentCommand; - SOURCE_DESTINATION_ALIGNMENT CD_Mask; - PARAMETERS_TYPE ParametersType; - CD_GENERIC_BYTE Multipurpose; - UINT8 CompareFlags; - COMMAND_SPECIFIC_UNION CommandSpecific; - CD_STATUS Status; - UINT8 Shift2MaskConverter; - UINT8 CurrentPortID; -} PARSER_TEMP_DATA; - - -typedef struct _WORKING_TABLE_DATA WORKING_TABLE_DATA; - - - -typedef VOID (*COMMANDS_DECODER)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -typedef VOID (*WRITE_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -typedef UINT32 (*READ_IO_FUNCTION)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); -typedef UINT32 (*CD_GET_PARAMETERS)(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -typedef struct _COMMANDS_PROPERTIES -{ - COMMANDS_DECODER function; - UINT8 destination; - UINT8 headersize; -} COMMANDS_PROPERTIES; - -typedef struct _INDIRECT_IO_PARSER_COMMANDS -{ - COMMANDS_DECODER func; - UINT8 csize; -} INDIRECT_IO_PARSER_COMMANDS; - -#if (PARSER_TYPE==DRIVER_TYPE_PARSER) -#pragma pack(pop) -#endif - -#endif diff --git a/src/AtomBios/includes/CD_binding.h b/src/AtomBios/includes/CD_binding.h deleted file mode 100644 index 7b021d3..0000000 --- a/src/AtomBios/includes/CD_binding.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifdef NT_BUILD -#ifdef LH_BUILD -#include <ntddk.h> -#else -#include <miniport.h> -#endif // LH_BUILD -#endif // NT_BUILD - - -#if ((defined DBG) || (defined DEBUG)) -#define DEBUG_PARSER 1 // enable parser debug output -#endif - -#define USE_SWITCH_COMMAND 1 -#define DRIVER_TYPE_PARSER 0x48 - -#define PARSER_TYPE DRIVER_TYPE_PARSER - -#define AllocateWorkSpace(x,y) AllocateMemory(pDeviceData,y) -#define FreeWorkSpace(x,y) ReleaseMemory(x,y) - -#define RELATIVE_TO_BIOS_IMAGE( x ) ((ULONG_PTR)x + (ULONG_PTR)((DEVICE_DATA*)pParserTempData->pDeviceData->pBIOS_Image)) -#define RELATIVE_TO_TABLE( x ) (x + (UCHAR *)(pParserTempData->pWorkingTableData->pTableHead)) - diff --git a/src/AtomBios/includes/CD_hw_services.h b/src/AtomBios/includes/CD_hw_services.h deleted file mode 100644 index 529fde5..0000000 --- a/src/AtomBios/includes/CD_hw_services.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _HW_SERVICES_INTERFACE_ -#define _HW_SERVICES_INTERFACE_ - -#include "CD_Common_Types.h" -#include "CD_Structs.h" - - -// CD - from Command Decoder -typedef UINT16 CD_REG_INDEX; -typedef UINT8 CD_PCI_OFFSET; -typedef UINT16 CD_FB_OFFSET; -typedef UINT16 CD_SYS_IO_PORT; -typedef UINT8 CD_MEM_TYPE; -typedef UINT8 CD_MEM_SIZE; - -typedef VOID * CD_VIRT_ADDR; -typedef UINT32 CD_PHYS_ADDR; -typedef UINT32 CD_IO_ADDR; - -/***********************ATI Registers access routines**************************/ - - VOID ReadIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteIndReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadPLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePLL32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteMC32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/************************PCI Registers access routines*************************/ - - UINT8 ReadPCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT16 ReadPCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadPCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePCIReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePCIReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WritePCIReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/***************************Frame buffer access routines************************/ - - UINT32 ReadFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteFrameBuffer32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/******************System IO Registers access routines********************/ - - UINT8 ReadSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT16 ReadSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - UINT32 ReadSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteSysIOReg8(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteSysIOReg16(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID WriteSysIOReg32(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - -/****************************Delay routines****************************************/ - - VOID DelayMicroseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); // take WORKING_TABLE_DATA->SourceData32 as a delay value - - VOID DelayMilliseconds(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID PostCharOutput(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - VOID CallerDebugFunc(PARSER_TEMP_DATA STACK_BASED * pParserTempData); - - -//************************Tracing/Debugging routines and macroses******************/ -#define KEYPRESSED -1 - -#if (DEBUG_PARSER != 0) - -#ifdef DRIVER_PARSER - -VOID CD_print_string (DEVICE_DATA STACK_BASED *pDeviceData, UINT8 *str); -VOID CD_print_value (DEVICE_DATA STACK_BASED *pDeviceData, ULONG_PTR value, UINT16 value_type ); - -// Level 1 : can use WorkingTableData or pDeviceData -#define CD_TRACE_DL1(string) CD_print_string(pDeviceData, string); -#define CD_TRACETAB_DL1(string) CD_TRACE_DL1("\n");CD_TRACE_DL1(string) -#define CD_TRACEDEC_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_DEC); -#define CD_TRACEHEX_DL1(value) CD_print_value( pDeviceData, (ULONG_PTR)value, PARSER_HEX); - -// Level 2:can use pWorkingTableData -#define CD_TRACE_DL2(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); -#define CD_TRACETAB_DL2(string) CD_TRACE_DL2("\n");CD_TRACE_DL2(string) -#define CD_TRACEDEC_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_DEC); -#define CD_TRACEHEX_DL2(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, (ULONG_PTR)value, PARSER_HEX); - -// Level 3:can use pWorkingTableData -#define CD_TRACE_DL3(string) CD_print_string( pWorkingTableData->pParserTempData->pDeviceData, string); -#define CD_TRACETAB_DL3(string) CD_TRACE_DL3("\n");CD_TRACE_DL3(string) -#define CD_TRACEDEC_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_DEC); -#define CD_TRACEHEX_DL3(value) CD_print_value( pWorkingTableData->pParserTempData->pDeviceData, value, PARSER_HEX); - -#define CD_TRACE(string) -#define CD_WAIT(what) -#define CD_BREAKPOINT() - -#else - - -VOID CD_assert (UINT8 *file, INTN lineno); //output file/line to debug console -VOID CD_postcode(UINT8 value); //output post code to debug console -VOID CD_print (UINT8 *str); //output text to debug console -VOID CD_print_dec(UINTN value); //output value in decimal format to debug console -VOID CD_print_hex(UINT32 value, UINT8 len); //output value in hexadecimal format to debug console -VOID CD_print_buf(UINT8 *p, UINTN len); //output dump of memory to debug console -VOID CD_wait(INT32 what); //wait for KEYPRESSED=-1 or Delay value expires -VOID CD_breakpoint(); //insert int3 opcode or 0xF1 (for American Arium) - -#define CD_ASSERT(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE(value) CD_postcode(value) -#define CD_TRACE(string) CD_print(string) -#define CD_TRACETAB(string) CD_print(string) -#define CD_TRACEDEC(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT(what) CD_wait((INT32)what) -#define CD_BREAKPOINT() CD_breakpoint() - -#if (DEBUG_PARSER == 4) -#define CD_ASSERT_DL4(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL4(value) CD_postcode(value) -#define CD_TRACE_DL4(string) CD_print(string) -#define CD_TRACETAB_DL4(string) CD_print("\n\t\t");CD_print(string) -#define CD_TRACEDEC_DL4(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL4(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL4(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL4(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL4() CD_breakpoint() -#else -#define CD_ASSERT_DL4(condition) -#define CD_POSTCODE_DL4(value) -#define CD_TRACE_DL4(string) -#define CD_TRACETAB_DL4(string) -#define CD_TRACEDEC_DL4(value) -#define CD_TRACEHEX_DL4(value) -#define CD_TRACEBUF_DL4(pointer, len) -#define CD_WAIT_DL4(what) -#define CD_BREAKPOINT_DL4() -#endif - -#if (DEBUG_PARSER >= 3) -#define CD_ASSERT_DL3(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL3(value) CD_postcode(value) -#define CD_TRACE_DL3(string) CD_print(string) -#define CD_TRACETAB_DL3(string) CD_print("\n\t\t");CD_print(string) -#define CD_TRACEDEC_DL3(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL3(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL3(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL3(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL3() CD_breakpoint() -#else -#define CD_ASSERT_DL3(condition) -#define CD_POSTCODE_DL3(value) -#define CD_TRACE_DL3(string) -#define CD_TRACETAB_DL3(string) -#define CD_TRACEDEC_DL3(value) -#define CD_TRACEHEX_DL3(value) -#define CD_TRACEBUF_DL3(pointer, len) -#define CD_WAIT_DL3(what) -#define CD_BREAKPOINT_DL3() -#endif - - -#if (DEBUG_PARSER >= 2) -#define CD_ASSERT_DL2(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL2(value) CD_postcode(value) -#define CD_TRACE_DL2(string) CD_print(string) -#define CD_TRACETAB_DL2(string) CD_print("\n\t");CD_print(string) -#define CD_TRACEDEC_DL2(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL2(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL2(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL2(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL2() CD_breakpoint() -#else -#define CD_ASSERT_DL2(condition) -#define CD_POSTCODE_DL2(value) -#define CD_TRACE_DL2(string) -#define CD_TRACETAB_DL2(string) -#define CD_TRACEDEC_DL2(value) -#define CD_TRACEHEX_DL2(value) -#define CD_TRACEBUF_DL2(pointer, len) -#define CD_WAIT_DL2(what) -#define CD_BREAKPOINT_DL2() -#endif - - -#if (DEBUG_PARSER >= 1) -#define CD_ASSERT_DL1(condition) if(!(condition)) CD_assert(__FILE__, __LINE__) -#define CD_POSTCODE_DL1(value) CD_postcode(value) -#define CD_TRACE_DL1(string) CD_print(string) -#define CD_TRACETAB_DL1(string) CD_print("\n");CD_print(string) -#define CD_TRACEDEC_DL1(value) CD_print_dec( (UINTN)(value)) -#define CD_TRACEHEX_DL1(value) CD_print_hex( (UINT32)(value), sizeof(value) ) -#define CD_TRACEBUF_DL1(pointer, len) CD_print_buf( (UINT8 *)(pointer), (UINTN) len) -#define CD_WAIT_DL1(what) CD_wait((INT32)what) -#define CD_BREAKPOINT_DL1() CD_breakpoint() -#else -#define CD_ASSERT_DL1(condition) -#define CD_POSTCODE_DL1(value) -#define CD_TRACE_DL1(string) -#define CD_TRACETAB_DL1(string) -#define CD_TRACEDEC_DL1(value) -#define CD_TRACEHEX_DL1(value) -#define CD_TRACEBUF_DL1(pointer, len) -#define CD_WAIT_DL1(what) -#define CD_BREAKPOINT_DL1() -#endif - -#endif //#ifdef DRIVER_PARSER - - -#else - -#define CD_ASSERT(condition) -#define CD_POSTCODE(value) -#define CD_TRACE(string) -#define CD_TRACEDEC(value) -#define CD_TRACEHEX(value) -#define CD_TRACEBUF(pointer, len) -#define CD_WAIT(what) -#define CD_BREAKPOINT() - -#define CD_ASSERT_DL4(condition) -#define CD_POSTCODE_DL4(value) -#define CD_TRACE_DL4(string) -#define CD_TRACETAB_DL4(string) -#define CD_TRACEDEC_DL4(value) -#define CD_TRACEHEX_DL4(value) -#define CD_TRACEBUF_DL4(pointer, len) -#define CD_WAIT_DL4(what) -#define CD_BREAKPOINT_DL4() - -#define CD_ASSERT_DL3(condition) -#define CD_POSTCODE_DL3(value) -#define CD_TRACE_DL3(string) -#define CD_TRACETAB_DL3(string) -#define CD_TRACEDEC_DL3(value) -#define CD_TRACEHEX_DL3(value) -#define CD_TRACEBUF_DL3(pointer, len) -#define CD_WAIT_DL3(what) -#define CD_BREAKPOINT_DL3() - -#define CD_ASSERT_DL2(condition) -#define CD_POSTCODE_DL2(value) -#define CD_TRACE_DL2(string) -#define CD_TRACETAB_DL2(string) -#define CD_TRACEDEC_DL2(value) -#define CD_TRACEHEX_DL2(value) -#define CD_TRACEBUF_DL2(pointer, len) -#define CD_WAIT_DL2(what) -#define CD_BREAKPOINT_DL2() - -#define CD_ASSERT_DL1(condition) -#define CD_POSTCODE_DL1(value) -#define CD_TRACE_DL1(string) -#define CD_TRACETAB_DL1(string) -#define CD_TRACEDEC_DL1(value) -#define CD_TRACEHEX_DL1(value) -#define CD_TRACEBUF_DL1(pointer, len) -#define CD_WAIT_DL1(what) -#define CD_BREAKPOINT_DL1() - - -#endif //#if (DEBUG_PARSER > 0) - - -#ifdef CHECKSTACK -VOID CD_fillstack(UINT16 size); -UINT16 CD_checkstack(UINT16 size); -#define CD_CHECKSTACK(stacksize) CD_checkstack(stacksize) -#define CD_FILLSTACK(stacksize) CD_fillstack(stacksize) -#else -#define CD_CHECKSTACK(stacksize) 0 -#define CD_FILLSTACK(stacksize) -#endif - - -#endif diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h deleted file mode 100644 index 24c25fc..0000000 --- a/src/AtomBios/includes/Decoder.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/*++ - -Module Name: - -Decoder.h - -Abstract: - -Includes all helper headers - -Revision History: - -NEG:27.08.2002 Initiated. ---*/ -#ifndef _DECODER_H_ -#define _DECODER_H_ -#define WS_QUOTIENT_C 64 -#define WS_REMINDER_C (WS_QUOTIENT_C+1) -#define WS_DATAPTR_C (WS_REMINDER_C+1) -#define WS_SHIFT_C (WS_DATAPTR_C+1) -#define WS_OR_MASK_C (WS_SHIFT_C+1) -#define WS_AND_MASK_C (WS_OR_MASK_C+1) -#define WS_FB_WINDOW_C (WS_AND_MASK_C+1) -#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1) -#define PARSER_VERSION_MAJOR 0x00000000 -#define PARSER_VERSION_MINOR 0x0000000E -#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR) -#include "CD_binding.h" -#include "CD_Common_Types.h" -#include "CD_hw_services.h" -#include "CD_Structs.h" -#include "CD_Definitions.h" -#include "CD_Opcodes.h" - -#define SOURCE_ONLY_CMD_TYPE 0//0xFE -#define SOURCE_DESTINATION_CMD_TYPE 1//0xFD -#define DESTINATION_ONLY_CMD_TYPE 2//0xFC - -#define ACCESS_TYPE_BYTE 0//0xF9 -#define ACCESS_TYPE_WORD 1//0xF8 -#define ACCESS_TYPE_DWORD 2//0xF7 -#define SWITCH_TYPE_ACCESS 3//0xF6 - -#define CD_CONTINUE 0//0xFB -#define CD_STOP 1//0xFA - - -#define IS_END_OF_TABLE(cmd) ((cmd) == EOT_OPCODE) -#define IS_COMMAND_VALID(cmd) (((cmd)<=LastValidCommand)&&((cmd)>=FirstValidCommand)) -#define IS_IT_SHIFT_COMMAND(Opcode) ((Opcode<=SHIFT_RIGHT_MC_OPCODE)&&(Opcode>=SHIFT_LEFT_REG_OPCODE)) -#define IS_IT_XXXX_COMMAND(Group, Opcode) ((Opcode<=Group##_MC_OPCODE)&&(Opcode>=Group##_REG_OPCODE)) -#define CheckCaseAndAdjustIP_Macro(size) \ - if (pParserTempData->SourceData32==(UINT32)((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.Value){\ - pParserTempData->CommandSpecific.ContinueSwitch = CD_STOP;\ - pParserTempData->pWorkingTableData->IP =(COMMAND_HEADER_POINTER *) RELATIVE_TO_TABLE(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->XX_Access.size##.Access.JumpOffset);\ - }else{\ - pParserTempData->pWorkingTableData->IP+=(sizeof (CASE_##size##ACCESS)\ - +sizeof(((CASE_OFFSET*)pParserTempData->pWorkingTableData->IP)->CaseSignature));\ - } - -#endif -/* pWorkingTableData->pCmd->Header.Attribute.SourceAlignment=alignmentLowerWord;\*/ - -// EOF diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h deleted file mode 100644 index e6d41fe..0000000 --- a/src/AtomBios/includes/ObjectID.h +++ /dev/null @@ -1,484 +0,0 @@ -/* -* Copyright 2006-2007 Advanced Micro Devices, Inc. -* -* Permission is hereby granted, free of charge, to any person obtaining a -* copy of this software and associated documentation files (the "Software"), -* to deal in the Software without restriction, including without limitation -* the rights to use, copy, modify, merge, publish, distribute, sublicense, -* and/or sell copies of the Software, and to permit persons to whom the -* Software is furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR -* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -* OTHER DEALINGS IN THE SOFTWARE. -*/
-/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
-
-#ifndef _OBJECTID_H
-#define _OBJECTID_H
-
-#if defined(_X86_)
-#pragma pack(1)
-#endif
-
-/****************************************************/
-/* Graphics Object Type Definition */
-/****************************************************/
-#define GRAPH_OBJECT_TYPE_NONE 0x0
-#define GRAPH_OBJECT_TYPE_GPU 0x1
-#define GRAPH_OBJECT_TYPE_ENCODER 0x2
-#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
-#define GRAPH_OBJECT_TYPE_ROUTER 0x4
-/* deleted */
-
-/****************************************************/
-/* Encoder Object ID Definition */
-/****************************************************/
-#define ENCODER_OBJECT_ID_NONE 0x00
-
-/* Radeon Class Display Hardware */
-#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
-#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02
-#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03
-#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04
-#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */
-#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06
-#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07
-
-/* External Third Party Encoders */
-#define ENCODER_OBJECT_ID_SI170B 0x08
-#define ENCODER_OBJECT_ID_CH7303 0x09
-#define ENCODER_OBJECT_ID_CH7301 0x0A
-#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */
-#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C
-#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D
-#define ENCODER_OBJECT_ID_TITFP513 0x0E
-#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */
-#define ENCODER_OBJECT_ID_VT1623 0x10
-#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
-#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
-/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */
-#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */
-#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */
-#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19
-#define ENCODER_OBJECT_ID_VT1625 0x1A
-#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B
-#define ENCODER_OBJECT_ID_DP_AN9801 0x1C
-#define ENCODER_OBJECT_ID_DP_DP501 0x1D
-#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E
-#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F
-
-/****************************************************/
-/* Connector Object ID Definition */
-/****************************************************/
-#define CONNECTOR_OBJECT_ID_NONE 0x00
-#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
-#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
-#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
-#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04
-#define CONNECTOR_OBJECT_ID_VGA 0x05
-#define CONNECTOR_OBJECT_ID_COMPOSITE 0x06
-#define CONNECTOR_OBJECT_ID_SVIDEO 0x07
-#define CONNECTOR_OBJECT_ID_YPbPr 0x08
-#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09
-#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */
-#define CONNECTOR_OBJECT_ID_SCART 0x0B
-#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C
-#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D
-#define CONNECTOR_OBJECT_ID_LVDS 0x0E
-#define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F
-#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10
-#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11
-#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12
-#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
-
-/* deleted */
-
-/****************************************************/
-/* Router Object ID Definition */
-/****************************************************/
-#define ROUTER_OBJECT_ID_NONE 0x00
-#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01
-
-/****************************************************/
-// Graphics Object ENUM ID Definition */
-/****************************************************/
-#define GRAPH_OBJECT_ENUM_ID1 0x01
-#define GRAPH_OBJECT_ENUM_ID2 0x02
-#define GRAPH_OBJECT_ENUM_ID3 0x03
-#define GRAPH_OBJECT_ENUM_ID4 0x04
-
-/****************************************************/
-/* Graphics Object ID Bit definition */
-/****************************************************/
-#define OBJECT_ID_MASK 0x00FF
-#define ENUM_ID_MASK 0x0700
-#define RESERVED1_ID_MASK 0x0800
-#define OBJECT_TYPE_MASK 0x7000
-#define RESERVED2_ID_MASK 0x8000
-
-#define OBJECT_ID_SHIFT 0x00
-#define ENUM_ID_SHIFT 0x08
-#define OBJECT_TYPE_SHIFT 0x0C
-
-
-/****************************************************/
-/* Graphics Object family definition */
-/****************************************************/
-#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
- GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT)
-/****************************************************/
-/* GPU Object ID definition - Shared with BIOS */
-/****************************************************/
-#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
-
-/****************************************************/
-/* Encoder Object ID definition - Shared with BIOS */
-/****************************************************/
-/*
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
-#define ENCODER_SIL170B_ENUM_ID1 0x2108
-#define ENCODER_CH7303_ENUM_ID1 0x2109
-#define ENCODER_CH7301_ENUM_ID1 0x210A
-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C
-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D
-#define ENCODER_TITFP513_ENUM_ID1 0x210E
-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F
-#define ENCODER_VT1623_ENUM_ID1 0x2110
-#define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111
-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
-#define ENCODER_SI178_ENUM_ID1 0x2117
-#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
-#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
-#define ENCODER_VT1625_ENUM_ID1 0x211A
-#define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B
-#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C
-#define ENCODER_DP_DP501_ENUM_ID1 0x211D
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E
-*/
-#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
-
-#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
-
-
-#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT
-
-#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
-
-#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
-
-#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
-
-#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
-
-#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
-
-#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
-
-/****************************************************/
-/* Connector Object ID definition - Shared with BIOS */
-/****************************************************/
-/*
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103
-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104
-#define CONNECTOR_VGA_ENUM_ID1 0x3105
-#define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106
-#define CONNECTOR_SVIDEO_ENUM_ID1 0x3107
-#define CONNECTOR_YPbPr_ENUM_ID1 0x3108
-#define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109
-#define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A
-#define CONNECTOR_SCART_ENUM_ID1 0x310B
-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C
-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D
-#define CONNECTOR_LVDS_ENUM_ID1 0x310E
-#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110
-*/
-#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
-
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
- CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
-
-/****************************************************/
-/* Router Object ID definition - Shared with BIOS */
-/****************************************************/
-#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
- GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
- ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
-
-/* deleted */
-
-/****************************************************/
-/* Object Cap definition - Shared with BIOS */
-/****************************************************/
-#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L
-#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L
-
-
-#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01
-#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02
-#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03
-
-#if defined(_X86_)
-#pragma pack()
-#endif
-
-#endif /*GRAPHICTYPE */
-
-
-
-
diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h deleted file mode 100644 index 16fcf2d..0000000 --- a/src/AtomBios/includes/atombios.h +++ /dev/null @@ -1,4436 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - - -/****************************************************************************/ -/*Portion I: Definitions shared between VBIOS and Driver */ -/****************************************************************************/ - - -#ifndef _ATOMBIOS_H -#define _ATOMBIOS_H - -#define ATOM_VERSION_MAJOR 0x00020000 -#define ATOM_VERSION_MINOR 0x00000002 - -#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) - - -#ifdef _H2INC - #ifndef ULONG - typedef unsigned long ULONG; - #endif - - #ifndef UCHAR - typedef unsigned char UCHAR; - #endif - - #ifndef USHORT - typedef unsigned short USHORT; - #endif -#endif - -#define ATOM_DAC_A 0 -#define ATOM_DAC_B 1 -#define ATOM_EXT_DAC 2 - -#define ATOM_CRTC1 0 -#define ATOM_CRTC2 1 - -#define ATOM_DIGA 0 -#define ATOM_DIGB 1 - -#define ATOM_PPLL1 0 -#define ATOM_PPLL2 1 - -#define ATOM_SCALER1 0 -#define ATOM_SCALER2 1 - -#define ATOM_SCALER_DISABLE 0 -#define ATOM_SCALER_CENTER 1 -#define ATOM_SCALER_EXPANSION 2 -#define ATOM_SCALER_MULTI_EX 3 - -#define ATOM_DISABLE 0 -#define ATOM_ENABLE 1 -#define ATOM_LCD_BLOFF (ATOM_DISABLE+2) -#define ATOM_LCD_BLON (ATOM_ENABLE+2) -#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) -#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) -#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) -#define ATOM_ENCODER_INIT (ATOM_DISABLE+7) - -#define ATOM_BLANKING 1 -#define ATOM_BLANKING_OFF 0 - -#define ATOM_CURSOR1 0 -#define ATOM_CURSOR2 1 - -#define ATOM_ICON1 0 -#define ATOM_ICON2 1 - -#define ATOM_CRT1 0 -#define ATOM_CRT2 1 - -#define ATOM_TV_NTSC 1 -#define ATOM_TV_NTSCJ 2 -#define ATOM_TV_PAL 3 -#define ATOM_TV_PALM 4 -#define ATOM_TV_PALCN 5 -#define ATOM_TV_PALN 6 -#define ATOM_TV_PAL60 7 -#define ATOM_TV_SECAM 8 -#define ATOM_TV_CV 16 - -#define ATOM_DAC1_PS2 1 -#define ATOM_DAC1_CV 2 -#define ATOM_DAC1_NTSC 3 -#define ATOM_DAC1_PAL 4 - -#define ATOM_DAC2_PS2 ATOM_DAC1_PS2 -#define ATOM_DAC2_CV ATOM_DAC1_CV -#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC -#define ATOM_DAC2_PAL ATOM_DAC1_PAL - -#define ATOM_PM_ON 0 -#define ATOM_PM_STANDBY 1 -#define ATOM_PM_SUSPEND 2 -#define ATOM_PM_OFF 3 - -/* Bit0:{=0:single, =1:dual}, - Bit1 {=0:666RGB, =1:888RGB}, - Bit2:3:{Grey level} - Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ - -#define ATOM_PANEL_MISC_DUAL 0x00000001 -#define ATOM_PANEL_MISC_888RGB 0x00000002 -#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C -#define ATOM_PANEL_MISC_FPDI 0x00000010 -#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 -#define ATOM_PANEL_MISC_SPATIAL 0x00000020 -#define ATOM_PANEL_MISC_TEMPORAL 0x00000040 -#define ATOM_PANEL_MISC_API_ENABLED 0x00000080 - - -#define MEMTYPE_DDR1 "DDR1" -#define MEMTYPE_DDR2 "DDR2" -#define MEMTYPE_DDR3 "DDR3" -#define MEMTYPE_DDR4 "DDR4" - -#define ASIC_BUS_TYPE_PCI "PCI" -#define ASIC_BUS_TYPE_AGP "AGP" -#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" - -/* Maximum size of that FireGL flag string */ - -#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support -#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) - -#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop -#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING - -#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support -#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) - -#define HW_ASSISTED_I2C_STATUS_FAILURE 2 -#define HW_ASSISTED_I2C_STATUS_SUCCESS 1 - -#pragma pack(1) /* BIOS data must use byte aligment */ - -/* Define offset to location of ROM header. */ - -#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L -#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L - -#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 -#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ -#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f -#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e - -/* Common header for all ROM Data tables. - Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. - And the pointer actually points to this header. */ - -typedef struct _ATOM_COMMON_TABLE_HEADER -{ - USHORT usStructureSize; - UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ - UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ - /*Image can't be updated, while Driver needs to carry the new table! */ -}ATOM_COMMON_TABLE_HEADER; - -typedef struct _ATOM_ROM_HEADER -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, - atombios should init it as "ATOM", don't change the position */ - USHORT usBiosRuntimeSegmentAddress; - USHORT usProtectedModeInfoOffset; - USHORT usConfigFilenameOffset; - USHORT usCRC_BlockOffset; - USHORT usBIOS_BootupMessageOffset; - USHORT usInt10Offset; - USHORT usPciBusDevInitCode; - USHORT usIoBaseAddress; - USHORT usSubsystemVendorID; - USHORT usSubsystemID; - USHORT usPCI_InfoOffset; - USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ - USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ - UCHAR ucExtendedFunctionCode; - UCHAR ucReserved; -}ATOM_ROM_HEADER; - -/*==============================Command Table Portion==================================== */ - -#ifdef UEFI_BUILD - #define UTEMP USHORT - #define USHORT void* -#endif - -typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ - USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 - USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON - USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios - USHORT DIGxEncoderControl; //Only used by Bios - USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 - USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed - USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 - USHORT GPIOPinControl; //Atomic Table, only used by Bios - USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 - USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 - USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 - USHORT DynamicClockGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT MemoryPLLInit; - USHORT AdjustDisplayPll; //only used by Bios - USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios - USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios - USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 - USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 - USHORT LCD1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT CV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetConditionalGoldenSetting; //only used by Bios - USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 - USHORT TMDSAEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 - USHORT LVDSEncoderControl; //Atomic Table, directly used by various SW components,latest version 1.3 - USHORT TV1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableScaler; //Atomic Table, used only by Bios - USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 - USHORT EnableVGA_Access; //Obsolete , only used by Bios - USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 - USHORT SetCRTC_Replication; //Atomic Table, used only by Bios - USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios - USHORT UpdateCRTC_DoubleBufferRegisters; - USHORT LUT_AutoFill; //Atomic Table, only used by Bios - USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios - USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 - USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT VRAM_BlockDetectionByStrap; - USHORT MemoryCleanUp; //Atomic Table, only used by Bios - USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios - USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components - USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components - USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init - USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock - USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock - USHORT VRAM_GetCurrentInfoBlock; - USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT MemoryTraining; - USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 - USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 - USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetupHWAssistedI2CStatus; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" - USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init - USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock - USHORT EnableYUV; //Atomic Table, indirectly used by various SW components,called from EnableVGARender - USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios - USHORT DPEncoderService; //Function Table,only used by Bios -}ATOM_MASTER_LIST_OF_COMMAND_TABLES; - -#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction - -#define UNIPHYTransmitterControl DIG1TransmitterControl -#define LVTMATransmitterControl DIG2TransmitterControl -#define SetCRTC_DPM_State GetConditionalGoldenSetting - -typedef struct _ATOM_MASTER_COMMAND_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; -}ATOM_MASTER_COMMAND_TABLE; - -typedef struct _ATOM_TABLE_ATTRIBUTE -{ - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), - USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag -}ATOM_TABLE_ATTRIBUTE; - -// Common header for all command tables. -//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. -//And the pointer actually points to this header. - -typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER -{ - ATOM_COMMON_TABLE_HEADER CommonHeader; - ATOM_TABLE_ATTRIBUTE TableAttribute; -}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; - - -typedef struct _ASIC_INIT_PARAMETERS -{ - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit -}ASIC_INIT_PARAMETERS; - -#define COMPUTE_MEMORY_PLL_PARAM 1 -#define COMPUTE_ENGINE_PLL_PARAM 2 - -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS -{ - ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div - UCHAR ucAction; //0:reserved //1:Memory //2:Engine - UCHAR ucReserved; //may expand to return larger Fbdiv later - UCHAR ucFbDiv; //return value - UCHAR ucPostDiv; //return value -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; - -typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 -{ - ULONG ulClock; //When return, [23:0] return real clock - UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register - USHORT usFbDiv; //return Feedback value to be written to register - UCHAR ucPostDiv; //return post div to be written to register -}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; -#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS - - -#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value -#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) -#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition -#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change -#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup -#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL -#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK - -#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) -#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition -#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change -#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup -#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL - -typedef struct _SET_ENGINE_CLOCK_PARAMETERS -{ - ULONG ulTargetEngineClock; //In 10Khz unit -}SET_ENGINE_CLOCK_PARAMETERS; - -typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION -{ - ULONG ulTargetEngineClock; //In 10Khz unit - COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -}SET_ENGINE_CLOCK_PS_ALLOCATION; - - -typedef struct _SET_MEMORY_CLOCK_PARAMETERS -{ - ULONG ulTargetMemoryClock; //In 10Khz unit -}SET_MEMORY_CLOCK_PARAMETERS; - -typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION -{ - ULONG ulTargetMemoryClock; //In 10Khz unit - COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; -}SET_MEMORY_CLOCK_PS_ALLOCATION; - -typedef struct _ASIC_INIT_PS_ALLOCATION -{ - ASIC_INIT_PARAMETERS sASICInitClocks; - SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure -}ASIC_INIT_PS_ALLOCATION; - - -typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[3]; -}DYNAMIC_CLOCK_GATING_PARAMETERS; -#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS - - -typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[3]; -}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; -#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS - - -typedef struct _DAC_LOAD_DETECTION_PARAMETERS -{ - USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} - UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} - UCHAR ucMisc; //Valid only when table revision =1.3 and above -}DAC_LOAD_DETECTION_PARAMETERS; - -// DAC_LOAD_DETECTION_PARAMETERS.ucMisc -#define DAC_LOAD_MISC_YPrPb 0x01 - - -typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION -{ - DAC_LOAD_DETECTION_PARAMETERS sDacload; - ULONG Reserved[2];// Don't set this one, allocation for EXT DAC -}DAC_LOAD_DETECTION_PS_ALLOCATION; - - -typedef struct _DAC_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder - // 7: ATOM_ENCODER_INIT Initialize DAC -}DAC_ENCODER_CONTROL_PARAMETERS; - -#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS - -typedef struct _TV_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder -}TV_ENCODER_CONTROL_PARAMETERS; - -typedef struct _DIG_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucConfig; - // [2] Link Select: - // =0: PHY linkA if bfLane<3 - // =1: PHY linkB if bfLanes<3 - // =0: PHY linkA+B if bfLanes=3 - // [3] Transmitter Sel - // =0: UNIPHY or PCIEPHY - // =1: LVTMA - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder - UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder - // =3: HDMI encoder - // =4: SDVO encoder - UCHAR ucLaneNum; // how many lanes to enable - UCHAR ucReserved[2]; -}DIG_ENCODER_CONTROL_PARAMETERS; -#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS -#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS -#define EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PS_ALLOCATION - -//ucConfig -#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 -#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 -#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 -#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 -#define ATOM_ENCODER_CONFIG_LINKA 0x00 -#define ATOM_ENCODER_CONFIG_LINKB 0x04 -#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA -#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB -#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 -#define ATOM_ENCODER_CONFIG_UNIPHY 0x00 -#define ATOM_ENCODER_CONFIG_LVTMA 0x08 -#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 -#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 -#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 -// ucAction -// ATOM_ENABLE: Enable Encoder -// ATOM_DISABLE: Disable Encoder - -//ucEncoderMode -#define ATOM_ENCODER_MODE_DP 0 -#define ATOM_ENCODER_MODE_LVDS 1 -#define ATOM_ENCODER_MODE_DVI 2 -#define ATOM_ENCODER_MODE_HDMI 3 -#define ATOM_ENCODER_MODE_SDVO 4 -#define ATOM_ENCODER_MODE_TV 13 -#define ATOM_ENCODER_MODE_CV 14 -#define ATOM_ENCODER_MODE_CRT 15 - -typedef struct _ATOM_DP_VS_MODE -{ - UCHAR ucLaneSel; - UCHAR ucLaneSet; -}ATOM_DP_VS_MODE; - -typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS -{ - union - { - USHORT usPixelClock; // in 10KHz; for bios convenient - USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h - ATOM_DP_VS_MODE asMode; // DP Voltage swing mode - }; - UCHAR ucConfig; - // [0]=0: 4 lane Link, - // =1: 8 lane Link ( Dual Links TMDS ) - // [1]=0: InCoherent mode - // =1: Coherent Mode - // [2] Link Select: - // =0: PHY linkA if bfLane<3 - // =1: PHY linkB if bfLanes<3 - // =0: PHY linkA+B if bfLanes=3 - // [5:4]PCIE lane Sel - // =0: lane 0~3 or 0~7 - // =1: lane 4~7 - // =2: lane 8~11 or 8~15 - // =3: lane 12~15 - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder - UCHAR ucReserved[4]; -}DIG_TRANSMITTER_CONTROL_PARAMETERS; - -#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS - -//ucInitInfo -#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff - -//ucConfig -#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 -#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 -#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 -#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 -#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 -#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 -#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 - -#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE -#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE -#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE - -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 -#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 -#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 -#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 -#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 -#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 -#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 -#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 -#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 - -//ucAction -#define ATOM_TRANSMITTER_ACTION_DISABLE 0 -#define ATOM_TRANSMITTER_ACTION_ENABLE 1 -#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 -#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 -#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 -#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 -#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 -#define ATOM_TRANSMITTER_ACTION_INIT 7 -#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 -#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 -#define ATOM_TRANSMITTER_ACTION_SETUP 10 -#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 - -/****************************Device Output Control Command Table Definitions**********************/ -typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -{ - UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE - // When the display is LCD, in addition to above: - // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| - // ATOM_LCD_SELFTEST_STOP - - UCHAR aucPadding[3]; // padding to DWORD aligned -}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; - -#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS - - -#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION - -#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION -#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS - -/**************************************************************************/ -typedef struct _BLANK_CRTC_PARAMETERS -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF - USHORT usBlackColorRCr; - USHORT usBlackColorGY; - USHORT usBlackColorBCb; -}BLANK_CRTC_PARAMETERS; -#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS - - -typedef struct _ENABLE_CRTC_PARAMETERS -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[2]; -}ENABLE_CRTC_PARAMETERS; -#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS - - -typedef struct _SET_CRTC_OVERSCAN_PARAMETERS -{ - USHORT usOverscanRight; // right - USHORT usOverscanLeft; // left - USHORT usOverscanBottom; // bottom - USHORT usOverscanTop; // top - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucPadding[3]; -}SET_CRTC_OVERSCAN_PARAMETERS; -#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS - - -typedef struct _SET_CRTC_REPLICATION_PARAMETERS -{ - UCHAR ucH_Replication; // horizontal replication - UCHAR ucV_Replication; // vertical replication - UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucPadding; -}SET_CRTC_REPLICATION_PARAMETERS; -#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS - - -typedef struct _SELECT_CRTC_SOURCE_PARAMETERS -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... - UCHAR ucPadding[2]; -}SELECT_CRTC_SOURCE_PARAMETERS; -#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS - -typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 -{ - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO - UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO - UCHAR ucPadding; -}SELECT_CRTC_SOURCE_PARAMETERS_V2; - -//ucEncoderID -//#define ASIC_INT_DAC1_ENCODER_ID 0x00 -//#define ASIC_INT_TV_ENCODER_ID 0x02 -//#define ASIC_INT_DIG1_ENCODER_ID 0x03 -//#define ASIC_INT_DAC2_ENCODER_ID 0x04 -//#define ASIC_EXT_TV_ENCODER_ID 0x06 -//#define ASIC_INT_DVO_ENCODER_ID 0x07 -//#define ASIC_INT_DIG2_ENCODER_ID 0x09 -//#define ASIC_EXT_DIG_ENCODER_ID 0x05 - -//ucEncodeMode -//#define ATOM_ENCODER_MODE_DP 0 -//#define ATOM_ENCODER_MODE_LVDS 1 -//#define ATOM_ENCODER_MODE_DVI 2 -//#define ATOM_ENCODER_MODE_HDMI 3 -//#define ATOM_ENCODER_MODE_SDVO 4 -//#define ATOM_ENCODER_MODE_TV 13 -//#define ATOM_ENCODER_MODE_CV 14 -//#define ATOM_ENCODER_MODE_CRT 15 - -//Major revision=1., Minor revision=1 -typedef struct _PIXEL_CLOCK_PARAMETERS -{ - USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) - // 0 means disable PPLL - USHORT usRefDiv; // Reference divider - USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider - UCHAR ucFracFbDiv; // fractional feedback divider - UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 - UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER - UCHAR ucCRTC; // Which CRTC uses this Ppll - UCHAR ucPadding; -}PIXEL_CLOCK_PARAMETERS; - - -//Major revision=1., Minor revision=2, add ucMiscIfno -//ucMiscInfo: -#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 -#define MISC_DEVICE_INDEX_MASK 0xF0 -#define MISC_DEVICE_INDEX_SHIFT 4 - -typedef struct _PIXEL_CLOCK_PARAMETERS_V2 -{ - USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) - // 0 means disable PPLL - USHORT usRefDiv; // Reference divider - USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider - UCHAR ucFracFbDiv; // fractional feedback divider - UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 - UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER - UCHAR ucCRTC; // Which CRTC uses this Ppll - UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog -}PIXEL_CLOCK_PARAMETERS_V2; - -//Major revision=1., Minor revision=3, structure/definition change -//ucEncoderMode: -//ATOM_ENCODER_MODE_DP -//ATOM_ENOCDER_MODE_LVDS -//ATOM_ENOCDER_MODE_DVI -//ATOM_ENOCDER_MODE_HDMI -//ATOM_ENOCDER_MODE_SDVO -//ATOM_ENCODER_MODE_TV 13 -//ATOM_ENCODER_MODE_CV 14 -//ATOM_ENCODER_MODE_CRT 15 - -//ucDVOConfig -//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 -//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 -//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 -//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c -//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 -//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 -//#define DVO_ENCODER_CONFIG_24BIT 0x08 - -//ucMiscInfo: also changed, see below -#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 -#define PIXEL_CLOCK_MISC_VGA_MODE 0x02 -#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 -#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 -#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 -#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 - -typedef struct _PIXEL_CLOCK_PARAMETERS_V3 -{ - USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) - // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. - USHORT usRefDiv; // Reference divider - USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider - UCHAR ucFracFbDiv; // fractional feedback divider - UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 - UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h - union - { - UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ - UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit - }; - UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel - // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source -}PIXEL_CLOCK_PARAMETERS_V3; - -#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 -#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST - -typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS -{ - USHORT usPixelClock; - UCHAR ucTransmitterID; - UCHAR ucEncodeMode; - union - { - UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit - UCHAR ucConfig; //if none DVO, not defined yet - }; - UCHAR ucReserved[3]; -}ADJUST_DISPLAY_PLL_PARAMETERS; - -#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 - -#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS - -typedef struct _ENABLE_YUV_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) - UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format - UCHAR ucPadding[2]; -}ENABLE_YUV_PARAMETERS; -#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS - -typedef struct _GET_MEMORY_CLOCK_PARAMETERS -{ - ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit -} GET_MEMORY_CLOCK_PARAMETERS; -#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS - - -typedef struct _GET_ENGINE_CLOCK_PARAMETERS -{ - ULONG ulReturnEngineClock; // current engine speed in 10KHz unit -} GET_ENGINE_CLOCK_PARAMETERS; -#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS - - -//Maxium 8 bytes,the data read in will be placed in the parameter space. -//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed -typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS -{ - USHORT usPrescale; //Ratio between Engine clock and I2C clock - USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID - USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status - //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte - UCHAR ucSlaveAddr; //Read from which slave - UCHAR ucLineNumber; //Read from which HW assisted line -}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; -#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS - - -#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 -#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 -#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 -#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 -#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 - -typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS -{ - USHORT usPrescale; //Ratio between Engine clock and I2C clock - USHORT usByteOffset; //Write to which byte - //Upper portion of usByteOffset is Format of data - //1bytePS+offsetPS - //2bytesPS+offsetPS - //blockID+offsetPS - //blockID+offsetID - //blockID+counterID+offsetID - UCHAR ucData; //PS data1 - UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 - UCHAR ucSlaveAddr; //Write to which slave - UCHAR ucLineNumber; //Write from which HW assisted line -}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; - -#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS - -typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS -{ - USHORT usPrescale; //Ratio between Engine clock and I2C clock - UCHAR ucSlaveAddr; //Write to which slave - UCHAR ucLineNumber; //Write from which HW assisted line -}SET_UP_HW_I2C_DATA_PARAMETERS; - - -/**************************************************************************/ -#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS - -typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS -{ - UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected - UCHAR ucPwrBehaviorId; - USHORT usPwrBudget; //how much power currently boot to in unit of watt -}POWER_CONNECTOR_DETECTION_PARAMETERS; - -typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION -{ - UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected - UCHAR ucReserved; - USHORT usPwrBudget; //how much power currently boot to in unit of watt - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -}POWER_CONNECTOR_DETECTION_PS_ALLOCATION; - -/****************************LVDS SS Command Table Definitions**********************/ -typedef struct _ENABLE_LVDS_SS_PARAMETERS -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD - UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY - UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[3]; -}ENABLE_LVDS_SS_PARAMETERS; - -//ucTableFormatRevision=1,ucTableContentRevision=2 -typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD - UCHAR ucSpreadSpectrumStep; // - UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE - UCHAR ucSpreadSpectrumDelay; - UCHAR ucSpreadSpectrumRange; - UCHAR ucPadding; -}ENABLE_LVDS_SS_PARAMETERS_V2; - -//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. -typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD - UCHAR ucSpreadSpectrumStep; // - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucSpreadSpectrumDelay; - UCHAR ucSpreadSpectrumRange; - UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 -}ENABLE_SPREAD_SPECTRUM_ON_PPLL; - -#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL - -/**************************************************************************/ - -typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION -{ - PIXEL_CLOCK_PARAMETERS sPCLKInput; - ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion -}SET_PIXEL_CLOCK_PS_ALLOCATION; - -#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION - -typedef struct _MEMORY_TRAINING_PARAMETERS -{ - ULONG ulTargetMemoryClock; //In 10Khz unit -}MEMORY_TRAINING_PARAMETERS; -#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS - - - -/****************************LVDS and other encoder command table definitions **********************/ -typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucMisc; // bit0=0: Enable single link - // =1: Enable dual link - // Bit1=0: 666RGB - // =1: 888RGB - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder -}LVDS_ENCODER_CONTROL_PARAMETERS; - -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS - -#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS - -#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS - -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS -{ - UCHAR ucEnable; // Enable or Disable External TMDS encoder - UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} - UCHAR ucPadding[2]; -}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; - -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION -{ - ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion -}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; - - -//ucTableFormatRevision=1,ucTableContentRevision=2 -typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 -{ - USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below - UCHAR ucAction; // 0: turn off encoder - // 1: setup and turn on encoder - UCHAR ucTruncate; // bit0=0: Disable truncate - // =1: Enable truncate - // bit4=0: 666RGB - // =1: 888RGB - UCHAR ucSpatial; // bit0=0: Disable spatial dithering - // =1: Enable spatial dithering - // bit4=0: 666RGB - // =1: 888RGB - UCHAR ucTemporal; // bit0=0: Disable temporal dithering - // =1: Enable temporal dithering - // bit4=0: 666RGB - // =1: 888RGB - // bit5=0: Gray level 2 - // =1: Gray level 4 - UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E - // =1: 25FRC_SEL pattern F - // bit6:5=0: 50FRC_SEL pattern A - // =1: 50FRC_SEL pattern B - // =2: 50FRC_SEL pattern C - // =3: 50FRC_SEL pattern D - // bit7=0: 75FRC_SEL pattern E - // =1: 75FRC_SEL pattern F -}LVDS_ENCODER_CONTROL_PARAMETERS_V2; - -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 - -#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 - -#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 -#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 - -typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 -{ - ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion -}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; - - -//ucTableFormatRevision=1,ucTableContentRevision=3 - -//ucDVOConfig: -#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 -#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 -#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 -#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c -#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 -#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 -#define DVO_ENCODER_CONFIG_24BIT 0x08 - -typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 -{ - USHORT usPixelClock; - UCHAR ucDVOConfig; - UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT - UCHAR ucReseved[4]; -}DVO_ENCODER_CONTROL_PARAMETERS_V3; -#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 - -//ucTableFormatRevision=1 -//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for -// bit1=0: non-coherent mode -// =1: coherent mode - -#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 - -#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 - -#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 - -//========================================================================================== -//Only change is here next time when changing encoder parameter definitions again! -#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST - -#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST - -#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 -#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST - -#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS -#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION - -//========================================================================================== -#define PANEL_ENCODER_MISC_DUAL 0x01 -#define PANEL_ENCODER_MISC_COHERENT 0x02 -#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 -#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 - -#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE -#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE -#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) - -#define PANEL_ENCODER_TRUNCATE_EN 0x01 -#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 -#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 -#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 -#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 -#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 -#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 -#define PANEL_ENCODER_25FRC_MASK 0x10 -#define PANEL_ENCODER_25FRC_E 0x00 -#define PANEL_ENCODER_25FRC_F 0x10 -#define PANEL_ENCODER_50FRC_MASK 0x60 -#define PANEL_ENCODER_50FRC_A 0x00 -#define PANEL_ENCODER_50FRC_B 0x20 -#define PANEL_ENCODER_50FRC_C 0x40 -#define PANEL_ENCODER_50FRC_D 0x60 -#define PANEL_ENCODER_75FRC_MASK 0x80 -#define PANEL_ENCODER_75FRC_E 0x00 -#define PANEL_ENCODER_75FRC_F 0x80 - -/**************************************************************************/ - -#define SET_VOLTAGE_TYPE_ASIC_VDDC 1 -#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 -#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 -#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 - -#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 -#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 -#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 - -#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 -#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 -#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 - -typedef struct _SET_VOLTAGE_PARAMETERS -{ - UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ - UCHAR ucVoltageMode; // To set all, to set source A or source B or ... - UCHAR ucVoltageIndex; // An index to tell which voltage level - UCHAR ucReserved; -}SET_VOLTAGE_PARAMETERS; - - -typedef struct _SET_VOLTAGE_PARAMETERS_V2 -{ - UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ - UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode - USHORT usVoltageLevel; // real voltage level -}SET_VOLTAGE_PARAMETERS_V2; - - -typedef struct _SET_VOLTAGE_PS_ALLOCATION -{ - SET_VOLTAGE_PARAMETERS sASICSetVoltage; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; -}SET_VOLTAGE_PS_ALLOCATION; - -typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION -{ - TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one -}TV_ENCODER_CONTROL_PS_ALLOCATION; - -//==============================Data Table Portion==================================== - -#ifdef UEFI_BUILD - #define UTEMP USHORT - #define USHORT void* -#endif - -typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES -{ - USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! - USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios - USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios - USHORT StandardVESA_Timing; // Only used by Bios - USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 - USHORT DAC_Info; // Will be obsolete from R600 - USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 - USHORT TMDS_Info; // Will be obsolete from R600 - USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 - USHORT SupportedDevicesInfo; // Will be obsolete from R600 - USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 - USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 - USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 - USHORT VESA_ToInternalModeLUT; // Only used by Bios - USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 - USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 - USHORT CompassionateData; // Will be obsolete from R600 - USHORT SaveRestoreInfo; // Only used by Bios - USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info - USHORT OemInfo; // Defined and used by external SW, should be obsolete soon - USHORT XTMDS_Info; // Will be obsolete from R600 - USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used - USHORT Object_Header; // Shared by various SW components,latest version 1.1 - USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! - USHORT MC_InitParameter; // Only used by command table - USHORT ASIC_VDDC_Info; // Will be obsolete from R600 - USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" - USHORT TV_VideoMode; // Only used by command table - USHORT VRAM_Info; // Only used by command table, latest version 1.3 - USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 - USHORT IntegratedSystemInfo; // Shared by various SW components - USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 - USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 - USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 -}ATOM_MASTER_LIST_OF_DATA_TABLES; - -#ifdef UEFI_BUILD - #define USHORT UTEMP -#endif - - -typedef struct _ATOM_MASTER_DATA_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; -}ATOM_MASTER_DATA_TABLE; - - -typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulSignature; // HW info table signature string "$ATI" - UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) - UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) - UCHAR ucVideoPortInfo; // Provides the video port capabilities - UCHAR ucHostPortInfo; // Provides host port configuration information -}ATOM_MULTIMEDIA_CAPABILITY_INFO; - - -typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulSignature; // MM info table signature sting "$MMT" - UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) - UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) - UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting - UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) - UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) - UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) - UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) - UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) - UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) -}ATOM_MULTIMEDIA_CONFIG_INFO; - -/****************************Firmware Info Table Definitions**********************/ - -// usBIOSCapability Defintion: -// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; -// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; -// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; -// Others: Reserved -#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 -#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 -#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 -#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 -#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 -#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 -#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 -#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 -#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 -#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 -#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 -#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 - - -#ifndef _H2INC - -//Please don't add or expand this bitfield structure below, this one will retire soon.! -typedef struct _ATOM_FIRMWARE_CAPABILITY -{ - USHORT FirmwarePosted:1; - USHORT DualCRTC_Support:1; - USHORT ExtendedDesktopSupport:1; - USHORT MemoryClockSS_Support:1; - USHORT EngineClockSS_Support:1; - USHORT GPUControlsBL:1; - USHORT WMI_SUPPORT:1; - USHORT PPMode_Assigned:1; - USHORT HyperMemory_Support:1; - USHORT HyperMemory_Size:4; - USHORT Reserved:3; -}ATOM_FIRMWARE_CAPABILITY; - -typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS -{ - ATOM_FIRMWARE_CAPABILITY sbfAccess; - USHORT susAccess; -}ATOM_FIRMWARE_CAPABILITY_ACCESS; - -#else - -typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS -{ - USHORT susAccess; -}ATOM_FIRMWARE_CAPABILITY_ACCESS; - -#endif - -typedef struct _ATOM_FIRMWARE_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucPadding[3]; //Don't use them - ULONG aulReservedForBIOS[3]; //Don't use them - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO; - -typedef struct _ATOM_FIRMWARE_INFO_V1_2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - UCHAR ucPadding[2]; //Don't use them - ULONG aulReservedForBIOS[2]; //Don't use them - ULONG ulMinPixelClockPLL_Output; //In 10Khz unit - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO_V1_2; - -typedef struct _ATOM_FIRMWARE_INFO_V1_3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - UCHAR ucPadding[2]; //Don't use them - ULONG aulReservedForBIOS; //Don't use them - ULONG ul3DAccelerationEngineClock;//In 10Khz unit - ULONG ulMinPixelClockPLL_Output; //In 10Khz unit - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO_V1_3; - -typedef struct _ATOM_FIRMWARE_INFO_V1_4 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulFirmwareRevision; - ULONG ulDefaultEngineClock; //In 10Khz unit - ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulDriverTargetEngineClock; //In 10Khz unit - ULONG ulDriverTargetMemoryClock; //In 10Khz unit - ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit - ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit - ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit - ULONG ulASICMaxEngineClock; //In 10Khz unit - ULONG ulASICMaxMemoryClock; //In 10Khz unit - UCHAR ucASICMaxTemperature; - UCHAR ucMinAllowedBL_Level; - USHORT usBootUpVDDCVoltage; //In MV unit - USHORT usLcdMinPixelClockPLL_Output; // In MHz unit - USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit - ULONG ul3DAccelerationEngineClock;//In 10Khz unit - ULONG ulMinPixelClockPLL_Output; //In 10Khz unit - USHORT usMinEngineClockPLL_Input; //In 10Khz unit - USHORT usMaxEngineClockPLL_Input; //In 10Khz unit - USHORT usMinEngineClockPLL_Output; //In 10Khz unit - USHORT usMinMemoryClockPLL_Input; //In 10Khz unit - USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit - USHORT usMinMemoryClockPLL_Output; //In 10Khz unit - USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk - USHORT usMinPixelClockPLL_Input; //In 10Khz unit - USHORT usMaxPixelClockPLL_Input; //In 10Khz unit - USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output - ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit - UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit - UCHAR ucDesign_ID; //Indicate what is the board design - UCHAR ucMemoryModule_ID; //Indicate what is the board design -}ATOM_FIRMWARE_INFO_V1_4; - -#define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4 - -#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 -#define IGP_CAP_FLAG_AC_CARD 0x4 -#define IGP_CAP_FLAG_SDVO_CARD 0x8 -#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 - -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulBootUpMemoryClock; //in 10kHz unit - ULONG ulMaxSystemMemoryClock; //in 10kHz unit - ULONG ulMinSystemMemoryClock; //in 10kHz unit - UCHAR ucNumberOfCyclesInPeriodHi; - UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. - USHORT usReserved1; - USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage - USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage - ULONG ulReserved[2]; - - USHORT usFSBClock; //In MHz unit - USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable - //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card - //Bit[4]==1: P/2 mode, ==0: P/1 mode - USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal - USHORT usK8MemoryClock; //in MHz unit - USHORT usK8SyncStartDelay; //in 0.01 us unit - USHORT usK8DataReturnTime; //in 0.01 us unit - UCHAR ucMaxNBVoltage; - UCHAR ucMinNBVoltage; - UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved - UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod - UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime - UCHAR ucHTLinkWidth; //16 bit vs. 8 bit - UCHAR ucMaxNBVoltageHigh; - UCHAR ucMinNBVoltageHigh; -}ATOM_INTEGRATED_SYSTEM_INFO; - -/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO -ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock - For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock -ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 - For AMD IGP,for now this can be 0 -ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 - For AMD IGP,for now this can be 0 - -usFSBClock: For Intel IGP,it's FSB Freq - For AMD IGP,it's HT Link Speed - -usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 -usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation -usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation - -VC:Voltage Control -ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. -ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. - -ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. -ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 - -ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. -ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. - - -usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. -usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. -*/ - - -/* -The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; -Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. -The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. - -SW components can access the IGP system infor structure in the same way as before -*/ - - -typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulReserved1[2]; //must be 0x0 for the reserved - ULONG ulBootUpUMAClock; //in 10kHz unit - ULONG ulBootUpSidePortClock; //in 10kHz unit - ULONG ulMinSidePortClock; //in 10kHz unit - ULONG ulReserved2[6]; //must be 0x0 for the reserved - ULONG ulSystemConfig; //see explanation below - ULONG ulBootUpReqDisplayVector; - ULONG ulOtherDisplayMisc; - ULONG ulDDISlot1Config; - ULONG ulDDISlot2Config; - UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved - UCHAR ucUMAChannelNumber; - UCHAR ucDockingPinBit; - UCHAR ucDockingPinPolarity; - ULONG ulDockingPinCFGInfo; - ULONG ulCPUCapInfo; - USHORT usNumberOfCyclesInPeriod; - USHORT usMaxNBVoltage; - USHORT usMinNBVoltage; - USHORT usBootUpNBVoltage; - ULONG ulHTLinkFreq; //in 10Khz - USHORT usMinHTLinkWidth; - USHORT usMaxHTLinkWidth; - USHORT usUMASyncStartDelay; - USHORT usUMADataReturnTime; - USHORT usLinkStatusZeroTime; - USHORT usReserved; - ULONG ulReserved3[101]; //must be 0x0 -}ATOM_INTEGRATED_SYSTEM_INFO_V2; - -/* -ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; -ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present -ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock - -ulSystemConfig: -Bit[0]: =1 PowerExpress mode =0 Non-PowerExpress mode; -Bit[1]=1: system is running at overdrived engine clock =0:system is not running at overdrived engine clock - -ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. - -ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; - [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; - -ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). - [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) - [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) - [15:8] - Lane configuration attribute; - [23:16]- Connector type, possible value: - CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D - CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D - CONNECTOR_OBJECT_ID_HDMI_TYPE_A - CONNECTOR_OBJECT_ID_DISPLAYPORT - [31:24]- Reserved - -ulDDISlot2Config: Same as Slot1. -ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. -For IGP, Hypermemory is the only memory type showed in CCC. - -ucUMAChannelNumber: how many channels for the UMA; - -ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin -ucDockingPinBit: which bit in this register to read the pin status; -ucDockingPinPolarity:Polarity of the pin when docked; - -ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 - -usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. -usMaxNBVoltage:Voltage regulator dependent PWM value.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. -usMinNBVoltage:Voltage regulator dependent PWM value.Set this one to 0x00 if VC without PWM or no VC at all. -usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. - - -ulHTLinkFreq: Current HT link Frequency in 10Khz. -usMinHTLinkWidth: -usMaxHTLinkWidth: -usUMASyncStartDelay: Memory access latency, required for watermark calculation -usUMADataReturnTime: Memory access latency, required for watermark calculation -usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us -for Griffin or Greyhound. SBIOS needs to convert to actual time by: - if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) - if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) - if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) - if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) -*/ - -#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 -#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 - -#define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF - -#define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F -#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 -#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 -#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 -#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 -#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 - -#define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 -#define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 -#define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 - -#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 - -#define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 -#define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 -#define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 -#define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 -#define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 -#define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 -#define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 -#define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 -#define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 -#define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 -#define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A -#define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B -#define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C -#define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D - -// define ASIC internal encoder id ( bit vector ) -#define ASIC_INT_DAC1_ENCODER_ID 0x00 -#define ASIC_INT_TV_ENCODER_ID 0x02 -#define ASIC_INT_DIG1_ENCODER_ID 0x03 -#define ASIC_INT_DAC2_ENCODER_ID 0x04 -#define ASIC_EXT_TV_ENCODER_ID 0x06 -#define ASIC_INT_DVO_ENCODER_ID 0x07 -#define ASIC_INT_DIG2_ENCODER_ID 0x09 -#define ASIC_EXT_DIG_ENCODER_ID 0x05 - -//define Encoder attribute -#define ATOM_ANALOG_ENCODER 0 -#define ATOM_DIGITAL_ENCODER 1 - -#define ATOM_DEVICE_CRT1_INDEX 0x00000000 -#define ATOM_DEVICE_LCD1_INDEX 0x00000001 -#define ATOM_DEVICE_TV1_INDEX 0x00000002 -#define ATOM_DEVICE_DFP1_INDEX 0x00000003 -#define ATOM_DEVICE_CRT2_INDEX 0x00000004 -#define ATOM_DEVICE_LCD2_INDEX 0x00000005 -#define ATOM_DEVICE_TV2_INDEX 0x00000006 -#define ATOM_DEVICE_DFP2_INDEX 0x00000007 -#define ATOM_DEVICE_CV_INDEX 0x00000008 -#define ATOM_DEVICE_DFP3_INDEX 0x00000009 -#define ATOM_DEVICE_RESERVEDA_INDEX 0x0000000A -#define ATOM_DEVICE_RESERVEDB_INDEX 0x0000000B -#define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C -#define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D -#define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E -#define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F -#define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_CV_INDEX+2) -#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO -#define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) - -#define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) -#define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) -#define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) -#define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX) -#define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) -#define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) -#define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX ) -#define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX) -#define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) -#define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) - -#define ATOM_DEVICE_CRT_SUPPORT ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT -#define ATOM_DEVICE_DFP_SUPPORT ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT -#define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT -#define ATOM_DEVICE_LCD_SUPPORT ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT - -#define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 -#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 -#define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 -#define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 -#define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 -#define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 -#define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 -#define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 -#define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 -#define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 -#define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 -#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A -#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B -#define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E -#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F - - -#define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F -#define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 -#define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 -#define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 -#define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 -#define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 - -#define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 - -#define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F -#define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 - -#define ATOM_DEVICE_I2C_ID_MASK 0x00000070 -#define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 -#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 -#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 -#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 -#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 - -#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 -#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 -#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 -#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 - -// usDeviceSupport: -// Bits0 = 0 - no CRT1 support= 1- CRT1 is supported -// Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported -// Bit 2 = 0 - no TV1 support= 1- TV1 is supported -// Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported -// Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported -// Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported -// Bit 6 = 0 - no TV2 support= 1- TV2 is supported -// Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported -// Bit 8 = 0 - no CV support= 1- CV is supported -// Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported -// Byte1 (Supported Device Info) -// Bit 0 = = 0 - no CV support= 1- CV is supported -// -// - -// ucI2C_ConfigID -// [7:0] - I2C LINE Associate ID -// = 0 - no I2C -// [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) -// = 0, [6:0]=SW assisted I2C ID -// [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use -// = 2, HW engine for Multimedia use -// = 3-7 Reserved for future I2C engines -// [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C - - -typedef struct _ATOM_I2C_ID_CONFIG -{ - UCHAR bfI2C_LineMux:4; - UCHAR bfHW_EngineID:3; - UCHAR bfHW_Capable:1; -}ATOM_I2C_ID_CONFIG; - -typedef union _ATOM_I2C_ID_CONFIG_ACCESS -{ - ATOM_I2C_ID_CONFIG sbfAccess; - UCHAR ucAccess; -}ATOM_I2C_ID_CONFIG_ACCESS; - - -typedef struct _ATOM_GPIO_I2C_ASSIGMENT -{ - USHORT usClkMaskRegisterIndex; - USHORT usClkEnRegisterIndex; - USHORT usClkY_RegisterIndex; - USHORT usClkA_RegisterIndex; - USHORT usDataMaskRegisterIndex; - USHORT usDataEnRegisterIndex; - USHORT usDataY_RegisterIndex; - USHORT usDataA_RegisterIndex; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; - UCHAR ucClkMaskShift; - UCHAR ucClkEnShift; - UCHAR ucClkY_Shift; - UCHAR ucClkA_Shift; - UCHAR ucDataMaskShift; - UCHAR ucDataEnShift; - UCHAR ucDataY_Shift; - UCHAR ucDataA_Shift; - UCHAR ucReserved1; - UCHAR ucReserved2; -}ATOM_GPIO_I2C_ASSIGMENT; - -typedef struct _ATOM_GPIO_I2C_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; -}ATOM_GPIO_I2C_INFO; - - -#ifndef _H2INC - -//Please don't add or expand this bitfield structure below, this one will retire soon.! -typedef struct _ATOM_MODE_MISC_INFO -{ - USHORT HorizontalCutOff:1; - USHORT HSyncPolarity:1; //0=Active High, 1=Active Low - USHORT VSyncPolarity:1; //0=Active High, 1=Active Low - USHORT VerticalCutOff:1; - USHORT H_ReplicationBy2:1; - USHORT V_ReplicationBy2:1; - USHORT CompositeSync:1; - USHORT Interlace:1; - USHORT DoubleClock:1; - USHORT RGB888:1; - USHORT Reserved:6; -}ATOM_MODE_MISC_INFO; - -typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ - ATOM_MODE_MISC_INFO sbfAccess; - USHORT usAccess; -}ATOM_MODE_MISC_INFO_ACCESS; - -#else - -typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ - USHORT usAccess; -}ATOM_MODE_MISC_INFO_ACCESS; - -#endif - -// usModeMiscInfo- -#define ATOM_H_CUTOFF 0x01 -#define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low -#define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low -#define ATOM_V_CUTOFF 0x08 -#define ATOM_H_REPLICATIONBY2 0x10 -#define ATOM_V_REPLICATIONBY2 0x20 -#define ATOM_COMPOSITESYNC 0x40 -#define ATOM_INTERLACE 0x80 -#define ATOM_DOUBLE_CLOCK_MODE 0x100 -#define ATOM_RGB888_MODE 0x200 - -//usRefreshRate- -#define ATOM_REFRESH_43 43 -#define ATOM_REFRESH_47 47 -#define ATOM_REFRESH_56 56 -#define ATOM_REFRESH_60 60 -#define ATOM_REFRESH_65 65 -#define ATOM_REFRESH_70 70 -#define ATOM_REFRESH_72 72 -#define ATOM_REFRESH_75 75 -#define ATOM_REFRESH_85 85 - -// ATOM_MODE_TIMING data are exactly the same as VESA timing data. -// Translation from EDID to ATOM_MODE_TIMING, use the following formula. -// -// VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK -// = EDID_HA + EDID_HBL -// VESA_HDISP = VESA_ACTIVE = EDID_HA -// VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH -// = EDID_HA + EDID_HSO -// VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW -// VESA_BORDER = EDID_BORDER - - -typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS -{ - USHORT usH_Size; - USHORT usH_Blanking_Time; - USHORT usV_Size; - USHORT usV_Blanking_Time; - USHORT usH_SyncOffset; - USHORT usH_SyncWidth; - USHORT usV_SyncOffset; - USHORT usV_SyncWidth; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucH_Border; // From DFP EDID - UCHAR ucV_Border; - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucPadding[3]; -}SET_CRTC_USING_DTD_TIMING_PARAMETERS; - -typedef struct _SET_CRTC_TIMING_PARAMETERS -{ - USHORT usH_Total; // horizontal total - USHORT usH_Disp; // horizontal display - USHORT usH_SyncStart; // horozontal Sync start - USHORT usH_SyncWidth; // horizontal Sync width - USHORT usV_Total; // vertical total - USHORT usV_Disp; // vertical display - USHORT usV_SyncStart; // vertical Sync start - USHORT usV_SyncWidth; // vertical Sync width - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucOverscanRight; // right - UCHAR ucOverscanLeft; // left - UCHAR ucOverscanBottom; // bottom - UCHAR ucOverscanTop; // top - UCHAR ucReserved; -}SET_CRTC_TIMING_PARAMETERS; -#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS - - -typedef struct _ATOM_MODE_TIMING -{ - USHORT usCRTC_H_Total; - USHORT usCRTC_H_Disp; - USHORT usCRTC_H_SyncStart; - USHORT usCRTC_H_SyncWidth; - USHORT usCRTC_V_Total; - USHORT usCRTC_V_Disp; - USHORT usCRTC_V_SyncStart; - USHORT usCRTC_V_SyncWidth; - USHORT usPixelClock; //in 10Khz unit - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - USHORT usCRTC_OverscanRight; - USHORT usCRTC_OverscanLeft; - USHORT usCRTC_OverscanBottom; - USHORT usCRTC_OverscanTop; - USHORT usReserve; - UCHAR ucInternalModeNumber; - UCHAR ucRefreshRate; -}ATOM_MODE_TIMING; - - -typedef struct _ATOM_DTD_FORMAT -{ - USHORT usPixClk; - USHORT usHActive; - USHORT usHBlanking_Time; - USHORT usVActive; - USHORT usVBlanking_Time; - USHORT usHSyncOffset; - USHORT usHSyncWidth; - USHORT usVSyncOffset; - USHORT usVSyncWidth; - USHORT usImageHSize; - USHORT usImageVSize; - UCHAR ucHBorder; - UCHAR ucVBorder; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; - UCHAR ucInternalModeNumber; - UCHAR ucRefreshRate; -}ATOM_DTD_FORMAT; - -#define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 -#define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 -#define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 -#define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 - -/****************************LVDS Info Table Definitions **********************/ -//ucTableFormatRevision=1 -//ucTableContentRevision=1 -typedef struct _ATOM_LVDS_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT sLCDTiming; - USHORT usModePatchTableOffset; - USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. - USHORT usOffDelayInMs; - UCHAR ucPowerSequenceDigOntoDEin10Ms; - UCHAR ucPowerSequenceDEtoBLOnin10Ms; - UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} - // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} - // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} - // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} - UCHAR ucPanelDefaultRefreshRate; - UCHAR ucPanelIdentification; - UCHAR ucSS_Id; -}ATOM_LVDS_INFO; - -//ucTableFormatRevision=1 -//ucTableContentRevision=2 -typedef struct _ATOM_LVDS_INFO_V12 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_DTD_FORMAT sLCDTiming; - USHORT usExtInfoTableOffset; - USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. - USHORT usOffDelayInMs; - UCHAR ucPowerSequenceDigOntoDEin10Ms; - UCHAR ucPowerSequenceDEtoBLOnin10Ms; - UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} - // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} - // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} - // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} - UCHAR ucPanelDefaultRefreshRate; - UCHAR ucPanelIdentification; - UCHAR ucSS_Id; - USHORT usLCDVenderID; - USHORT usLCDProductID; - UCHAR ucLCDPanel_SpecialHandlingCap; - UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable - UCHAR ucReserved[2]; -}ATOM_LVDS_INFO_V12; - -#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 - -typedef struct _ATOM_PATCH_RECORD_MODE -{ - UCHAR ucRecordType; - USHORT usHDisp; - USHORT usVDisp; -}ATOM_PATCH_RECORD_MODE; - -typedef struct _ATOM_LCD_RTS_RECORD -{ - UCHAR ucRecordType; - UCHAR ucRTSValue; -}ATOM_LCD_RTS_RECORD; - -//!! If the record below exits, it shoud always be the first record for easy use in command table!!! -typedef struct _ATOM_LCD_MODE_CONTROL_CAP -{ - UCHAR ucRecordType; - USHORT usLCDCap; -}ATOM_LCD_MODE_CONTROL_CAP; - -#define LCD_MODE_CAP_BL_OFF 1 -#define LCD_MODE_CAP_CRTC_OFF 2 -#define LCD_MODE_CAP_PANEL_OFF 4 - -typedef struct _ATOM_FAKE_EDID_PATCH_RECORD -{ - UCHAR ucRecordType; - UCHAR ucFakeEDIDLength; - UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. -} ATOM_FAKE_EDID_PATCH_RECORD; - -typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD -{ - UCHAR ucRecordType; - USHORT usHSize; - USHORT usVSize; -}ATOM_PANEL_RESOLUTION_PATCH_RECORD; - -#define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 -#define LCD_RTS_RECORD_TYPE 2 -#define LCD_CAP_RECORD_TYPE 3 -#define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 -#define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 -#define ATOM_RECORD_END_TYPE 0xFF - -/****************************Spread Spectrum Info Table Definitions **********************/ - -//ucTableFormatRevision=1 -//ucTableContentRevision=2 -typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT -{ - USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD - UCHAR ucSS_Step; - UCHAR ucSS_Delay; - UCHAR ucSS_Id; - UCHAR ucRecommandedRef_Div; - UCHAR ucSS_Range; //it was reserved for V11 -}ATOM_SPREAD_SPECTRUM_ASSIGNMENT; - -#define ATOM_MAX_SS_ENTRY 16 -#define ATOM_DP_SS_ID1 0x0f1 // SS modulation freq=30k -#define ATOM_DP_SS_ID2 0x0f2 // SS modulation freq=33k - - -#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 -#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 -#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 -#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 -#define ATOM_INTERNAL_SS_MASK 0x00000000 -#define ATOM_EXTERNAL_SS_MASK 0x00000002 -#define EXEC_SS_STEP_SIZE_SHIFT 2 -#define EXEC_SS_DELAY_SHIFT 4 -#define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 - -typedef struct _ATOM_SPREAD_SPECTRUM_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; -}ATOM_SPREAD_SPECTRUM_INFO; - - - - -//ucTVBootUpDefaultStd definiton: - -//ATOM_TV_NTSC 1 -//ATOM_TV_NTSCJ 2 -//ATOM_TV_PAL 3 -//ATOM_TV_PALM 4 -//ATOM_TV_PALCN 5 -//ATOM_TV_PALN 6 -//ATOM_TV_PAL60 7 -//ATOM_TV_SECAM 8 - - -//ucTVSuppportedStd definition: -#define NTSC_SUPPORT 0x1 -#define NTSCJ_SUPPORT 0x2 - -#define PAL_SUPPORT 0x4 -#define PALM_SUPPORT 0x8 -#define PALCN_SUPPORT 0x10 -#define PALN_SUPPORT 0x20 -#define PAL60_SUPPORT 0x40 -#define SECAM_SUPPORT 0x80 - -#define MAX_SUPPORTED_TV_TIMING 2 - -typedef struct _ATOM_ANALOG_TV_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; - UCHAR ucExt_TV_ASIC_ID; - UCHAR ucExt_TV_ASIC_SlaveAddr; - /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ - ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; -}ATOM_ANALOG_TV_INFO; - - -/**************************************************************************/ -// VRAM usage and their defintions - -// One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. -// Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. -// All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! -// To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR -// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX - -#ifndef VESA_MEMORY_IN_64K_BLOCK -#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) -#endif - -#define ATOM_EDID_RAW_DATASIZE 256 //In Bytes -#define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes -#define ATOM_HWICON_INFOTABLE_SIZE 32 -#define MAX_DTD_MODE_IN_VRAM 6 -#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) -#define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) -#define DFP_ENCODER_TYPE_OFFSET 0x80 -#define DP_ENCODER_LANE_NUM_OFFSET 0x84 -#define DP_ENCODER_LINK_RATE_OFFSET 0x88 - -#define ATOM_HWICON1_SURFACE_ADDR 0 -#define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) -#define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) -#define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) -#define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) -#define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) - -#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) -#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 - -//The size below is in Kb! -#define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) - -#define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L -#define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 -#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 -#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 - -#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 - -typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO -{ - ULONG ulStartAddrUsedByFirmware; - USHORT usFirmwareUseInKb; - USHORT usReserved; -}ATOM_FIRMWARE_VRAM_RESERVE_INFO; - -typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; -}ATOM_VRAM_USAGE_BY_FIRMWARE; - -/**************************************************************************/ -//GPIO Pin lut table definition -typedef struct _ATOM_GPIO_PIN_ASSIGNMENT -{ - USHORT usGpioPin_AIndex; - UCHAR ucGpioPinBitShift; - UCHAR ucGPIO_ID; -}ATOM_GPIO_PIN_ASSIGNMENT; - -typedef struct _ATOM_GPIO_PIN_LUT -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; -}ATOM_GPIO_PIN_LUT; - -/**************************************************************************/ - - -#define GPIO_PIN_ACTIVE_HIGH 0x1 - -#define MAX_SUPPORTED_CV_STANDARDS 5 - -// definitions for ATOM_D_INFO.ucSettings -#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] -#define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out -#define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] - -typedef struct _ATOM_GPIO_INFO -{ - USHORT usAOffset; - UCHAR ucSettings; - UCHAR ucReserved; -}ATOM_GPIO_INFO; - -// definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) -#define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 - -// definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i -#define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; -#define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] - -// definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode -//Line 3 out put 5V. -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 - -//Line 3 out put 2.2V -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 - -//Line 3 out put 0V -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 - -#define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] - -#define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 - -//GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. -#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. - - -typedef struct _ATOM_COMPONENT_VIDEO_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMask_PinRegisterIndex; - USHORT usEN_PinRegisterIndex; - USHORT usY_PinRegisterIndex; - USHORT usA_PinRegisterIndex; - UCHAR ucBitShift; - UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low - ATOM_DTD_FORMAT sReserved; // must be zeroed out - UCHAR ucMiscInfo; - UCHAR uc480i; - UCHAR uc480p; - UCHAR uc720p; - UCHAR uc1080i; - UCHAR ucLetterBoxMode; - UCHAR ucReserved[3]; - UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector - ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; -}ATOM_COMPONENT_VIDEO_INFO; - -//ucTableFormatRevision=2 -//ucTableContentRevision=1 -typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucMiscInfo; - UCHAR uc480i; - UCHAR uc480p; - UCHAR uc720p; - UCHAR uc1080i; - UCHAR ucReserved; - UCHAR ucLetterBoxMode; - UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector - ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; - ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; -}ATOM_COMPONENT_VIDEO_INFO_V21; - -#define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 - -/**************************************************************************/ -//Object table starts here -typedef struct _ATOM_OBJECT_HEADER -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - USHORT usConnectorObjectTableOffset; - USHORT usRouterObjectTableOffset; - USHORT usEncoderObjectTableOffset; - USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. - USHORT usDisplayPathTableOffset; -}ATOM_OBJECT_HEADER; - - -typedef struct _ATOM_DISPLAY_OBJECT_PATH -{ - USHORT usDeviceTag; //supported device - USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH - USHORT usConnObjectId; //Connector Object ID - USHORT usGPUObjectId; //GPU ID - USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. -}ATOM_DISPLAY_OBJECT_PATH; - -typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE -{ - UCHAR ucNumOfDispPath; - UCHAR ucVersion; - UCHAR ucPadding[2]; - ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; -}ATOM_DISPLAY_OBJECT_PATH_TABLE; - - -typedef struct _ATOM_OBJECT //each object has this structure -{ - USHORT usObjectID; - USHORT usSrcDstTableOffset; - USHORT usRecordOffset; //this pointing to a bunch of records defined below - USHORT usReserved; -}ATOM_OBJECT; - -typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure -{ - UCHAR ucNumberOfObjects; - UCHAR ucPadding[3]; - ATOM_OBJECT asObjects[1]; -}ATOM_OBJECT_TABLE; - -typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure -{ - UCHAR ucNumberOfSrc; - USHORT usSrcObjectID[1]; - UCHAR ucNumberOfDst; - USHORT usDstObjectID[1]; -}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; - - -//Related definitions, all records are differnt but they have a commond header -typedef struct _ATOM_COMMON_RECORD_HEADER -{ - UCHAR ucRecordType; //An emun to indicate the record type - UCHAR ucRecordSize; //The size of the whole record in byte -}ATOM_COMMON_RECORD_HEADER; - - -#define ATOM_I2C_RECORD_TYPE 1 -#define ATOM_HPD_INT_RECORD_TYPE 2 -#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 -#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 -#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE -#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE -#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 -#define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE -#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 -#define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 -#define ATOM_CONNECTOR_CF_RECORD_TYPE 11 -#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 -#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 -#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 -#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 - -//Must be updated when new record type is added,equal to that record definition! -#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE - -typedef struct _ATOM_I2C_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - ATOM_I2C_ID_CONFIG sucI2cId; - UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC -}ATOM_I2C_RECORD; - -typedef struct _ATOM_HPD_INT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info - UCHAR ucPluggged_PinState; -}ATOM_HPD_INT_RECORD; - - -typedef struct _ATOM_OUTPUT_PROTECTION_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucProtectionFlag; - UCHAR ucReserved; -}ATOM_OUTPUT_PROTECTION_RECORD; - -typedef struct _ATOM_CONNECTOR_DEVICE_TAG -{ - ULONG ulACPIDeviceEnum; //Reserved for now - USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" - USHORT usPadding; -}ATOM_CONNECTOR_DEVICE_TAG; - -typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucNumberOfDevice; - UCHAR ucReserved; - ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation -}ATOM_CONNECTOR_DEVICE_TAG_RECORD; - - -typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucConfigGPIOID; - UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in - UCHAR ucFlowinGPIPID; - UCHAR ucExtInGPIPID; -}ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; - -typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucCTL1GPIO_ID; - UCHAR ucCTL1GPIOState; //Set to 1 when it's active high - UCHAR ucCTL2GPIO_ID; - UCHAR ucCTL2GPIOState; //Set to 1 when it's active high - UCHAR ucCTL3GPIO_ID; - UCHAR ucCTL3GPIOState; //Set to 1 when it's active high - UCHAR ucCTLFPGA_IN_ID; - UCHAR ucPadding[3]; -}ATOM_ENCODER_FPGA_CONTROL_RECORD; - -typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info - UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected -}ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; - -typedef struct _ATOM_JTAG_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucTMSGPIO_ID; - UCHAR ucTMSGPIOState; //Set to 1 when it's active high - UCHAR ucTCKGPIO_ID; - UCHAR ucTCKGPIOState; //Set to 1 when it's active high - UCHAR ucTDOGPIO_ID; - UCHAR ucTDOGPIOState; //Set to 1 when it's active high - UCHAR ucTDIGPIO_ID; - UCHAR ucTDIGPIOState; //Set to 1 when it's active high - UCHAR ucPadding[2]; -}ATOM_JTAG_RECORD; - - -//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually -typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR -{ - UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table - UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin -}ATOM_GPIO_PIN_CONTROL_PAIR; - -typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucFlags; // Future expnadibility - UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object - ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins -}ATOM_OBJECT_GPIO_CNTL_RECORD; - -//Definitions for GPIO pin state -#define GPIO_PIN_TYPE_INPUT 0x00 -#define GPIO_PIN_TYPE_OUTPUT 0x10 -#define GPIO_PIN_TYPE_HW_CONTROL 0x20 - -//For GPIO_PIN_TYPE_OUTPUT the following is defined -#define GPIO_PIN_OUTPUT_STATE_MASK 0x01 -#define GPIO_PIN_OUTPUT_STATE_SHIFT 0 -#define GPIO_PIN_STATE_ACTIVE_LOW 0x0 -#define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 - -typedef struct _ATOM_ENCODER_DVO_CF_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - ULONG ulStrengthControl; // DVOA strength control for CF - UCHAR ucPadding[2]; -}ATOM_ENCODER_DVO_CF_RECORD; - -// value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle -#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 -#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 - -typedef struct _ATOM_CONNECTOR_CF_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - USHORT usMaxPixClk; - UCHAR ucFlowCntlGpioId; - UCHAR ucSwapCntlGpioId; - UCHAR ucConnectedDvoBundle; - UCHAR ucPadding; -}ATOM_CONNECTOR_CF_RECORD; - -typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - ATOM_DTD_FORMAT asTiming; -}ATOM_CONNECTOR_HARDCODE_DTD_RECORD; - -typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE - UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A - UCHAR ucReserved; -}ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; - - -typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state - UCHAR ucMuxControlPin; - UCHAR ucMuxState[2]; //for alligment purpose -}ATOM_ROUTER_DDC_PATH_SELECT_RECORD; - -typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD -{ - ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucMuxType; - UCHAR ucMuxControlPin; - UCHAR ucMuxState[2]; //for alligment purpose -}ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; - -// define ucMuxType -#define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f -#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 - -/**************************************************************************/ -//ASIC voltage data table starts here - -typedef struct _ATOM_VOLTAGE_INFO_HEADER -{ - USHORT usVDDCBaseLevel; //In number of 50mv unit - USHORT usReserved; //For possible extension table offset - UCHAR ucNumOfVoltageEntries; - UCHAR ucBytesPerVoltageEntry; - UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit - UCHAR ucDefaultVoltageEntry; - UCHAR ucVoltageControlI2cLine; - UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; -}ATOM_VOLTAGE_INFO_HEADER; - -typedef struct _ATOM_VOLTAGE_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_INFO_HEADER viHeader; - UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry -}ATOM_VOLTAGE_INFO; - - -typedef struct _ATOM_VOLTAGE_FORMULA -{ - USHORT usVoltageBaseLevel; // In number of 1mv unit - USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit - UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage - UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv - UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep - UCHAR ucReserved; - UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries -}ATOM_VOLTAGE_FORMULA; - -typedef struct _ATOM_VOLTAGE_CONTROL -{ - UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine - UCHAR ucVoltageControlI2cLine; - UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; - USHORT usGpioPin_AIndex; //GPIO_PAD register index - UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff - UCHAR ucReserved; -}ATOM_VOLTAGE_CONTROL; - -// Define ucVoltageControlId -#define VOLTAGE_CONTROLLED_BY_HW 0x00 -#define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F -#define VOLTAGE_CONTROLLED_BY_GPIO 0x80 -#define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage -#define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI -#define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage -#define VOLTAGE_CONTROL_ID_DS4402 0x04 - -typedef struct _ATOM_VOLTAGE_OBJECT -{ - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucSize; //Size of Object - ATOM_VOLTAGE_CONTROL asControl; //describ how to control - ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID -}ATOM_VOLTAGE_OBJECT; - -typedef struct _ATOM_VOLTAGE_OBJECT_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control -}ATOM_VOLTAGE_OBJECT_INFO; - -typedef struct _ATOM_LEAKID_VOLTAGE -{ - UCHAR ucLeakageId; - UCHAR ucReserved; - USHORT usVoltage; -}ATOM_LEAKID_VOLTAGE; - -typedef struct _ATOM_ASIC_PROFILE_VOLTAGE -{ - UCHAR ucProfileId; - UCHAR ucReserved; - USHORT usSize; - USHORT usEfuseSpareStartAddr; - USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, - ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage -}ATOM_ASIC_PROFILE_VOLTAGE; - -//ucProfileId -#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 -#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 -#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 - -typedef struct _ATOM_ASIC_PROFILING_INFO -{ - ATOM_COMMON_TABLE_HEADER asHeader; - ATOM_ASIC_PROFILE_VOLTAGE asVoltage; -}ATOM_ASIC_PROFILING_INFO; - -typedef struct _ATOM_POWER_SOURCE_OBJECT -{ - UCHAR ucPwrSrcId; // Power source - UCHAR ucPwrSensorType; // GPIO, I2C or none - UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id - UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect - UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect - UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect - UCHAR ucPwrSensActiveState; // high active or low active - UCHAR ucReserve[3]; // reserve - USHORT usSensPwr; // in unit of watt -}ATOM_POWER_SOURCE_OBJECT; - -typedef struct _ATOM_POWER_SOURCE_INFO -{ - ATOM_COMMON_TABLE_HEADER asHeader; - UCHAR asPwrbehave[16]; - ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; -}ATOM_POWER_SOURCE_INFO; - - -//Define ucPwrSrcId -#define POWERSOURCE_PCIE_ID1 0x00 -#define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 -#define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 -#define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 -#define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 - -//define ucPwrSensorId -#define POWER_SENSOR_ALWAYS 0x00 -#define POWER_SENSOR_GPIO 0x01 -#define POWER_SENSOR_I2C 0x02 - -/**************************************************************************/ -// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design -//Memory SS Info Table -//Define Memory Clock SS chip ID -#define ICS91719 1 -#define ICS91720 2 - -//Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol -typedef struct _ATOM_I2C_DATA_RECORD -{ - UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" - UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually -}ATOM_I2C_DATA_RECORD; - - -//Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information -typedef struct _ATOM_I2C_DEVICE_SETUP_INFO -{ - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. - UCHAR ucSSChipID; //SS chip being used - UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip - UCHAR ucNumOfI2CDataRecords; //number of data block - ATOM_I2C_DATA_RECORD asI2CData[1]; -}ATOM_I2C_DEVICE_SETUP_INFO; - -//========================================================================================== -typedef struct _ATOM_ASIC_MVDD_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; -}ATOM_ASIC_MVDD_INFO; - -//========================================================================================== -#define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO - -//========================================================================================== -/**************************************************************************/ - -typedef struct _ATOM_ASIC_SS_ASSIGNMENT -{ - ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz - USHORT usSpreadSpectrumPercentage; //in unit of 0.01% - USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq - UCHAR ucClockIndication; //Indicate which clock source needs SS - UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. - UCHAR ucReserved[2]; -}ATOM_ASIC_SS_ASSIGNMENT; - -//Define ucSpreadSpectrumType -#define ASIC_INTERNAL_MEMORY_SS 1 -#define ASIC_INTERNAL_ENGINE_SS 2 -#define ASIC_INTERNAL_UVD_SS 3 - -typedef struct _ATOM_ASIC_INTERNAL_SS_INFO{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; -}ATOM_ASIC_INTERNAL_SS_INFO; - -//==============================Scratch Pad Definition Portion=============================== -#define ATOM_DEVICE_CONNECT_INFO_DEF 0 -#define ATOM_ROM_LOCATION_DEF 1 -#define ATOM_TV_STANDARD_DEF 2 -#define ATOM_ACTIVE_INFO_DEF 3 -#define ATOM_LCD_INFO_DEF 4 -#define ATOM_DOS_REQ_INFO_DEF 5 -#define ATOM_ACC_CHANGE_INFO_DEF 6 -#define ATOM_DOS_MODE_INFO_DEF 7 -#define ATOM_I2C_CHANNEL_STATUS_DEF 8 -#define ATOM_I2C_CHANNEL_STATUS1_DEF 9 - - -// BIOS_0_SCRATCH Definition -#define ATOM_S0_CRT1_MONO 0x00000001L -#define ATOM_S0_CRT1_COLOR 0x00000002L -#define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) - -#define ATOM_S0_TV1_COMPOSITE_A 0x00000004L -#define ATOM_S0_TV1_SVIDEO_A 0x00000008L -#define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) - -#define ATOM_S0_CV_A 0x00000010L -#define ATOM_S0_CV_DIN_A 0x00000020L -#define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) - - -#define ATOM_S0_CRT2_MONO 0x00000100L -#define ATOM_S0_CRT2_COLOR 0x00000200L -#define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) - -#define ATOM_S0_TV1_COMPOSITE 0x00000400L -#define ATOM_S0_TV1_SVIDEO 0x00000800L -#define ATOM_S0_TV1_SCART 0x00004000L -#define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) - -#define ATOM_S0_CV 0x00001000L -#define ATOM_S0_CV_DIN 0x00002000L -#define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) - - -#define ATOM_S0_DFP1 0x00010000L -#define ATOM_S0_DFP2 0x00020000L -#define ATOM_S0_LCD1 0x00040000L -#define ATOM_S0_LCD2 0x00080000L -#define ATOM_S0_TV2 0x00100000L -#define ATOM_S0_DFP3 0x00200000L - -#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with - // the FAD/HDP reg access bug. Bit is read by DAL - -#define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L -#define ATOM_S0_THERMAL_STATE_SHIFT 26 - -#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L -#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 - -#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 -#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 -#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 - -//Byte aligned defintion for BIOS usage -#define ATOM_S0_CRT1_MONOb0 0x01 -#define ATOM_S0_CRT1_COLORb0 0x02 -#define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) - -#define ATOM_S0_TV1_COMPOSITEb0 0x04 -#define ATOM_S0_TV1_SVIDEOb0 0x08 -#define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) - -#define ATOM_S0_CVb0 0x10 -#define ATOM_S0_CV_DINb0 0x20 -#define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) - -#define ATOM_S0_CRT2_MONOb1 0x01 -#define ATOM_S0_CRT2_COLORb1 0x02 -#define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) - -#define ATOM_S0_TV1_COMPOSITEb1 0x04 -#define ATOM_S0_TV1_SVIDEOb1 0x08 -#define ATOM_S0_TV1_SCARTb1 0x40 -#define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) - -#define ATOM_S0_CVb1 0x10 -#define ATOM_S0_CV_DINb1 0x20 -#define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) - -#define ATOM_S0_DFP1b2 0x01 -#define ATOM_S0_DFP2b2 0x02 -#define ATOM_S0_LCD1b2 0x04 -#define ATOM_S0_LCD2b2 0x08 -#define ATOM_S0_TV2b2 0x10 -#define ATOM_S0_DFP3b2 0x20 - -#define ATOM_S0_THERMAL_STATE_MASKb3 0x1C -#define ATOM_S0_THERMAL_STATE_SHIFTb3 2 - -#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 -#define ATOM_S0_LCD1_SHIFT 18 - -// BIOS_1_SCRATCH Definition -#define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL -#define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L - - -// BIOS_2_SCRATCH Definition -#define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL -#define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L -#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 - -#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L -#define ATOM_S2_LCD1_DPMS_STATE 0x00020000L -#define ATOM_S2_TV1_DPMS_STATE 0x00040000L -#define ATOM_S2_DFP1_DPMS_STATE 0x00080000L -#define ATOM_S2_CRT2_DPMS_STATE 0x00100000L -#define ATOM_S2_LCD2_DPMS_STATE 0x00200000L -#define ATOM_S2_TV2_DPMS_STATE 0x00400000L -#define ATOM_S2_DFP2_DPMS_STATE 0x00800000L -#define ATOM_S2_CV_DPMS_STATE 0x01000000L -#define ATOM_S2_DFP3_DPMS_STATE 0x02000000L - -#define ATOM_S2_DEVICE_DPMS_STATE (ATOM_S2_CRT1_DPMS_STATE+ATOM_S2_LCD1_DPMS_STATE+ATOM_S2_TV1_DPMS_STATE+\ - ATOM_S2_DFP1I_DPMS_STATE+ATOM_S2_CRT2_DPMS_STATE+ATOM_S2_LCD2_DPMS_STATE+\ - ATOM_S2_TV2_DPMS_STATE+ATOM_S2_DFP1X_DPMS_STATE+ATOM_S2_CV_DPMS_STATE+\ - ATOM_S2_DFP3_DPMS_STATE) - - -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L - -#define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L - -#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 -#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 -#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 -#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 -#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 -#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L - - -//Byte aligned defintion for BIOS usage -#define ATOM_S2_TV1_STANDARD_MASKb0 0x0F -#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF -#define ATOM_S2_CRT1_DPMS_STATEb2 0x01 -#define ATOM_S2_LCD1_DPMS_STATEb2 0x02 -#define ATOM_S2_TV1_DPMS_STATEb2 0x04 -#define ATOM_S2_DFP1_DPMS_STATEb2 0x08 -#define ATOM_S2_CRT2_DPMS_STATEb2 0x10 -#define ATOM_S2_LCD2_DPMS_STATEb2 0x20 -#define ATOM_S2_TV2_DPMS_STATEb2 0x40 -#define ATOM_S2_DFP2_DPMS_STATEb2 0x80 -#define ATOM_S2_CV_DPMS_STATEb3 0x01 -#define ATOM_S2_DFP3_DPMS_STATEb3 0x02 - -#define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C -#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 -#define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 -#define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 - - -// BIOS_3_SCRATCH Definition -#define ATOM_S3_CRT1_ACTIVE 0x00000001L -#define ATOM_S3_LCD1_ACTIVE 0x00000002L -#define ATOM_S3_TV1_ACTIVE 0x00000004L -#define ATOM_S3_DFP1_ACTIVE 0x00000008L -#define ATOM_S3_CRT2_ACTIVE 0x00000010L -#define ATOM_S3_LCD2_ACTIVE 0x00000020L -#define ATOM_S3_TV2_ACTIVE 0x00000040L -#define ATOM_S3_DFP2_ACTIVE 0x00000080L -#define ATOM_S3_CV_ACTIVE 0x00000100L -#define ATOM_S3_DFP3_ACTIVE 0x00000200L - -#define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL - -#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L -#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L - -#define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L -#define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L -#define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L -#define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L -#define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L -#define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L -#define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L -#define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L -#define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L -#define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L - -#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x03FF0000L -#define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L -#define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L -#define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L - -//Byte aligned defintion for BIOS usage -#define ATOM_S3_CRT1_ACTIVEb0 0x01 -#define ATOM_S3_LCD1_ACTIVEb0 0x02 -#define ATOM_S3_TV1_ACTIVEb0 0x04 -#define ATOM_S3_DFP1_ACTIVEb0 0x08 -#define ATOM_S3_CRT2_ACTIVEb0 0x10 -#define ATOM_S3_LCD2_ACTIVEb0 0x20 -#define ATOM_S3_TV2_ACTIVEb0 0x40 -#define ATOM_S3_DFP2_ACTIVEb0 0x80 -#define ATOM_S3_CV_ACTIVEb1 0x01 -#define ATOM_S3_DFP3_ACTIVEb1 0x02 - -#define ATOM_S3_ACTIVE_CRTC1w0 0x3FF - -#define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 -#define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 -#define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 -#define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 -#define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 -#define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 -#define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40 -#define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 -#define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 -#define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 - -#define ATOM_S3_ACTIVE_CRTC2w1 0x3FF - -#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 -#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 -#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 - -// BIOS_4_SCRATCH Definition -#define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL -#define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L -#define ATOM_S4_LCD1_REFRESH_SHIFT 8 - - -//Byte aligned defintion for BIOS usage -#define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF -#define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 -#define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 - - -// BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! -#define ATOM_S5_DOS_REQ_CRT1b0 0x01 -#define ATOM_S5_DOS_REQ_LCD1b0 0x02 -#define ATOM_S5_DOS_REQ_TV1b0 0x04 -#define ATOM_S5_DOS_REQ_DFP1b0 0x08 -#define ATOM_S5_DOS_REQ_CRT2b0 0x10 -#define ATOM_S5_DOS_REQ_LCD2b0 0x20 -#define ATOM_S5_DOS_REQ_TV2b0 0x40 -#define ATOM_S5_DOS_REQ_DFP2b0 0x80 -#define ATOM_S5_DOS_REQ_CVb1 0x01 -#define ATOM_S5_DOS_REQ_DFP3b1 0x02 - -#define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF - -#define ATOM_S5_DOS_REQ_CRT1 0x0001 -#define ATOM_S5_DOS_REQ_LCD1 0x0002 -#define ATOM_S5_DOS_REQ_TV1 0x0004 -#define ATOM_S5_DOS_REQ_DFP1 0x0008 -#define ATOM_S5_DOS_REQ_CRT2 0x0010 -#define ATOM_S5_DOS_REQ_LCD2 0x0020 -#define ATOM_S5_DOS_REQ_TV2 0x0040 -#define ATOM_S5_DOS_REQ_DFP2 0x0080 -#define ATOM_S5_DOS_REQ_CV 0x0100 -#define ATOM_S5_DOS_REQ_DFP3 0x0200 - -#define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 -#define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 -#define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 -#define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 -#define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ - (ATOM_S5_DOS_FORCE_CVb3<<8)) - -// BIOS_6_SCRATCH Definition -#define ATOM_S6_DEVICE_CHANGE 0x00000001L -#define ATOM_S6_SCALER_CHANGE 0x00000002L -#define ATOM_S6_LID_CHANGE 0x00000004L -#define ATOM_S6_DOCKING_CHANGE 0x00000008L -#define ATOM_S6_ACC_MODE 0x00000010L -#define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L -#define ATOM_S6_LID_STATE 0x00000040L -#define ATOM_S6_DOCK_STATE 0x00000080L -#define ATOM_S6_CRITICAL_STATE 0x00000100L -#define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L -#define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L -#define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L -#define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD - -#define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion -#define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion - - -#define ATOM_S6_ACC_REQ_CRT1 0x00010000L -#define ATOM_S6_ACC_REQ_LCD1 0x00020000L -#define ATOM_S6_ACC_REQ_TV1 0x00040000L -#define ATOM_S6_ACC_REQ_DFP1 0x00080000L -#define ATOM_S6_ACC_REQ_CRT2 0x00100000L -#define ATOM_S6_ACC_REQ_LCD2 0x00200000L -#define ATOM_S6_ACC_REQ_TV2 0x00400000L -#define ATOM_S6_ACC_REQ_DFP2 0x00800000L -#define ATOM_S6_ACC_REQ_CV 0x01000000L -#define ATOM_S6_ACC_REQ_DFP3 0x02000000L - -#define ATOM_S6_ACC_REQ_MASK 0x03FF0000L -#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L -#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L -#define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L -#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L - -//Byte aligned defintion for BIOS usage -#define ATOM_S6_DEVICE_CHANGEb0 0x01 -#define ATOM_S6_SCALER_CHANGEb0 0x02 -#define ATOM_S6_LID_CHANGEb0 0x04 -#define ATOM_S6_DOCKING_CHANGEb0 0x08 -#define ATOM_S6_ACC_MODEb0 0x10 -#define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 -#define ATOM_S6_LID_STATEb0 0x40 -#define ATOM_S6_DOCK_STATEb0 0x80 -#define ATOM_S6_CRITICAL_STATEb1 0x01 -#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 -#define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 -#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 -#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 - -#define ATOM_S6_ACC_REQ_CRT1b2 0x01 -#define ATOM_S6_ACC_REQ_LCD1b2 0x02 -#define ATOM_S6_ACC_REQ_TV1b2 0x04 -#define ATOM_S6_ACC_REQ_DFP1b2 0x08 -#define ATOM_S6_ACC_REQ_CRT2b2 0x10 -#define ATOM_S6_ACC_REQ_LCD2b2 0x20 -#define ATOM_S6_ACC_REQ_TV2b2 0x40 -#define ATOM_S6_ACC_REQ_DFP2b2 0x80 -#define ATOM_S6_ACC_REQ_CVb3 0x01 -#define ATOM_S6_ACC_REQ_DFP3b3 0x02 - -#define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 -#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 -#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 -#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 -#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 - -#define ATOM_S6_DEVICE_CHANGE_SHIFT 0 -#define ATOM_S6_SCALER_CHANGE_SHIFT 1 -#define ATOM_S6_LID_CHANGE_SHIFT 2 -#define ATOM_S6_DOCKING_CHANGE_SHIFT 3 -#define ATOM_S6_ACC_MODE_SHIFT 4 -#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 -#define ATOM_S6_LID_STATE_SHIFT 6 -#define ATOM_S6_DOCK_STATE_SHIFT 7 -#define ATOM_S6_CRITICAL_STATE_SHIFT 8 -#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 -#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 -#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 -#define ATOM_S6_REQ_SCALER_SHIFT 12 -#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 -#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 -#define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 -#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 -#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 -#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 -#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 - -// BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! -#define ATOM_S7_DOS_MODE_TYPEb0 0x03 -#define ATOM_S7_DOS_MODE_VGAb0 0x00 -#define ATOM_S7_DOS_MODE_VESAb0 0x01 -#define ATOM_S7_DOS_MODE_EXTb0 0x02 -#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C -#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 -#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 -#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF - -#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 - -// BIOS_8_SCRATCH Definition -#define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF -#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 - -#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 -#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 - -// BIOS_9_SCRATCH Definition -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK -#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF -#endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK -#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 -#endif -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT -#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 -#endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT -#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 -#endif - - -#define ATOM_FLAG_SET 0x20 -#define ATOM_FLAG_CLEAR 0 -#define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) -#define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) - -#define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) -#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) - -#define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) - -#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) - -#define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) -#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) - -#define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) - -#define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) - -#define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) -#define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) -#define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) -#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) - -/****************************************************************************/ -//Portion II: Definitinos only used in Driver -/****************************************************************************/ - -// Macros used by driver - -#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) - -#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) -#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) - -#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION -#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION - -/****************************************************************************/ -//Portion III: Definitinos only used in VBIOS -/****************************************************************************/ -#define ATOM_DAC_SRC 0x80 -#define ATOM_SRC_DAC1 0 -#define ATOM_SRC_DAC2 0x80 - - -#ifdef UEFI_BUILD - #define USHORT UTEMP -#endif - -typedef struct _MEMORY_PLLINIT_PARAMETERS -{ - ULONG ulTargetMemoryClock; //In 10Khz unit - UCHAR ucAction; //not define yet - UCHAR ucFbDiv_Hi; //Fbdiv Hi byte - UCHAR ucFbDiv; //FB value - UCHAR ucPostDiv; //Post div -}MEMORY_PLLINIT_PARAMETERS; - -#define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS - - -#define GPIO_PIN_WRITE 0x01 -#define GPIO_PIN_READ 0x00 - -typedef struct _GPIO_PIN_CONTROL_PARAMETERS -{ - UCHAR ucGPIO_ID; //return value, read from GPIO pins - UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update - UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask - UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write -}GPIO_PIN_CONTROL_PARAMETERS; - -typedef struct _ENABLE_SCALER_PARAMETERS -{ - UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 - UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION - UCHAR ucTVStandard; // - UCHAR ucPadding[1]; -}ENABLE_SCALER_PARAMETERS; -#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS - -//ucEnable: -#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 -#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 -#define SCALER_ENABLE_2TAP_ALPHA_MODE 2 -#define SCALER_ENABLE_MULTITAP_MODE 3 - -typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS -{ - ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position - UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset - UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset - UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE -}ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; - -typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION -{ - ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; - ENABLE_CRTC_PARAMETERS sReserved; -}ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; - -typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS -{ - USHORT usHight; // Image Hight - USHORT usWidth; // Image Width - UCHAR ucSurface; // Surface 1 or 2 - UCHAR ucPadding[3]; -}ENABLE_GRAPH_SURFACE_PARAMETERS; - -typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 -{ - USHORT usHight; // Image Hight - USHORT usWidth; // Image Width - UCHAR ucSurface; // Surface 1 or 2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - UCHAR ucPadding[2]; -}ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; - -typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION -{ - ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; - ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one -}ENABLE_GRAPH_SURFACE_PS_ALLOCATION; - -typedef struct _MEMORY_CLEAN_UP_PARAMETERS -{ - USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address - USHORT usMemorySize; //8Kb blocks aligned -}MEMORY_CLEAN_UP_PARAMETERS; -#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS - -typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS -{ - USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC - USHORT usY_Size; -}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; - -typedef struct _INDIRECT_IO_ACCESS -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR IOAccessSequence[256]; -} INDIRECT_IO_ACCESS; - -#define INDIRECT_READ 0x00 -#define INDIRECT_WRITE 0x80 - -#define INDIRECT_IO_MM 0 -#define INDIRECT_IO_PLL 1 -#define INDIRECT_IO_MC 2 -#define INDIRECT_IO_PCIE 3 -#define INDIRECT_IO_PCIEP 4 -#define INDIRECT_IO_NBMISC 5 - -#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ -#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE -#define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ -#define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE -#define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ -#define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE -#define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ -#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE -#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ -#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE - -typedef struct _ATOM_OEM_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; -}ATOM_OEM_INFO; - -typedef struct _ATOM_TV_MODE -{ - UCHAR ucVMode_Num; //Video mode number - UCHAR ucTV_Mode_Num; //Internal TV mode number -}ATOM_TV_MODE; - -typedef struct _ATOM_BIOS_INT_TVSTD_MODE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table - USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table - USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table - USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table - USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table -}ATOM_BIOS_INT_TVSTD_MODE; - - -typedef struct _ATOM_TV_MODE_SCALER_PTR -{ - USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients - USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients - UCHAR ucTV_Mode_Num; -}ATOM_TV_MODE_SCALER_PTR; - -typedef struct _ATOM_STANDARD_VESA_TIMING -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_MODE_TIMING aModeTimings[16]; // 16 is not the real array number, just for initial allocation -}ATOM_STANDARD_VESA_TIMING; - - -typedef struct _ATOM_STD_FORMAT -{ - USHORT usSTD_HDisp; - USHORT usSTD_VDisp; - USHORT usSTD_RefreshRate; - USHORT usReserved; -}ATOM_STD_FORMAT; - -typedef struct _ATOM_VESA_TO_EXTENDED_MODE -{ - USHORT usVESA_ModeNumber; - USHORT usExtendedModeNumber; -}ATOM_VESA_TO_EXTENDED_MODE; - -typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT -{ - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; -}ATOM_VESA_TO_INTENAL_MODE_LUT; - -/*************** ATOM Memory Related Data Structure ***********************/ -typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ - UCHAR ucMemoryType; - UCHAR ucMemoryVendor; - UCHAR ucAdjMCId; - UCHAR ucDynClkId; - ULONG ulDllResetClkRange; -}ATOM_MEMORY_VENDOR_BLOCK; - - -typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ - ULONG ulMemClockRange:24; - ULONG ucMemBlkId:8; -}ATOM_MEMORY_SETTING_ID_CONFIG; - -typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS -{ - ATOM_MEMORY_SETTING_ID_CONFIG slAccess; - ULONG ulAccess; -}ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; - - -typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ - ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; - ULONG aulMemData[1]; -}ATOM_MEMORY_SETTING_DATA_BLOCK; - - -typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ - USHORT usRegIndex; // MC register index - UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf -}ATOM_INIT_REG_INDEX_FORMAT; - - -typedef struct _ATOM_INIT_REG_BLOCK{ - USHORT usRegIndexTblSize; //size of asRegIndexBuf - USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK - ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; - ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; -}ATOM_INIT_REG_BLOCK; - -#define END_OF_REG_INDEX_BLOCK 0x0ffff -#define END_OF_REG_DATA_BLOCK 0x00000000 -#define ATOM_INIT_REG_MASK_FLAG 0x80 -#define CLOCK_RANGE_HIGHEST 0x00ffffff - -#define VALUE_DWORD SIZEOF ULONG -#define VALUE_SAME_AS_ABOVE 0 -#define VALUE_MASK_DWORD 0x84 - -typedef struct _ATOM_MC_INIT_PARAM_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usAdjustARB_SEQDataOffset; - USHORT usMCInitMemTypeTblOffset; - USHORT usMCInitCommonTblOffset; - USHORT usMCInitPowerDownTblOffset; - ULONG ulARB_SEQDataBuf[32]; - ATOM_INIT_REG_BLOCK asMCInitMemType; - ATOM_INIT_REG_BLOCK asMCInitCommon; -}ATOM_MC_INIT_PARAM_TABLE; - - -#define _4Mx16 0x2 -#define _4Mx32 0x3 -#define _8Mx16 0x12 -#define _8Mx32 0x13 -#define _16Mx16 0x22 -#define _16Mx32 0x23 -#define _32Mx16 0x32 -#define _32Mx32 0x33 -#define _64Mx8 0x41 -#define _64Mx16 0x42 - -#define SAMSUNG 0x1 -#define INFINEON 0x2 -#define ELPIDA 0x3 -#define ETRON 0x4 -#define NANYA 0x5 -#define HYNIX 0x6 -#define MOSEL 0x7 -#define WINBOND 0x8 -#define ESMT 0x9 -#define MICRON 0xF - -#define QIMONDA INFINEON -#define PROMOS MOSEL - -#define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 - -#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF -typedef struct _ATOM_VRAM_MODULE_V1 -{ - ULONG ulReserved; - USHORT usEMRSValue; - USHORT usMRSValue; - USHORT usReserved; - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender - UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... - UCHAR ucRow; // Number of Row,in power of 2; - UCHAR ucColumn; // Number of Column,in power of 2; - UCHAR ucBank; // Nunber of Bank; - UCHAR ucRank; // Number of Rank, in power of 2 - UCHAR ucChannelNum; // Number of channel; - UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 - UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; - UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; - UCHAR ucReserved[2]; -}ATOM_VRAM_MODULE_V1; - - -typedef struct _ATOM_VRAM_MODULE_V2 -{ - ULONG ulReserved; - ULONG ulFlags; // To enable/disable functionalities based on memory type - ULONG ulEngineClock; // Override of default engine clock for particular memory type - ULONG ulMemoryClock; // Override of default memory clock for particular memory type - USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRSValue; - USHORT usMRSValue; - USHORT usReserved; - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed - UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... - UCHAR ucRow; // Number of Row,in power of 2; - UCHAR ucColumn; // Number of Column,in power of 2; - UCHAR ucBank; // Nunber of Bank; - UCHAR ucRank; // Number of Rank, in power of 2 - UCHAR ucChannelNum; // Number of channel; - UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 - UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; - UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; - UCHAR ucRefreshRateFactor; - UCHAR ucReserved[3]; -}ATOM_VRAM_MODULE_V2; - - -typedef struct _ATOM_MEMORY_TIMING_FORMAT -{ - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - USHORT usMRS; // mode register - USHORT usEMRS; // extended mode register - UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency - UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC - UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR - UCHAR uctRCDW; // tRCDW - UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD - UCHAR uctWR; // tWR - UCHAR uctWTR; // tWTR - UCHAR uctPDIX; // tPDIX - UCHAR uctFAW; // tFAW - UCHAR uctAOND; // tAOND - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon - UCHAR ucReserved; // -}ATOM_MEMORY_TIMING_FORMAT; - -#define MEM_TIMING_FLAG_APP_MODE 0x01 // =0 mid clock range =1 high clock range - -typedef struct _ATOM_MEMORY_FORMAT -{ - ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock - USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed - UCHAR ucRow; // Number of Row,in power of 2; - UCHAR ucColumn; // Number of Column,in power of 2; - UCHAR ucBank; // Nunber of Bank; - UCHAR ucRank; // Number of Rank, in power of 2 - UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 - UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) - UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms - UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 - UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble - UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc - ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock -}ATOM_MEMORY_FORMAT; - - -typedef struct _ATOM_VRAM_MODULE_V3 -{ - ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination - USHORT usSize; // size of ATOM_VRAM_MODULE_V3 - USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage - USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage - UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module - UCHAR ucChannelNum; // board dependent parameter:Number of channel; - UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit - UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv - UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters - UCHAR ucFlag; // To enable/disable functionalities based on memory type - ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec -}ATOM_VRAM_MODULE_V3; - - -//ATOM_VRAM_MODULE_V3.ucNPL_RT -#define NPL_RT_MASK 0x0f -#define BATTERY_ODT_MASK 0xc0 - -#define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 - -typedef struct _ATOM_VRAM_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; -}ATOM_VRAM_INFO_V2; - -typedef struct _ATOM_VRAM_INFO_V3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting - USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting - USHORT usRerseved; - UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator - UCHAR ucNumOfVRAMModule; - ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; - ATOM_INIT_REG_BLOCK asMemPatch; // for allocation - // ATOM_INIT_REG_BLOCK aMemAdjust; -}ATOM_VRAM_INFO_V3; - -#define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 - -typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator -}ATOM_VRAM_GPIO_DETECTION_INFO; - - -typedef struct _ATOM_MEMORY_TRAINING_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucTrainingLoop; - UCHAR ucReserved[3]; - ATOM_INIT_REG_BLOCK asMemTrainingSetting; -}ATOM_MEMORY_TRAINING_INFO; - - -typedef struct SW_I2C_CNTL_DATA_PARAMETERS -{ - UCHAR ucControl; - UCHAR ucData; - UCHAR ucSatus; - UCHAR ucTemp; -} SW_I2C_CNTL_DATA_PARAMETERS; - -#define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS - -typedef struct _SW_I2C_IO_DATA_PARAMETERS -{ - USHORT GPIO_Info; - UCHAR ucAct; - UCHAR ucData; - } SW_I2C_IO_DATA_PARAMETERS; - -#define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS - -/****************************SW I2C CNTL DEFINITIONS**********************/ -#define SW_I2C_IO_RESET 0 -#define SW_I2C_IO_GET 1 -#define SW_I2C_IO_DRIVE 2 -#define SW_I2C_IO_SET 3 -#define SW_I2C_IO_START 4 - -#define SW_I2C_IO_CLOCK 0 -#define SW_I2C_IO_DATA 0x80 - -#define SW_I2C_IO_ZERO 0 -#define SW_I2C_IO_ONE 0x100 - -#define SW_I2C_CNTL_READ 0 -#define SW_I2C_CNTL_WRITE 1 -#define SW_I2C_CNTL_START 2 -#define SW_I2C_CNTL_STOP 3 -#define SW_I2C_CNTL_OPEN 4 -#define SW_I2C_CNTL_CLOSE 5 -#define SW_I2C_CNTL_WRITE1BIT 6 - -//==============================VESA definition Portion=============================== -#define VESA_OEM_PRODUCT_REV '01.00' -#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support -#define VESA_MODE_WIN_ATTRIBUTE 7 -#define VESA_WIN_SIZE 64 - -typedef struct _PTR_32_BIT_STRUCTURE -{ - USHORT Offset16; - USHORT Segment16; -} PTR_32_BIT_STRUCTURE; - -typedef union _PTR_32_BIT_UNION -{ - PTR_32_BIT_STRUCTURE SegmentOffset; - ULONG Ptr32_Bit; -} PTR_32_BIT_UNION; - -typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE -{ - UCHAR VbeSignature[4]; - USHORT VbeVersion; - PTR_32_BIT_UNION OemStringPtr; - UCHAR Capabilities[4]; - PTR_32_BIT_UNION VideoModePtr; - USHORT TotalMemory; -} VBE_1_2_INFO_BLOCK_UPDATABLE; - - -typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE -{ - VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; - USHORT OemSoftRev; - PTR_32_BIT_UNION OemVendorNamePtr; - PTR_32_BIT_UNION OemProductNamePtr; - PTR_32_BIT_UNION OemProductRevPtr; -} VBE_2_0_INFO_BLOCK_UPDATABLE; - -typedef union _VBE_VERSION_UNION -{ - VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; - VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; -} VBE_VERSION_UNION; - -typedef struct _VBE_INFO_BLOCK -{ - VBE_VERSION_UNION UpdatableVBE_Info; - UCHAR Reserved[222]; - UCHAR OemData[256]; -} VBE_INFO_BLOCK; - -typedef struct _VBE_FP_INFO -{ - USHORT HSize; - USHORT VSize; - USHORT FPType; - UCHAR RedBPP; - UCHAR GreenBPP; - UCHAR BlueBPP; - UCHAR ReservedBPP; - ULONG RsvdOffScrnMemSize; - ULONG RsvdOffScrnMEmPtr; - UCHAR Reserved[14]; -} VBE_FP_INFO; - -typedef struct _VESA_MODE_INFO_BLOCK -{ -// Mandatory information for all VBE revisions - USHORT ModeAttributes; // dw ? ; mode attributes - UCHAR WinAAttributes; // db ? ; window A attributes - UCHAR WinBAttributes; // db ? ; window B attributes - USHORT WinGranularity; // dw ? ; window granularity - USHORT WinSize; // dw ? ; window size - USHORT WinASegment; // dw ? ; window A start segment - USHORT WinBSegment; // dw ? ; window B start segment - ULONG WinFuncPtr; // dd ? ; real mode pointer to window function - USHORT BytesPerScanLine;// dw ? ; bytes per scan line - -//; Mandatory information for VBE 1.2 and above - USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters - USHORT YResolution; // dw ? ; vertical resolution in pixels or characters - UCHAR XCharSize; // db ? ; character cell width in pixels - UCHAR YCharSize; // db ? ; character cell height in pixels - UCHAR NumberOfPlanes; // db ? ; number of memory planes - UCHAR BitsPerPixel; // db ? ; bits per pixel - UCHAR NumberOfBanks; // db ? ; number of banks - UCHAR MemoryModel; // db ? ; memory model type - UCHAR BankSize; // db ? ; bank size in KB - UCHAR NumberOfImagePages;// db ? ; number of images - UCHAR ReservedForPageFunction;//db 1 ; reserved for page function - -//; Direct Color fields(required for direct/6 and YUV/7 memory models) - UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits - UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask - UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits - UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask - UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits - UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask - UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits - UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask - UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes - -//; Mandatory information for VBE 2.0 and above - ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer - ULONG Reserved_1; // dd 0 ; reserved - always set to 0 - USHORT Reserved_2; // dw 0 ; reserved - always set to 0 - -//; Mandatory information for VBE 3.0 and above - USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes - UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes - UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes - UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) - UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) - UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) - UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) - UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) - UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) - UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) - UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) - ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode - UCHAR Reserved; // db 190 dup (0) -} VESA_MODE_INFO_BLOCK; - -// BIOS function CALLS -#define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code -#define ATOM_BIOS_FUNCTION_COP_MODE 0x00 -#define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 -#define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 -#define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 -#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B -#define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E -#define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F -#define ATOM_BIOS_FUNCTION_STV_STD 0x16 -#define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 -#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 - -#define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 -#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 -#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 -#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A -#define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B -#define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 -#define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 - -#define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D -#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E -#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F -#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 -#define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 -#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state -#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state -#define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 -#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 -#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported - - -#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS -#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 -#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 -#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. -#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY -#define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND -#define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF -#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) - -#define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L -#define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L -#define ATOM_BIOS_REG_LOW_MASK 0x000000FFL - -// structure used for VBIOS only - -//DispOutInfoTable -typedef struct _ASIC_TRANSMITTER_INFO -{ - USHORT usTransmitterObjId; - USHORT usSupportDevice; - UCHAR ucTransmitterCmdTblId; - UCHAR ucConfig; - UCHAR ucEncoderID; //available 1st encoder ( default ) - UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) - UCHAR uc2ndEncoderID; - UCHAR ucReserved; -}ASIC_TRANSMITTER_INFO; - -typedef struct _ASIC_ENCODER_INFO -{ - UCHAR ucEncoderID; - UCHAR ucEncoderConfig; - USHORT usEncoderCmdTblId; -}ASIC_ENCODER_INFO; - -typedef struct _ATOM_DISP_OUT_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT ptrTransmitterInfo; - USHORT ptrEncoderInfo; - ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; - ASIC_ENCODER_INFO asEncoderInfo[1]; -}ATOM_DISP_OUT_INFO; - -// DispDevicePriorityInfo -typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT asDevicePriority[16]; -}ATOM_DISPLAY_DEVICE_PRIORITY_INFO; - -//ProcessAuxChannelTransactionTable -typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS -{ - USHORT lpAuxRequest; - USHORT lpDataOut; - UCHAR ucChannelID; - union - { - UCHAR ucReplyStatus; - UCHAR ucDelay; - }; - UCHAR ucDataOutLen; - UCHAR ucReserved; -}PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; - -#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS - -//GetSinkType - -typedef struct _DP_ENCODER_SERVICE_PARAMETERS -{ - USHORT ucLinkClock; - union - { - UCHAR ucConfig; // for DP training command - UCHAR ucI2cId; // use for GET_SINK_TYPE command - }; - UCHAR ucAction; - UCHAR ucStatus; - UCHAR ucLaneNum; - UCHAR ucReserved[2]; -}DP_ENCODER_SERVICE_PARAMETERS; - -// ucAction -#define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 -#define ATOM_DP_ACTION_TRAINING_START 0x02 -#define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 -#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 -#define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 -#define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 - -// ucConfig -#define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 -#define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 -#define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 -#define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 -#define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 -#define ATOM_DP_CONFIG_LINK_A 0x00 -#define ATOM_DP_CONFIG_LINK_B 0x04 - -#define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS - -// DP_TRAINING_TABLE -#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR -#define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) -#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) -#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) -#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) -#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) -#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) -#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) -#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) -#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) -#define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) -#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) - - -typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS -{ - UCHAR ucI2CSpeed; - union - { - UCHAR ucRegIndex; - UCHAR ucStatus; - }; - USHORT lpI2CDataOut; - UCHAR ucFlag; - UCHAR ucTransBytes; - UCHAR ucSlaveAddr; - UCHAR ucLineNumber; -}PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; - -#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS - -//ucFlag -#define HW_I2C_WRITE 1 -#define HW_I2C_READ 0 - - -/****************************************************************************/ -//Portion VI: Definitinos being oboselete -/****************************************************************************/ - -//========================================================================================== -//Remove the definitions below when driver is ready! -typedef struct _ATOM_DAC_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMaxFrequency; // in 10kHz unit - USHORT usReserved; -}ATOM_DAC_INFO; - - -typedef struct _COMPASSIONATE_DATA -{ - ATOM_COMMON_TABLE_HEADER sHeader; - - //============================== DAC1 portion - UCHAR ucDAC1_BG_Adjustment; - UCHAR ucDAC1_DAC_Adjustment; - USHORT usDAC1_FORCE_Data; - //============================== DAC2 portion - UCHAR ucDAC2_CRT2_BG_Adjustment; - UCHAR ucDAC2_CRT2_DAC_Adjustment; - USHORT usDAC2_CRT2_FORCE_Data; - USHORT usDAC2_CRT2_MUX_RegisterIndex; - UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low - UCHAR ucDAC2_NTSC_BG_Adjustment; - UCHAR ucDAC2_NTSC_DAC_Adjustment; - USHORT usDAC2_TV1_FORCE_Data; - USHORT usDAC2_TV1_MUX_RegisterIndex; - UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low - UCHAR ucDAC2_CV_BG_Adjustment; - UCHAR ucDAC2_CV_DAC_Adjustment; - USHORT usDAC2_CV_FORCE_Data; - USHORT usDAC2_CV_MUX_RegisterIndex; - UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low - UCHAR ucDAC2_PAL_BG_Adjustment; - UCHAR ucDAC2_PAL_DAC_Adjustment; - USHORT usDAC2_TV2_FORCE_Data; -}COMPASSIONATE_DATA; - -/****************************Supported Device Info Table Definitions**********************/ -// ucConnectInfo: -// [7:4] - connector type -// = 1 - VGA connector -// = 2 - DVI-I -// = 3 - DVI-D -// = 4 - DVI-A -// = 5 - SVIDEO -// = 6 - COMPOSITE -// = 7 - LVDS -// = 8 - DIGITAL LINK -// = 9 - SCART -// = 0xA - HDMI_type A -// = 0xB - HDMI_type B -// = 0xE - Special case1 (DVI+DIN) -// Others=TBD -// [3:0] - DAC Associated -// = 0 - no DAC -// = 1 - DACA -// = 2 - DACB -// = 3 - External DAC -// Others=TBD -// - -typedef struct _ATOM_CONNECTOR_INFO -{ - UCHAR bfAssociatedDAC:4; - UCHAR bfConnectorType:4; -}ATOM_CONNECTOR_INFO; - -typedef union _ATOM_CONNECTOR_INFO_ACCESS -{ - ATOM_CONNECTOR_INFO sbfAccess; - UCHAR ucAccess; -}ATOM_CONNECTOR_INFO_ACCESS; - -typedef struct _ATOM_CONNECTOR_INFO_I2C -{ - ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; -}ATOM_CONNECTOR_INFO_I2C; - - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; -}ATOM_SUPPORTED_DEVICES_INFO; - -#define NO_INT_SRC_MAPPED 0xFF - -typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP -{ - UCHAR ucIntSrcBitmap; -}ATOM_CONNECTOR_INC_SRC_BITMAP; - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; - ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; -}ATOM_SUPPORTED_DEVICES_INFO_2; - -typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDeviceSupport; - ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; - ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; -}ATOM_SUPPORTED_DEVICES_INFO_2d1; - -#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 - - - -typedef struct _ATOM_MISC_CONTROL_INFO -{ - USHORT usFrequency; - UCHAR ucPLL_ChargePump; // PLL charge-pump gain control - UCHAR ucPLL_DutyCycle; // PLL duty cycle control - UCHAR ucPLL_VCO_Gain; // PLL VCO gain control - UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control -}ATOM_MISC_CONTROL_INFO; - - -#define ATOM_MAX_MISC_INFO 4 - -typedef struct _ATOM_TMDS_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usMaxFrequency; // in 10Khz - ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; -}ATOM_TMDS_INFO; - - -typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE -{ - UCHAR ucTVStandard; //Same as TV standards defined above, - UCHAR ucPadding[1]; -}ATOM_ENCODER_ANALOG_ATTRIBUTE; - -typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE -{ - UCHAR ucAttribute; //Same as other digital encoder attributes defined above - UCHAR ucPadding[1]; -}ATOM_ENCODER_DIGITAL_ATTRIBUTE; - -typedef union _ATOM_ENCODER_ATTRIBUTE -{ - ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; - ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; -}ATOM_ENCODER_ATTRIBUTE; - - -typedef struct _DVO_ENCODER_CONTROL_PARAMETERS -{ - USHORT usPixelClock; - USHORT usEncoderID; - UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. - UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT - ATOM_ENCODER_ATTRIBUTE usDevAttr; -}DVO_ENCODER_CONTROL_PARAMETERS; - -typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION -{ - DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; - WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion -}DVO_ENCODER_CONTROL_PS_ALLOCATION; - - -#define ATOM_XTMDS_ASIC_SI164_ID 1 -#define ATOM_XTMDS_ASIC_SI178_ID 2 -#define ATOM_XTMDS_ASIC_TFP513_ID 3 -#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 -#define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 -#define ATOM_XTMDS_MVPU_FPGA 0x00000004 - - -typedef struct _ATOM_XTMDS_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usSingleLinkMaxFrequency; - ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip - UCHAR ucXtransimitterID; - UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported - UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters - // due to design. This ID is used to alert driver that the sequence is not "standard"! - UCHAR ucMasterAddress; // Address to control Master xTMDS Chip - UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip -}ATOM_XTMDS_INFO; - -typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS -{ - UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off - UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... - UCHAR ucPadding[2]; -}DFP_DPMS_STATUS_CHANGE_PARAMETERS; - -/****************************Legacy Power Play Table Definitions **********************/ - -//Definitions for ulPowerPlayMiscInfo -#define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L -#define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L -#define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L - -#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L -#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L - -#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L - -#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L -#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L -#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program - -#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L -#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L -#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L -#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L -#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L -#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L -#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L - -#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L -#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L -#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L -#define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L -#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L - -#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved -#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 - -#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L -#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L -#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L -#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic -#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic -#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode - -#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) -#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 -#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L - -#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L -#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L -#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L -#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L -#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L -#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L -#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. - //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback -#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L -#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L -#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L - -//ucTableFormatRevision=1 -//ucTableContentRevision=1 -typedef struct _ATOM_POWERMODE_INFO -{ - ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulReserved1; // must set to 0 - ULONG ulReserved2; // must set to 0 - USHORT usEngineClock; - USHORT usMemoryClock; - UCHAR ucVoltageDropIndex; // index to GPIO table - UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; // number of PCIE lanes -}ATOM_POWERMODE_INFO; - -//ucTableFormatRevision=2 -//ucTableContentRevision=1 -typedef struct _ATOM_POWERMODE_INFO_V2 -{ - ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; - ULONG ulMemoryClock; - UCHAR ucVoltageDropIndex; // index to GPIO table - UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; // number of PCIE lanes -}ATOM_POWERMODE_INFO_V2; - -//ucTableFormatRevision=2 -//ucTableContentRevision=2 -typedef struct _ATOM_POWERMODE_INFO_V3 -{ - ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; - ULONG ulMemoryClock; - UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table - UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate - UCHAR ucMinTemperature; - UCHAR ucMaxTemperature; - UCHAR ucNumPciELanes; // number of PCIE lanes - UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table -}ATOM_POWERMODE_INFO_V3; - - -#define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 - -#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 -#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 - -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 -#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog - - -typedef struct _ATOM_POWERPLAY_INFO -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -}ATOM_POWERPLAY_INFO; - -typedef struct _ATOM_POWERPLAY_INFO_V2 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -}ATOM_POWERPLAY_INFO_V2; - -typedef struct _ATOM_POWERPLAY_INFO_V3 -{ - ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR ucOverdriveThermalController; - UCHAR ucOverdriveI2cLine; - UCHAR ucOverdriveIntBitmap; - UCHAR ucOverdriveControllerAddress; - UCHAR ucSizeOfPowerModeEntry; - UCHAR ucNumOfPowerModeEntries; - ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; -}ATOM_POWERPLAY_INFO_V3; - - - -/**************************************************************************/ - - -// Following definitions are for compatiblity issue in different SW components. -#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 -#define Object_Info Object_Header -#define AdjustARB_SEQ MC_InitParameter -#define VRAM_GPIO_DetectionInfo VoltageObjectInfo -#define ASIC_VDDCI_Info ASIC_ProfilingInfo -#define ASIC_MVDDQ_Info MemoryTrainingInfo -#define SS_Info PPLL_SS_Info -#define ASIC_MVDDC_Info ASIC_InternalSS_Info -#define DispDevicePriorityInfo SaveRestoreInfo -#define DispOutInfo TV_VideoMode - - -#define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE -#define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE - -//New device naming, remove them when both DAL/VBIOS is ready -#define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS -#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS - -#define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS -#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS - -#define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS -#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION - -#define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT -#define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT - -#define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX -#define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX - -#define ATOM_DEVICE_DFP2I_INDEX 0x00000009 -#define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) - -#define ATOM_S0_DFP1I ATOM_S0_DFP1 -#define ATOM_S0_DFP1X ATOM_S0_DFP2 - -#define ATOM_S0_DFP2I 0x00200000L -#define ATOM_S0_DFP2Ib2 0x20 - -#define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE -#define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE - -#define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L -#define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 - -#define ATOM_S3_DFP2I_ACTIVEb1 0x02 - -#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE -#define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE - -#define ATOM_S3_DFP2I_ACTIVE 0x00000200L - -#define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE -#define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE -#define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L - -#define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 -#define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 - -#define ATOM_S5_DOS_REQ_DFP2I 0x0200 -#define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 -#define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 - -#define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 -#define ATOM_S6_ACC_REQ_DFP2I 0x02000000L - -#define TMDS1XEncoderControl DVOEncoderControl -#define DFP1XOutputControl DVOOutputControl - -#define ExternalDFPOutputControl DFP1XOutputControl -#define EnableExternalTMDS_Encoder TMDS1XEncoderControl - -#define DFP1IOutputControl TMDSAOutputControl -#define DFP2IOutputControl LVTMAOutputControl - -#define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS -#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION - -#define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS -#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION - -#define ucDac1Standard ucDacStandard -#define ucDac2Standard ucDacStandard - -#define TMDS1EncoderControl TMDSAEncoderControl -#define TMDS2EncoderControl LVTMAEncoderControl - -#define DFP1OutputControl TMDSAOutputControl -#define DFP2OutputControl LVTMAOutputControl -#define CRT1OutputControl DAC1OutputControl -#define CRT2OutputControl DAC2OutputControl - -//These two lines will be removed for sure in a few days, will follow up with Michael V. -#define EnableLVDS_SS EnableSpreadSpectrumOnPPLL -#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL - -/*********************************************************************************/ -#define ATOM_S3_SCALER2_ACTIVE_H 0x00004000L -#define ATOM_S3_SCALER2_ACTIVE_V 0x00008000L -#define ATOM_S6_REQ_SCALER2_H 0x00004000L -#define ATOM_S6_REQ_SCALER2_V 0x00008000L - -#define ATOM_S3_SCALER1_ACTIVE_H ATOM_S3_LCD_FULLEXPANSION_ACTIVE -#define ATOM_S3_SCALER1_ACTIVE_V ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE - -#define ATOM_S6_REQ_SCALER1_H ATOM_S6_REQ_LCD_EXPANSION_FULL -#define ATOM_S6_REQ_SCALER1_V ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO -//========================================================================================== - -#pragma pack() // BIOS data must use byte aligment - -#endif /* _ATOMBIOS_H */ diff --git a/src/AtomBios/includes/regsdef.h b/src/AtomBios/includes/regsdef.h deleted file mode 100644 index e557ac0..0000000 --- a/src/AtomBios/includes/regsdef.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright 2006-2007 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -//This is a dummy file used by driver-parser during compilation. -//Without this file, compatibility will be broken among ASICs and BIOs vs. driver -//James H. Apr. 22/03 diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h deleted file mode 100644 index 330d1a9..0000000 --- a/src/ati_pciids_gen.h +++ /dev/null @@ -1,358 +0,0 @@ -#define PCI_CHIP_RV380_3150 0x3150 -#define PCI_CHIP_RV380_3152 0x3152 -#define PCI_CHIP_RV380_3154 0x3154 -#define PCI_CHIP_RV380_3E50 0x3E50 -#define PCI_CHIP_RV380_3E54 0x3E54 -#define PCI_CHIP_RS100_4136 0x4136 -#define PCI_CHIP_RS200_4137 0x4137 -#define PCI_CHIP_R300_AD 0x4144 -#define PCI_CHIP_R300_AE 0x4145 -#define PCI_CHIP_R300_AF 0x4146 -#define PCI_CHIP_R300_AG 0x4147 -#define PCI_CHIP_R350_AH 0x4148 -#define PCI_CHIP_R350_AI 0x4149 -#define PCI_CHIP_R350_AJ 0x414A -#define PCI_CHIP_R350_AK 0x414B -#define PCI_CHIP_RV350_AP 0x4150 -#define PCI_CHIP_RV350_AQ 0x4151 -#define PCI_CHIP_RV360_AR 0x4152 -#define PCI_CHIP_RV350_AS 0x4153 -#define PCI_CHIP_RV350_AT 0x4154 -#define PCI_CHIP_RV350_4155 0x4155 -#define PCI_CHIP_RV350_AV 0x4156 -#define PCI_CHIP_MACH32 0x4158 -#define PCI_CHIP_RS250_4237 0x4237 -#define PCI_CHIP_R200_BB 0x4242 -#define PCI_CHIP_R200_BC 0x4243 -#define PCI_CHIP_RS100_4336 0x4336 -#define PCI_CHIP_RS200_4337 0x4337 -#define PCI_CHIP_MACH64CT 0x4354 -#define PCI_CHIP_MACH64CX 0x4358 -#define PCI_CHIP_RS250_4437 0x4437 -#define PCI_CHIP_MACH64ET 0x4554 -#define PCI_CHIP_MACH64GB 0x4742 -#define PCI_CHIP_MACH64GD 0x4744 -#define PCI_CHIP_MACH64GI 0x4749 -#define PCI_CHIP_MACH64GL 0x474C -#define PCI_CHIP_MACH64GM 0x474D -#define PCI_CHIP_MACH64GN 0x474E -#define PCI_CHIP_MACH64GO 0x474F -#define PCI_CHIP_MACH64GP 0x4750 -#define PCI_CHIP_MACH64GQ 0x4751 -#define PCI_CHIP_MACH64GR 0x4752 -#define PCI_CHIP_MACH64GS 0x4753 -#define PCI_CHIP_MACH64GT 0x4754 -#define PCI_CHIP_MACH64GU 0x4755 -#define PCI_CHIP_MACH64GV 0x4756 -#define PCI_CHIP_MACH64GW 0x4757 -#define PCI_CHIP_MACH64GX 0x4758 -#define PCI_CHIP_MACH64GY 0x4759 -#define PCI_CHIP_MACH64GZ 0x475A -#define PCI_CHIP_RV250_If 0x4966 -#define PCI_CHIP_RV250_Ig 0x4967 -#define PCI_CHIP_R420_JH 0x4A48 -#define PCI_CHIP_R420_JI 0x4A49 -#define PCI_CHIP_R420_JJ 0x4A4A -#define PCI_CHIP_R420_JK 0x4A4B -#define PCI_CHIP_R420_JL 0x4A4C -#define PCI_CHIP_R420_JM 0x4A4D -#define PCI_CHIP_R420_JN 0x4A4E -#define PCI_CHIP_R420_4A4F 0x4A4F -#define PCI_CHIP_R420_JP 0x4A50 -#define PCI_CHIP_R481_4B49 0x4B49 -#define PCI_CHIP_R481_4B4A 0x4B4A -#define PCI_CHIP_R481_4B4B 0x4B4B -#define PCI_CHIP_R481_4B4C 0x4B4C -#define PCI_CHIP_MACH64LB 0x4C42 -#define PCI_CHIP_MACH64LD 0x4C44 -#define PCI_CHIP_RAGE128LE 0x4C45 -#define PCI_CHIP_RAGE128LF 0x4C46 -#define PCI_CHIP_MACH64LG 0x4C47 -#define PCI_CHIP_MACH64LI 0x4C49 -#define PCI_CHIP_MACH64LM 0x4C4D -#define PCI_CHIP_MACH64LN 0x4C4E -#define PCI_CHIP_MACH64LP 0x4C50 -#define PCI_CHIP_MACH64LQ 0x4C51 -#define PCI_CHIP_MACH64LR 0x4C52 -#define PCI_CHIP_MACH64LS 0x4C53 -#define PCI_CHIP_RADEON_LW 0x4C57 -#define PCI_CHIP_RADEON_LX 0x4C58 -#define PCI_CHIP_RADEON_LY 0x4C59 -#define PCI_CHIP_RADEON_LZ 0x4C5A -#define PCI_CHIP_RV250_Ld 0x4C64 -#define PCI_CHIP_RV250_Lf 0x4C66 -#define PCI_CHIP_RV250_Lg 0x4C67 -#define PCI_CHIP_RAGE128MF 0x4D46 -#define PCI_CHIP_RAGE128ML 0x4D4C -#define PCI_CHIP_R300_ND 0x4E44 -#define PCI_CHIP_R300_NE 0x4E45 -#define PCI_CHIP_R300_NF 0x4E46 -#define PCI_CHIP_R300_NG 0x4E47 -#define PCI_CHIP_R350_NH 0x4E48 -#define PCI_CHIP_R350_NI 0x4E49 -#define PCI_CHIP_R360_NJ 0x4E4A -#define PCI_CHIP_R350_NK 0x4E4B -#define PCI_CHIP_RV350_NP 0x4E50 -#define PCI_CHIP_RV350_NQ 0x4E51 -#define PCI_CHIP_RV350_NR 0x4E52 -#define PCI_CHIP_RV350_NS 0x4E53 -#define PCI_CHIP_RV350_NT 0x4E54 -#define PCI_CHIP_RV350_NV 0x4E56 -#define PCI_CHIP_RAGE128PA 0x5041 -#define PCI_CHIP_RAGE128PB 0x5042 -#define PCI_CHIP_RAGE128PC 0x5043 -#define PCI_CHIP_RAGE128PD 0x5044 -#define PCI_CHIP_RAGE128PE 0x5045 -#define PCI_CHIP_RAGE128PF 0x5046 -#define PCI_CHIP_RAGE128PG 0x5047 -#define PCI_CHIP_RAGE128PH 0x5048 -#define PCI_CHIP_RAGE128PI 0x5049 -#define PCI_CHIP_RAGE128PJ 0x504A -#define PCI_CHIP_RAGE128PK 0x504B -#define PCI_CHIP_RAGE128PL 0x504C -#define PCI_CHIP_RAGE128PM 0x504D -#define PCI_CHIP_RAGE128PN 0x504E -#define PCI_CHIP_RAGE128PO 0x504F -#define PCI_CHIP_RAGE128PP 0x5050 -#define PCI_CHIP_RAGE128PQ 0x5051 -#define PCI_CHIP_RAGE128PR 0x5052 -#define PCI_CHIP_RAGE128PS 0x5053 -#define PCI_CHIP_RAGE128PT 0x5054 -#define PCI_CHIP_RAGE128PU 0x5055 -#define PCI_CHIP_RAGE128PV 0x5056 -#define PCI_CHIP_RAGE128PW 0x5057 -#define PCI_CHIP_RAGE128PX 0x5058 -#define PCI_CHIP_RADEON_QD 0x5144 -#define PCI_CHIP_RADEON_QE 0x5145 -#define PCI_CHIP_RADEON_QF 0x5146 -#define PCI_CHIP_RADEON_QG 0x5147 -#define PCI_CHIP_R200_QH 0x5148 -#define PCI_CHIP_R200_QL 0x514C -#define PCI_CHIP_R200_QM 0x514D -#define PCI_CHIP_RV200_QW 0x5157 -#define PCI_CHIP_RV200_QX 0x5158 -#define PCI_CHIP_RV100_QY 0x5159 -#define PCI_CHIP_RV100_QZ 0x515A -#define PCI_CHIP_RN50_515E 0x515E -#define PCI_CHIP_RAGE128RE 0x5245 -#define PCI_CHIP_RAGE128RF 0x5246 -#define PCI_CHIP_RAGE128RG 0x5247 -#define PCI_CHIP_RAGE128RK 0x524B -#define PCI_CHIP_RAGE128RL 0x524C -#define PCI_CHIP_RAGE128SE 0x5345 -#define PCI_CHIP_RAGE128SF 0x5346 -#define PCI_CHIP_RAGE128SG 0x5347 -#define PCI_CHIP_RAGE128SH 0x5348 -#define PCI_CHIP_RAGE128SK 0x534B -#define PCI_CHIP_RAGE128SL 0x534C -#define PCI_CHIP_RAGE128SM 0x534D -#define PCI_CHIP_RAGE128SN 0x534E -#define PCI_CHIP_RAGE128TF 0x5446 -#define PCI_CHIP_RAGE128TL 0x544C -#define PCI_CHIP_RAGE128TR 0x5452 -#define PCI_CHIP_RAGE128TS 0x5453 -#define PCI_CHIP_RAGE128TT 0x5454 -#define PCI_CHIP_RAGE128TU 0x5455 -#define PCI_CHIP_RV370_5460 0x5460 -#define PCI_CHIP_RV370_5462 0x5462 -#define PCI_CHIP_RV370_5464 0x5464 -#define PCI_CHIP_R423_UH 0x5548 -#define PCI_CHIP_R423_UI 0x5549 -#define PCI_CHIP_R423_UJ 0x554A -#define PCI_CHIP_R423_UK 0x554B -#define PCI_CHIP_R430_554C 0x554C -#define PCI_CHIP_R430_554D 0x554D -#define PCI_CHIP_R430_554E 0x554E -#define PCI_CHIP_R430_554F 0x554F -#define PCI_CHIP_R423_5550 0x5550 -#define PCI_CHIP_R423_UQ 0x5551 -#define PCI_CHIP_R423_UR 0x5552 -#define PCI_CHIP_R423_UT 0x5554 -#define PCI_CHIP_RV410_564A 0x564A -#define PCI_CHIP_RV410_564B 0x564B -#define PCI_CHIP_RV410_564F 0x564F -#define PCI_CHIP_RV410_5652 0x5652 -#define PCI_CHIP_RV410_5653 0x5653 -#define PCI_CHIP_MACH64VT 0x5654 -#define PCI_CHIP_MACH64VU 0x5655 -#define PCI_CHIP_MACH64VV 0x5656 -#define PCI_CHIP_RS300_5834 0x5834 -#define PCI_CHIP_RS300_5835 0x5835 -#define PCI_CHIP_RS480_5954 0x5954 -#define PCI_CHIP_RS480_5955 0x5955 -#define PCI_CHIP_RV280_5960 0x5960 -#define PCI_CHIP_RV280_5961 0x5961 -#define PCI_CHIP_RV280_5962 0x5962 -#define PCI_CHIP_RV280_5964 0x5964 -#define PCI_CHIP_RV280_5965 0x5965 -#define PCI_CHIP_RN50_5969 0x5969 -#define PCI_CHIP_RS482_5974 0x5974 -#define PCI_CHIP_RS485_5975 0x5975 -#define PCI_CHIP_RS400_5A41 0x5A41 -#define PCI_CHIP_RS400_5A42 0x5A42 -#define PCI_CHIP_RC410_5A61 0x5A61 -#define PCI_CHIP_RC410_5A62 0x5A62 -#define PCI_CHIP_RV370_5B60 0x5B60 -#define PCI_CHIP_RV370_5B62 0x5B62 -#define PCI_CHIP_RV370_5B63 0x5B63 -#define PCI_CHIP_RV370_5657 0x5657 -#define PCI_CHIP_RV370_5B64 0x5B64 -#define PCI_CHIP_RV370_5B65 0x5B65 -#define PCI_CHIP_RV280_5C61 0x5C61 -#define PCI_CHIP_RV280_5C63 0x5C63 -#define PCI_CHIP_R430_5D48 0x5D48 -#define PCI_CHIP_R430_5D49 0x5D49 -#define PCI_CHIP_R430_5D4A 0x5D4A -#define PCI_CHIP_R480_5D4C 0x5D4C -#define PCI_CHIP_R480_5D4D 0x5D4D -#define PCI_CHIP_R480_5D4E 0x5D4E -#define PCI_CHIP_R480_5D4F 0x5D4F -#define PCI_CHIP_R480_5D50 0x5D50 -#define PCI_CHIP_R480_5D52 0x5D52 -#define PCI_CHIP_R423_5D57 0x5D57 -#define PCI_CHIP_RV410_5E48 0x5E48 -#define PCI_CHIP_RV410_5E4A 0x5E4A -#define PCI_CHIP_RV410_5E4B 0x5E4B -#define PCI_CHIP_RV410_5E4C 0x5E4C -#define PCI_CHIP_RV410_5E4D 0x5E4D -#define PCI_CHIP_RV410_5E4F 0x5E4F -#define PCI_CHIP_R520_7100 0x7100 -#define PCI_CHIP_R520_7101 0x7101 -#define PCI_CHIP_R520_7102 0x7102 -#define PCI_CHIP_R520_7103 0x7103 -#define PCI_CHIP_R520_7104 0x7104 -#define PCI_CHIP_R520_7105 0x7105 -#define PCI_CHIP_R520_7106 0x7106 -#define PCI_CHIP_R520_7108 0x7108 -#define PCI_CHIP_R520_7109 0x7109 -#define PCI_CHIP_R520_710A 0x710A -#define PCI_CHIP_R520_710B 0x710B -#define PCI_CHIP_R520_710C 0x710C -#define PCI_CHIP_R520_710E 0x710E -#define PCI_CHIP_R520_710F 0x710F -#define PCI_CHIP_RV515_7140 0x7140 -#define PCI_CHIP_RV515_7141 0x7141 -#define PCI_CHIP_RV515_7142 0x7142 -#define PCI_CHIP_RV515_7143 0x7143 -#define PCI_CHIP_RV515_7144 0x7144 -#define PCI_CHIP_RV515_7145 0x7145 -#define PCI_CHIP_RV515_7146 0x7146 -#define PCI_CHIP_RV515_7147 0x7147 -#define PCI_CHIP_RV515_7149 0x7149 -#define PCI_CHIP_RV515_714A 0x714A -#define PCI_CHIP_RV515_714B 0x714B -#define PCI_CHIP_RV515_714C 0x714C -#define PCI_CHIP_RV515_714D 0x714D -#define PCI_CHIP_RV515_714E 0x714E -#define PCI_CHIP_RV515_714F 0x714F -#define PCI_CHIP_RV515_7151 0x7151 -#define PCI_CHIP_RV515_7152 0x7152 -#define PCI_CHIP_RV515_7153 0x7153 -#define PCI_CHIP_RV515_715E 0x715E -#define PCI_CHIP_RV515_715F 0x715F -#define PCI_CHIP_RV515_7180 0x7180 -#define PCI_CHIP_RV515_7181 0x7181 -#define PCI_CHIP_RV515_7183 0x7183 -#define PCI_CHIP_RV515_7186 0x7186 -#define PCI_CHIP_RV515_7187 0x7187 -#define PCI_CHIP_RV515_7188 0x7188 -#define PCI_CHIP_RV515_718A 0x718A -#define PCI_CHIP_RV515_718B 0x718B -#define PCI_CHIP_RV515_718C 0x718C -#define PCI_CHIP_RV515_718D 0x718D -#define PCI_CHIP_RV515_718F 0x718F -#define PCI_CHIP_RV515_7193 0x7193 -#define PCI_CHIP_RV515_7196 0x7196 -#define PCI_CHIP_RV515_719B 0x719B -#define PCI_CHIP_RV515_719F 0x719F -#define PCI_CHIP_RV530_71C0 0x71C0 -#define PCI_CHIP_RV530_71C1 0x71C1 -#define PCI_CHIP_RV530_71C2 0x71C2 -#define PCI_CHIP_RV530_71C3 0x71C3 -#define PCI_CHIP_RV530_71C4 0x71C4 -#define PCI_CHIP_RV530_71C5 0x71C5 -#define PCI_CHIP_RV530_71C6 0x71C6 -#define PCI_CHIP_RV530_71C7 0x71C7 -#define PCI_CHIP_RV530_71CD 0x71CD -#define PCI_CHIP_RV530_71CE 0x71CE -#define PCI_CHIP_RV530_71D2 0x71D2 -#define PCI_CHIP_RV530_71D4 0x71D4 -#define PCI_CHIP_RV530_71D5 0x71D5 -#define PCI_CHIP_RV530_71D6 0x71D6 -#define PCI_CHIP_RV530_71DA 0x71DA -#define PCI_CHIP_RV530_71DE 0x71DE -#define PCI_CHIP_RV530_7200 0x7200 -#define PCI_CHIP_RV530_7210 0x7210 -#define PCI_CHIP_RV530_7211 0x7211 -#define PCI_CHIP_R580_7240 0x7240 -#define PCI_CHIP_R580_7243 0x7243 -#define PCI_CHIP_R580_7244 0x7244 -#define PCI_CHIP_R580_7245 0x7245 -#define PCI_CHIP_R580_7246 0x7246 -#define PCI_CHIP_R580_7247 0x7247 -#define PCI_CHIP_R580_7248 0x7248 -#define PCI_CHIP_R580_7249 0x7249 -#define PCI_CHIP_R580_724A 0x724A -#define PCI_CHIP_R580_724B 0x724B -#define PCI_CHIP_R580_724C 0x724C -#define PCI_CHIP_R580_724D 0x724D -#define PCI_CHIP_R580_724E 0x724E -#define PCI_CHIP_R580_724F 0x724F -#define PCI_CHIP_RV570_7280 0x7280 -#define PCI_CHIP_RV560_7281 0x7281 -#define PCI_CHIP_RV560_7283 0x7283 -#define PCI_CHIP_R580_7284 0x7284 -#define PCI_CHIP_RV560_7287 0x7287 -#define PCI_CHIP_RV570_7288 0x7288 -#define PCI_CHIP_RV570_7289 0x7289 -#define PCI_CHIP_RV570_728B 0x728B -#define PCI_CHIP_RV570_728C 0x728C -#define PCI_CHIP_RV560_7290 0x7290 -#define PCI_CHIP_RV560_7291 0x7291 -#define PCI_CHIP_RV560_7293 0x7293 -#define PCI_CHIP_RV560_7297 0x7297 -#define PCI_CHIP_RS350_7834 0x7834 -#define PCI_CHIP_RS350_7835 0x7835 -#define PCI_CHIP_RS690_791E 0x791E -#define PCI_CHIP_RS690_791F 0x791F -#define PCI_CHIP_RS740_796C 0x796C -#define PCI_CHIP_RS740_796D 0x796D -#define PCI_CHIP_RS740_796E 0x796E -#define PCI_CHIP_RS740_796F 0x796F -#define PCI_CHIP_R600_9400 0x9400 -#define PCI_CHIP_R600_9401 0x9401 -#define PCI_CHIP_R600_9402 0x9402 -#define PCI_CHIP_R600_9403 0x9403 -#define PCI_CHIP_R600_9405 0x9405 -#define PCI_CHIP_R600_940A 0x940A -#define PCI_CHIP_R600_940B 0x940B -#define PCI_CHIP_R600_940F 0x940F -#define PCI_CHIP_RV610_94C0 0x94C0 -#define PCI_CHIP_RV610_94C1 0x94C1 -#define PCI_CHIP_RV610_94C3 0x94C3 -#define PCI_CHIP_RV610_94C4 0x94C4 -#define PCI_CHIP_RV610_94C5 0x94C5 -#define PCI_CHIP_RV610_94C6 0x94C6 -#define PCI_CHIP_RV610_94C7 0x94C7 -#define PCI_CHIP_RV610_94C8 0x94C8 -#define PCI_CHIP_RV610_94C9 0x94C9 -#define PCI_CHIP_RV610_94CB 0x94CB -#define PCI_CHIP_RV610_94CC 0x94CC -#define PCI_CHIP_RV670_9500 0x9500 -#define PCI_CHIP_RV670_9501 0x9501 -#define PCI_CHIP_RV670_9505 0x9505 -#define PCI_CHIP_RV670_9507 0x9507 -#define PCI_CHIP_RV670_950F 0x950F -#define PCI_CHIP_RV670_9511 0x9511 -#define PCI_CHIP_RV630_9580 0x9580 -#define PCI_CHIP_RV630_9581 0x9581 -#define PCI_CHIP_RV630_9583 0x9583 -#define PCI_CHIP_RV630_9586 0x9586 -#define PCI_CHIP_RV630_9587 0x9587 -#define PCI_CHIP_RV630_9588 0x9588 -#define PCI_CHIP_RV630_9589 0x9589 -#define PCI_CHIP_RV630_958A 0x958A -#define PCI_CHIP_RV630_958B 0x958B -#define PCI_CHIP_RV630_958C 0x958C -#define PCI_CHIP_RV630_958D 0x958D -#define PCI_CHIP_RV630_958E 0x958E diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv deleted file mode 100644 index 5a2191a..0000000 --- a/src/pcidb/ati_pciids.csv +++ /dev/null @@ -1,359 +0,0 @@ -"#pciid","define","family","mobility","igp","nocrtc2","Nointtvout","singledac","name" -"0x3150","RV380_3150","RV380",1,,,,,"ATI Radeon Mobility X600 (M24) 3150 (PCIE)" -"0x3152","RV380_3152","RV380",1,,,,,"ATI Radeon Mobility X300 (M24) 3152 (PCIE)" -"0x3154","RV380_3154","RV380",1,,,,,"ATI FireGL M24 GL 3154 (PCIE)" -"0x3E50","RV380_3E50","RV380",,,,,,"ATI Radeon X600 (RV380) 3E50 (PCIE)" -"0x3E54","RV380_3E54","RV380",,,,,,"ATI FireGL V3200 (RV380) 3E54 (PCIE)" -"0x4136","RS100_4136","RS100",,1,,,1,"ATI Radeon IGP320 (A3) 4136" -"0x4137","RS200_4137","RS200",,1,,,1,"ATI Radeon IGP330/340/350 (A4) 4137" -"0x4144","R300_AD","R300",,,,,,"ATI Radeon 9500 AD (AGP)" -"0x4145","R300_AE","R300",,,,,,"ATI Radeon 9500 AE (AGP)" -"0x4146","R300_AF","R300",,,,,,"ATI Radeon 9600TX AF (AGP)" -"0x4147","R300_AG","R300",,,,,,"ATI FireGL Z1 AG (AGP)" -"0x4148","R350_AH","R350",,,,,,"ATI Radeon 9800SE AH (AGP)" -"0x4149","R350_AI","R350",,,,,,"ATI Radeon 9800 AI (AGP)" -"0x414A","R350_AJ","R350",,,,,,"ATI Radeon 9800 AJ (AGP)" -"0x414B","R350_AK","R350",,,,,,"ATI FireGL X2 AK (AGP)" -"0x4150","RV350_AP","RV350",,,,,,"ATI Radeon 9600 AP (AGP)" -"0x4151","RV350_AQ","RV350",,,,,,"ATI Radeon 9600SE AQ (AGP)" -"0x4152","RV360_AR","RV350",,,,,,"ATI Radeon 9600XT AR (AGP)" -"0x4153","RV350_AS","RV350",,,,,,"ATI Radeon 9600 AS (AGP)" -"0x4154","RV350_AT","RV350",,,,,,"ATI FireGL T2 AT (AGP)" -"0x4155","RV350_4155","RV350",,,,,,"ATI Radeon 9650" -"0x4156","RV350_AV","RV350",,,,,,"ATI FireGL RV360 AV (AGP)" -"0x4158","MACH32","MACH32",,,,,, -"0x4237","RS250_4237","RS200",,1,,,1,"ATI Radeon 7000 IGP (A4+) 4237" -"0x4242","R200_BB","R200",,,,1,,"ATI Radeon 8500 AIW BB (AGP)" -"0x4243","R200_BC","R200",,,,1,,"ATI Radeon 8500 AIW BC (AGP)" -"0x4336","RS100_4336","RS100",1,1,,,1,"ATI Radeon IGP320M (U1) 4336" -"0x4337","RS200_4337","RS200",1,1,,,1,"ATI Radeon IGP330M/340M/350M (U2) 4337" -"0x4354","MACH64CT","MACH64",,,,,, -"0x4358","MACH64CX","MACH64",,,,,, -"0x4437","RS250_4437","RS200",1,1,,,1,"ATI Radeon Mobility 7000 IGP 4437" -"0x4554","MACH64ET","MACH64",,,,,, -"0x4742","MACH64GB","MACH64",,,,,, -"0x4744","MACH64GD","MACH64",,,,,, -"0x4749","MACH64GI","MACH64",,,,,, -"0x474C","MACH64GL","MACH64",,,,,, -"0x474D","MACH64GM","MACH64",,,,,, -"0x474E","MACH64GN","MACH64",,,,,, -"0x474F","MACH64GO","MACH64",,,,,, -"0x4750","MACH64GP","MACH64",,,,,, -"0x4751","MACH64GQ","MACH64",,,,,, -"0x4752","MACH64GR","MACH64",,,,,, -"0x4753","MACH64GS","MACH64",,,,,, -"0x4754","MACH64GT","MACH64",,,,,, -"0x4755","MACH64GU","MACH64",,,,,, -"0x4756","MACH64GV","MACH64",,,,,, -"0x4757","MACH64GW","MACH64",,,,,, -"0x4758","MACH64GX","MACH64",,,,,, -"0x4759","MACH64GY","MACH64",,,,,, -"0x475A","MACH64GZ","MACH64",,,,,, -"0x4966","RV250_If","RV250",,,,,,"ATI Radeon 9000/PRO If (AGP/PCI)" -"0x4967","RV250_Ig","RV250",,,,,,"ATI Radeon 9000 Ig (AGP/PCI)" -"0x4A48","R420_JH","R420",,,,,,"ATI Radeon X800 (R420) JH (AGP)" -"0x4A49","R420_JI","R420",,,,,,"ATI Radeon X800PRO (R420) JI (AGP)" -"0x4A4A","R420_JJ","R420",,,,,,"ATI Radeon X800SE (R420) JJ (AGP)" -"0x4A4B","R420_JK","R420",,,,,,"ATI Radeon X800 (R420) JK (AGP)" -"0x4A4C","R420_JL","R420",,,,,,"ATI Radeon X800 (R420) JL (AGP)" -"0x4A4D","R420_JM","R420",,,,,,"ATI FireGL X3 (R420) JM (AGP)" -"0x4A4E","R420_JN","R420",1,,,,,"ATI Radeon Mobility 9800 (M18) JN (AGP)" -"0x4A4F","R420_4A4F","R420",,,,,,"ATI Radeon X800 SE (R420) (AGP)" -"0x4A50","R420_JP","R420",,,,,,"ATI Radeon X800XT (R420) JP (AGP)" -"0x4B49","R481_4B49","R420",,,,,,"ATI Radeon X850 XT (R480) (AGP)" -"0x4B4A","R481_4B4A","R420",,,,,,"ATI Radeon X850 SE (R480) (AGP)" -"0x4B4B","R481_4B4B","R420",,,,,,"ATI Radeon X850 PRO (R480) (AGP)" -"0x4B4C","R481_4B4C","R420",,,,,,"ATI Radeon X850 XT PE (R480) (AGP)" -"0x4C42","MACH64LB","MACH64",,,,,, -"0x4C44","MACH64LD","MACH64",,,,,, -"0x4C45","RAGE128LE","R128",,,,,, -"0x4C46","RAGE128LF","R128",,,,,, -"0x4C47","MACH64LG","MACH64",,,,,, -"0x4C49","MACH64LI","MACH64",,,,,, -"0x4C4D","MACH64LM","MACH64",,,,,, -"0x4C4E","MACH64LN","MACH64",,,,,, -"0x4C50","MACH64LP","MACH64",,,,,, -"0x4C51","MACH64LQ","MACH64",,,,,, -"0x4C52","MACH64LR","MACH64",,,,,, -"0x4C53","MACH64LS","MACH64",,,,,, -"0x4C57","RADEON_LW","RV200",1,,,,,"ATI Radeon Mobility M7 LW (AGP)" -"0x4C58","RADEON_LX","RV200",1,,,,,"ATI Mobility FireGL 7800 M7 LX (AGP)" -"0x4C59","RADEON_LY","RV100",1,,,,,"ATI Radeon Mobility M6 LY (AGP)" -"0x4C5A","RADEON_LZ","RV100",1,,,,,"ATI Radeon Mobility M6 LZ (AGP)" -"0x4C64","RV250_Ld","RV250",1,,,,,"ATI FireGL Mobility 9000 (M9) Ld (AGP)" -"0x4C66","RV250_Lf","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lf (AGP)" -"0x4C67","RV250_Lg","RV250",1,,,,,"ATI Radeon Mobility 9000 (M9) Lg (AGP)" -"0x4D46","RAGE128MF","R128",,,,,, -"0x4D4C","RAGE128ML","R128",,,,,, -"0x4E44","R300_ND","R300",,,,,,"ATI Radeon 9700 Pro ND (AGP)" -"0x4E45","R300_NE","R300",,,,,,"ATI Radeon 9700/9500Pro NE (AGP)" -"0x4E46","R300_NF","R300",,,,,,"ATI Radeon 9600TX NF (AGP)" -"0x4E47","R300_NG","R300",,,,,,"ATI FireGL X1 NG (AGP)" -"0x4E48","R350_NH","R350",,,,,,"ATI Radeon 9800PRO NH (AGP)" -"0x4E49","R350_NI","R350",,,,,,"ATI Radeon 9800 NI (AGP)" -"0x4E4A","R360_NJ","R350",,,,,,"ATI FireGL X2 NK (AGP)" -"0x4E4B","R350_NK","R350",,,,,,"ATI Radeon 9800XT NJ (AGP)" -"0x4E50","RV350_NP","RV350",1,,,,,"ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" -"0x4E51","RV350_NQ","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NQ (AGP)" -"0x4E52","RV350_NR","RV350",1,,,,,"ATI Radeon Mobility 9600 (M11) NR (AGP)" -"0x4E53","RV350_NS","RV350",1,,,,,"ATI Radeon Mobility 9600 (M10) NS (AGP)" -"0x4E54","RV350_NT","RV350",1,,,,,"ATI FireGL Mobility T2 (M10) NT (AGP)" -"0x4E56","RV350_NV","RV350",1,,,,,"ATI FireGL Mobility T2e (M11) NV (AGP)" -"0x5041","RAGE128PA","R128",,,,,, -"0x5042","RAGE128PB","R128",,,,,, -"0x5043","RAGE128PC","R128",,,,,, -"0x5044","RAGE128PD","R128",,,,,, -"0x5045","RAGE128PE","R128",,,,,, -"0x5046","RAGE128PF","R128",,,,,, -"0x5047","RAGE128PG","R128",,,,,, -"0x5048","RAGE128PH","R128",,,,,, -"0x5049","RAGE128PI","R128",,,,,, -"0x504A","RAGE128PJ","R128",,,,,, -"0x504B","RAGE128PK","R128",,,,,, -"0x504C","RAGE128PL","R128",,,,,, -"0x504D","RAGE128PM","R128",,,,,, -"0x504E","RAGE128PN","R128",,,,,, -"0x504F","RAGE128PO","R128",,,,,, -"0x5050","RAGE128PP","R128",,,,,, -"0x5051","RAGE128PQ","R128",,,,,, -"0x5052","RAGE128PR","R128",,,,,, -"0x5053","RAGE128PS","R128",,,,,, -"0x5054","RAGE128PT","R128",,,,,, -"0x5055","RAGE128PU","R128",,,,,, -"0x5056","RAGE128PV","R128",,,,,, -"0x5057","RAGE128PW","R128",,,,,, -"0x5058","RAGE128PX","R128",,,,,, -"0x5144","RADEON_QD","RADEON",,,1,1,,"ATI Radeon QD (AGP)" -"0x5145","RADEON_QE","RADEON",,,1,1,,"ATI Radeon QE (AGP)" -"0x5146","RADEON_QF","RADEON",,,1,1,,"ATI Radeon QF (AGP)" -"0x5147","RADEON_QG","RADEON",,,1,1,,"ATI Radeon QG (AGP)" -"0x5148","R200_QH","R200",,,,1,,"ATI FireGL 8700/8800 QH (AGP)" -"0x514C","R200_QL","R200",,,,1,,"ATI Radeon 8500 QL (AGP)" -"0x514D","R200_QM","R200",,,,1,,"ATI Radeon 9100 QM (AGP)" -"0x5157","RV200_QW","RV200",,,,,,"ATI Radeon 7500 QW (AGP/PCI)" -"0x5158","RV200_QX","RV200",,,,,,"ATI Radeon 7500 QX (AGP/PCI)" -"0x5159","RV100_QY","RV100",,,,,,"ATI Radeon VE/7000 QY (AGP/PCI)" -"0x515A","RV100_QZ","RV100",,,,,,"ATI Radeon VE/7000 QZ (AGP/PCI)" -"0x515E","RN50_515E","RV100",,,1,,,"ATI ES1000 515E (PCI)" -"0x5245","RAGE128RE","R128",,,,,, -"0x5246","RAGE128RF","R128",,,,,, -"0x5247","RAGE128RG","R128",,,,,, -"0x524B","RAGE128RK","R128",,,,,, -"0x524C","RAGE128RL","R128",,,,,, -"0x5345","RAGE128SE","R128",,,,,, -"0x5346","RAGE128SF","R128",,,,,, -"0x5347","RAGE128SG","R128",,,,,, -"0x5348","RAGE128SH","R128",,,,,, -"0x534B","RAGE128SK","R128",,,,,, -"0x534C","RAGE128SL","R128",,,,,, -"0x534D","RAGE128SM","R128",,,,,, -"0x534E","RAGE128SN","R128",,,,,, -"0x5446","RAGE128TF","R128",,,,,, -"0x544C","RAGE128TL","R128",,,,,, -"0x5452","RAGE128TR","R128",,,,,, -"0x5453","RAGE128TS","R128",,,,,, -"0x5454","RAGE128TT","R128",,,,,, -"0x5455","RAGE128TU","R128",,,,,, -"0x5460","RV370_5460","RV380",1,,,,,"ATI Radeon Mobility X300 (M22) 5460 (PCIE)" -"0x5462","RV370_5462","RV380",1,,,,,"ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" -"0x5464","RV370_5464","RV380",1,,,,,"ATI FireGL M22 GL 5464 (PCIE)" -"0x5548","R423_UH","R420",,,,,,"ATI Radeon X800 (R423) UH (PCIE)" -"0x5549","R423_UI","R420",,,,,,"ATI Radeon X800PRO (R423) UI (PCIE)" -"0x554A","R423_UJ","R420",,,,,,"ATI Radeon X800LE (R423) UJ (PCIE)" -"0x554B","R423_UK","R420",,,,,,"ATI Radeon X800SE (R423) UK (PCIE)" -"0x554C","R430_554C","R420",,,,,,"ATI Radeon X800 XTP (R430) (PCIE)" -"0x554D","R430_554D","R420",,,,,,"ATI Radeon X800 XL (R430) (PCIE)" -"0x554E","R430_554E","R420",,,,,,"ATI Radeon X800 SE (R430) (PCIE)" -"0x554F","R430_554F","R420",,,,,,"ATI Radeon X800 (R430) (PCIE)" -"0x5550","R423_5550","R420",,,,,,"ATI FireGL V7100 (R423) (PCIE)" -"0x5551","R423_UQ","R420",,,,,,"ATI FireGL V5100 (R423) UQ (PCIE)" -"0x5552","R423_UR","R420",,,,,,"ATI FireGL unknown (R423) UR (PCIE)" -"0x5554","R423_UT","R420",,,,,,"ATI FireGL unknown (R423) UT (PCIE)" -"0x564A","RV410_564A","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)" -"0x564B","RV410_564B","RV410",1,,,,,"ATI Mobility FireGL V5000 (M26) (PCIE)" -"0x564F","RV410_564F","RV410",1,,,,,"ATI Mobility Radeon X700 XL (M26) (PCIE)" -"0x5652","RV410_5652","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" -"0x5653","RV410_5653","RV410",1,,,,,"ATI Mobility Radeon X700 (M26) (PCIE)" -"0x5654","MACH64VT","MACH64",,,,,, -"0x5655","MACH64VU","MACH64",,,,,, -"0x5656","MACH64VV","MACH64",,,,,, -"0x5834","RS300_5834","RS300",,1,,,1,"ATI Radeon 9100 IGP (A5) 5834" -"0x5835","RS300_5835","RS300",1,1,,,1,"ATI Radeon Mobility 9100 IGP (U3) 5835" -"0x5954","RS480_5954","RS400",,1,,,1,"ATI Radeon XPRESS 200 5954 (PCIE)" -"0x5955","RS480_5955","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5955 (PCIE)" -"0x5960","RV280_5960","RV280",,,,,,"ATI Radeon 9250 5960 (AGP)" -"0x5961","RV280_5961","RV280",,,,,,"ATI Radeon 9200 5961 (AGP)" -"0x5962","RV280_5962","RV280",,,,,,"ATI Radeon 9200 5962 (AGP)" -"0x5964","RV280_5964","RV280",,,,,,"ATI Radeon 9200SE 5964 (AGP)" -"0x5965","RV280_5965","RV280",,,,,,"ATI FireMV 2200 (PCI)" -"0x5969","RN50_5969","RV100",,,1,,,"ATI ES1000 5969 (PCI)" -"0x5974","RS482_5974","RS400",,1,,,1,"ATI Radeon XPRESS 200 5974 (PCIE)" -"0x5975","RS485_5975","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5975 (PCIE)" -"0x5A41","RS400_5A41","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A41 (PCIE)" -"0x5A42","RS400_5A42","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A42 (PCIE)" -"0x5A61","RC410_5A61","RS400",,1,,,1,"ATI Radeon XPRESS 200 5A61 (PCIE)" -"0x5A62","RC410_5A62","RS400",1,1,,,1,"ATI Radeon XPRESS 200M 5A62 (PCIE)" -"0x5B60","RV370_5B60","RV380",,,,,,"ATI Radeon X300 (RV370) 5B60 (PCIE)" -"0x5B62","RV370_5B62","RV380",,,,,,"ATI Radeon X600 (RV370) 5B62 (PCIE)" -"0x5B63","RV370_5B63","RV380",,,,,,"ATI Radeon X550 (RV370) 5B63 (PCIE)" -"0x5657","RV370_5657","RV380",,,,,,"ATI Radeon X550XTX (RV370) 5657 (PCIE)" -"0x5B64","RV370_5B64","RV380",,,,,,"ATI FireGL V3100 (RV370) 5B64 (PCIE)" -"0x5B65","RV370_5B65","RV380",,,,,,"ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" -"0x5C61","RV280_5C61","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" -"0x5C63","RV280_5C63","RV280",1,,,,,"ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" -"0x5D48","R430_5D48","R420",1,,,,,"ATI Mobility Radeon X800 XT (M28) (PCIE)" -"0x5D49","R430_5D49","R420",1,,,,,"ATI Mobility FireGL V5100 (M28) (PCIE)" -"0x5D4A","R430_5D4A","R420",1,,,,,"ATI Mobility Radeon X800 (M28) (PCIE)" -"0x5D4C","R480_5D4C","R420",,,,,,"ATI Radeon X850 5D4C (PCIE)" -"0x5D4D","R480_5D4D","R420",,,,,,"ATI Radeon X850 XT PE (R480) (PCIE)" -"0x5D4E","R480_5D4E","R420",,,,,,"ATI Radeon X850 SE (R480) (PCIE)" -"0x5D4F","R480_5D4F","R420",,,,,,"ATI Radeon X850 PRO (R480) (PCIE)" -"0x5D50","R480_5D50","R420",,,,,,"ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" -"0x5D52","R480_5D52","R420",,,,,,"ATI Radeon X850 XT (R480) (PCIE)" -"0x5D57","R423_5D57","R420",,,,,,"ATI Radeon X800XT (R423) 5D57 (PCIE)" -"0x5E48","RV410_5E48","RV410",,,,,,"ATI FireGL V5000 (RV410) (PCIE)" -"0x5E4A","RV410_5E4A","RV410",,,,,,"ATI Radeon X700 XT (RV410) (PCIE)" -"0x5E4B","RV410_5E4B","RV410",,,,,,"ATI Radeon X700 PRO (RV410) (PCIE)" -"0x5E4C","RV410_5E4C","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" -"0x5E4D","RV410_5E4D","RV410",,,,,,"ATI Radeon X700 (RV410) (PCIE)" -"0x5E4F","RV410_5E4F","RV410",,,,,,"ATI Radeon X700 SE (RV410) (PCIE)" -"0x7100","R520_7100","R520",,,,,,"ATI Radeon X1800" -"0x7101","R520_7101","R520",1,,,,,"ATI Mobility Radeon X1800 XT" -"0x7102","R520_7102","R520",1,,,,,"ATI Mobility Radeon X1800" -"0x7103","R520_7103","R520",1,,,,,"ATI Mobility FireGL V7200" -"0x7104","R520_7104","R520",,,,,,"ATI FireGL V7200" -"0x7105","R520_7105","R520",,,,,,"ATI FireGL V5300" -"0x7106","R520_7106","R520",1,,,,,"ATI Mobility FireGL V7100" -"0x7108","R520_7108","R520",,,,,,"ATI Radeon X1800" -"0x7109","R520_7109","R520",,,,,,"ATI Radeon X1800" -"0x710A","R520_710A","R520",,,,,,"ATI Radeon X1800" -"0x710B","R520_710B","R520",,,,,,"ATI Radeon X1800" -"0x710C","R520_710C","R520",,,,,,"ATI Radeon X1800" -"0x710E","R520_710E","R520",,,,,,"ATI FireGL V7300" -"0x710F","R520_710F","R520",,,,,,"ATI FireGL V7350" -"0x7140","RV515_7140","RV515",,,,,,"ATI Radeon X1600" -"0x7141","RV515_7141","RV515",,,,,,"ATI RV505" -"0x7142","RV515_7142","RV515",,,,,,"ATI Radeon X1300/X1550" -"0x7143","RV515_7143","RV515",,,,,,"ATI Radeon X1550" -"0x7144","RV515_7144","RV515",1,,,,,"ATI M54-GL" -"0x7145","RV515_7145","RV515",1,,,,,"ATI Mobility Radeon X1400" -"0x7146","RV515_7146","RV515",,,,,,"ATI Radeon X1300/X1550" -"0x7147","RV515_7147","RV515",,,,,,"ATI Radeon X1550 64-bit" -"0x7149","RV515_7149","RV515",1,,,,,"ATI Mobility Radeon X1300" -"0x714A","RV515_714A","RV515",1,,,,,"ATI Mobility Radeon X1300" -"0x714B","RV515_714B","RV515",1,,,,,"ATI Mobility Radeon X1300" -"0x714C","RV515_714C","RV515",1,,,,,"ATI Mobility Radeon X1300" -"0x714D","RV515_714D","RV515",,,,,,"ATI Radeon X1300" -"0x714E","RV515_714E","RV515",,,,,,"ATI Radeon X1300" -"0x714F","RV515_714F","RV515",,,,,,"ATI RV505" -"0x7151","RV515_7151","RV515",,,,,,"ATI RV505" -"0x7152","RV515_7152","RV515",,,,,,"ATI FireGL V3300" -"0x7153","RV515_7153","RV515",,,,,,"ATI FireGL V3350" -"0x715E","RV515_715E","RV515",,,,,,"ATI Radeon X1300" -"0x715F","RV515_715F","RV515",,,,,,"ATI Radeon X1550 64-bit" -"0x7180","RV515_7180","RV515",,,,,,"ATI Radeon X1300/X1550" -"0x7181","RV515_7181","RV515",,,,,,"ATI Radeon X1600" -"0x7183","RV515_7183","RV515",,,,,,"ATI Radeon X1300/X1550" -"0x7186","RV515_7186","RV515",1,,,,,"ATI Mobility Radeon X1450" -"0x7187","RV515_7187","RV515",,,,,,"ATI Radeon X1300/X1550" -"0x7188","RV515_7188","RV515",1,,,,,"ATI Mobility Radeon X2300" -"0x718A","RV515_718A","RV515",1,,,,,"ATI Mobility Radeon X2300" -"0x718B","RV515_718B","RV515",1,,,,,"ATI Mobility Radeon X1350" -"0x718C","RV515_718C","RV515",1,,,,,"ATI Mobility Radeon X1350" -"0x718D","RV515_718D","RV515",1,,,,,"ATI Mobility Radeon X1450" -"0x718F","RV515_718F","RV515",,,,,,"ATI Radeon X1300" -"0x7193","RV515_7193","RV515",,,,,,"ATI Radeon X1550" -"0x7196","RV515_7196","RV515",1,,,,,"ATI Mobility Radeon X1350" -"0x719B","RV515_719B","RV515",,,,,,"ATI FireMV 2250" -"0x719F","RV515_719F","RV515",,,,,,"ATI Radeon X1550 64-bit" -"0x71C0","RV530_71C0","RV530",,,,,,"ATI Radeon X1600" -"0x71C1","RV530_71C1","RV530",,,,,,"ATI Radeon X1650" -"0x71C2","RV530_71C2","RV530",,,,,,"ATI Radeon X1600" -"0x71C3","RV530_71C3","RV530",,,,,,"ATI Radeon X1600" -"0x71C4","RV530_71C4","RV530",1,,,,,"ATI Mobility FireGL V5200" -"0x71C5","RV530_71C5","RV530",1,,,,,"ATI Mobility Radeon X1600" -"0x71C6","RV530_71C6","RV530",,,,,,"ATI Radeon X1650" -"0x71C7","RV530_71C7","RV530",,,,,,"ATI Radeon X1650" -"0x71CD","RV530_71CD","RV530",,,,,,"ATI Radeon X1600" -"0x71CE","RV530_71CE","RV530",,,,,,"ATI Radeon X1300 XT/X1600 Pro" -"0x71D2","RV530_71D2","RV530",,,,,,"ATI FireGL V3400" -"0x71D4","RV530_71D4","RV530",1,,,,,"ATI Mobility FireGL V5250" -"0x71D5","RV530_71D5","RV530",1,,,,,"ATI Mobility Radeon X1700" -"0x71D6","RV530_71D6","RV530",1,,,,,"ATI Mobility Radeon X1700 XT" -"0x71DA","RV530_71DA","RV530",,,,,,"ATI FireGL V5200" -"0x71DE","RV530_71DE","RV530",1,,,,,"ATI Mobility Radeon X1700" -"0x7200","RV530_7200","RV530",,,,,,"ATI Radeon X2300HD" -"0x7210","RV530_7210","RV530",1,,,,,"ATI Mobility Radeon HD 2300" -"0x7211","RV530_7211","RV530",1,,,,,"ATI Mobility Radeon HD 2300" -"0x7240","R580_7240","R580",,,,,,"ATI Radeon X1950" -"0x7243","R580_7243","R580",,,,,,"ATI Radeon X1900" -"0x7244","R580_7244","R580",,,,,,"ATI Radeon X1950" -"0x7245","R580_7245","R580",,,,,,"ATI Radeon X1900" -"0x7246","R580_7246","R580",,,,,,"ATI Radeon X1900" -"0x7247","R580_7247","R580",,,,,,"ATI Radeon X1900" -"0x7248","R580_7248","R580",,,,,,"ATI Radeon X1900" -"0x7249","R580_7249","R580",,,,,,"ATI Radeon X1900" -"0x724A","R580_724A","R580",,,,,,"ATI Radeon X1900" -"0x724B","R580_724B","R580",,,,,,"ATI Radeon X1900" -"0x724C","R580_724C","R580",,,,,,"ATI Radeon X1900" -"0x724D","R580_724D","R580",,,,,,"ATI Radeon X1900" -"0x724E","R580_724E","R580",,,,,,"ATI AMD Stream Processor" -"0x724F","R580_724F","R580",,,,,,"ATI Radeon X1900" -"0x7280","RV570_7280","RV570",,,,,,"ATI Radeon X1950" -"0x7281","RV560_7281","RV560",,,,,,"ATI RV560" -"0x7283","RV560_7283","RV560",,,,,,"ATI RV560" -"0x7284","R580_7284","R580",1,,,,,"ATI Mobility Radeon X1900" -"0x7287","RV560_7287","RV560",,,,,,"ATI RV560" -"0x7288","RV570_7288","RV570",,,,,,"ATI Radeon X1950 GT" -"0x7289","RV570_7289","RV570",,,,,,"ATI RV570" -"0x728B","RV570_728B","RV570",,,,,,"ATI RV570" -"0x728C","RV570_728C","RV570",,,,,,"ATI ATI FireGL V7400" -"0x7290","RV560_7290","RV560",,,,,,"ATI RV560" -"0x7291","RV560_7291","RV560",,,,,,"ATI Radeon X1650" -"0x7293","RV560_7293","RV560",,,,,,"ATI Radeon X1650" -"0x7297","RV560_7297","RV560",,,,,,"ATI RV560" -"0x7834","RS350_7834","RS300",,1,,,1,"ATI Radeon 9100 PRO IGP 7834" -"0x7835","RS350_7835","RS300",1,1,,,1,"ATI Radeon Mobility 9200 IGP 7835" -"0x791E","RS690_791E","RS690",,1,,,1,"ATI Radeon X1200" -"0x791F","RS690_791F","RS690",,1,,,1,"ATI Radeon X1200" -"0x796C","RS740_796C","RS740",,1,,,1,"ATI RS740" -"0x796D","RS740_796D","RS740",,1,,,1,"ATI RS740M" -"0x796E","RS740_796E","RS740",,1,,,1,"ATI RS740" -"0x796F","RS740_796F","RS740",,1,,,1,"ATI RS740M" -"0x9400","R600_9400","R600",,,,,,"ATI Radeon HD 2900 XT" -"0x9401","R600_9401","R600",,,,,,"ATI Radeon HD 2900 XT" -"0x9402","R600_9402","R600",,,,,,"ATI Radeon HD 2900 XT" -"0x9403","R600_9403","R600",,,,,,"ATI Radeon HD 2900 Pro" -"0x9405","R600_9405","R600",,,,,,"ATI Radeon HD 2900 GT" -"0x940A","R600_940A","R600",,,,,,"ATI FireGL V8650" -"0x940B","R600_940B","R600",,,,,,"ATI FireGL V8600" -"0x940F","R600_940F","R600",,,,,,"ATI FireGL V7600" -"0x94C0","RV610_94C0","RV610",,,,,,"ATI RV610" -"0x94C1","RV610_94C1","RV610",,,,,,"ATI Radeon HD 2400 XT" -"0x94C3","RV610_94C3","RV610",,,,,,"ATI Radeon HD 2400 Pro" -"0x94C4","RV610_94C4","RV610",,,,,,"ATI ATI Radeon HD 2400 PRO AGP" -"0x94C5","RV610_94C5","RV610",,,,,,"ATI FireGL V4000" -"0x94C6","RV610_94C6","RV610",,,,,,"ATI RV610" -"0x94C7","RV610_94C7","RV610",,,,,,"ATI ATI Radeon HD 2350" -"0x94C8","RV610_94C8","RV610",1,,,,,"ATI Mobility Radeon HD 2400 XT" -"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400" -"0x94CB","RV610_94CB","RV610",1,,,,,"ATI ATI RADEON E2400" -"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610" -"0x9500","RV670_9500","RV670",,,,,,"ATI RV670" -"0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870" -"0x9505","RV670_9505","RV670",,,,,,"ATI Radeon HD3850" -"0x9507","RV670_9507","RV670",,,,,,"ATI RV670" -"0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2" -"0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700" -"0x9580","RV630_9580","RV630",,,,,,"ATI RV630" -"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600" -"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT" -"0x9586","RV630_9586","RV630",,,,,,"ATI ATI Radeon HD 2600 XT AGP" -"0x9587","RV630_9587","RV630",,,,,,"ATI ATI Radeon HD 2600 Pro AGP" -"0x9588","RV630_9588","RV630",,,,,,"ATI Radeon HD 2600 XT" -"0x9589","RV630_9589","RV630",,,,,,"ATI Radeon HD 2600 Pro" -"0x958A","RV630_958A","RV630",,,,,,"ATI Gemini RV630" -"0x958B","RV630_958B","RV630",1,,,,,"ATI Gemini ATI Mobility Radeon HD 2600 XT" -"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600" -"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600" -"0x958E","RV630_958E","RV630",,,,,,"ATI ATI Radeon HD 2600 LE" diff --git a/src/pcidb/parse_pci_ids.pl b/src/pcidb/parse_pci_ids.pl deleted file mode 100755 index a3a8af8..0000000 --- a/src/pcidb/parse_pci_ids.pl +++ /dev/null @@ -1,102 +0,0 @@ -#!/usr/bin/perl -# -# Copyright 2007 Red Hat Inc. -# This crappy script written by Dave Airlie to avoid hassle of adding -# ids in every place. -# -use strict; -use warnings; -use Text::CSV_XS; - -my $file = $ARGV[0]; - -my $atioutfile = 'ati_pciids_gen.h'; -my $radeonpcichipsetfile = 'radeon_pci_chipset_gen.h'; -my $radeonpcidevicematchfile = 'radeon_pci_device_match_gen.h'; -my $radeonchipsetfile = 'radeon_chipset_gen.h'; -my $radeonchipinfofile = 'radeon_chipinfo_gen.h'; - -my $csv = Text::CSV_XS->new(); - -open (CSV, "<", $file) or die $!; - -open (ATIOUT, ">", $atioutfile) or die; -open (PCICHIPSET, ">", $radeonpcichipsetfile) or die; -open (PCIDEVICEMATCH, ">", $radeonpcidevicematchfile) or die; -open (RADEONCHIPSET, ">", $radeonchipsetfile) or die; -open (RADEONCHIPINFO, ">", $radeonchipinfofile) or die; - -print RADEONCHIPSET "/* This file is autogenerated please do not edit */\n"; -print RADEONCHIPSET "static SymTabRec RADEONChipsets[] = {\n"; -print PCICHIPSET "/* This file is autogenerated please do not edit */\n"; -print PCICHIPSET "PciChipsets RADEONPciChipsets[] = {\n"; -print PCIDEVICEMATCH "/* This file is autogenerated please do not edit */\n"; -print PCIDEVICEMATCH "static const struct pci_id_match radeon_device_match[] = {\n"; -print RADEONCHIPINFO "/* This file is autogenerated please do not edit */\n"; -print RADEONCHIPINFO "RADEONCardInfo RADEONCards[] = {\n"; -while (<CSV>) { - if ($csv->parse($_)) { - my @columns = $csv->fields(); - - if ((substr($columns[0], 0, 1) ne "#")) { - - print ATIOUT "#define PCI_CHIP_$columns[1] $columns[0]\n"; - - if (($columns[2] ne "R128") && ($columns[2] ne "MACH64") && ($columns[2] ne "MACH32")) { - print PCICHIPSET " { PCI_CHIP_$columns[1], PCI_CHIP_$columns[1], RES_SHARED_VGA },\n"; - - print PCIDEVICEMATCH " ATI_DEVICE_MATCH( PCI_CHIP_$columns[1], 0 ),\n"; - - print RADEONCHIPSET " { PCI_CHIP_$columns[1], \"$columns[8]\" },\n"; - - print RADEONCHIPINFO " { $columns[0], CHIP_FAMILY_$columns[2], "; - - if ($columns[3] eq "1") { - print RADEONCHIPINFO "1, "; - } else { - print RADEONCHIPINFO "0, "; - } - - if ($columns[4] eq "1") { - print RADEONCHIPINFO "1, "; - } else { - print RADEONCHIPINFO "0, "; - } - - if ($columns[5] eq "1") { - print RADEONCHIPINFO "1, "; - } else { - print RADEONCHIPINFO "0, "; - } - - if ($columns[6] eq "1") { - print RADEONCHIPINFO "1, "; - } else { - print RADEONCHIPINFO "0, "; - } - - if ($columns[7] eq "1") { - print RADEONCHIPINFO "1 "; - } else { - print RADEONCHIPINFO "0 "; - } - - print RADEONCHIPINFO "},\n"; - } - } - } else { - my $err = $csv->error_input; - print "Failed to parse line: $err"; - } -} - -print RADEONCHIPINFO "};\n"; -print RADEONCHIPSET " { -1, NULL }\n};\n"; -print PCICHIPSET " { -1, -1, RES_UNDEFINED }\n};\n"; -print PCIDEVICEMATCH " { 0, 0, 0 }\n};\n"; -close CSV; -close ATIOUT; -close PCICHIPSET; -close PCIDEVICEMATCH; -close RADEONCHIPSET; -close RADEONCHIPINFO; diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h deleted file mode 100644 index 420f5d8..0000000 --- a/src/radeon_chipinfo_gen.h +++ /dev/null @@ -1,279 +0,0 @@ -/* This file is autogenerated please do not edit */ -RADEONCardInfo RADEONCards[] = { - { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 1 }, - { 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 }, - { 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, - { 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, - { 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, - { 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, - { 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, - { 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, - { 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, - { 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 }, - { 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, - { 0x4243, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, - { 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 1 }, - { 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 }, - { 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 }, - { 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, - { 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, - { 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, - { 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, - { 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, - { 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, - { 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, - { 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, - { 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, - { 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, - { 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, - { 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, - { 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, - { 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, - { 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, - { 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, - { 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, - { 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, - { 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, - { 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, - { 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, - { 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, - { 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, - { 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, - { 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, - { 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, - { 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, - { 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, - { 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, - { 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, - { 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, - { 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, - { 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, - { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, - { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, - { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, - { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, - { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, - { 0x5954, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, - { 0x5955, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, - { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, - { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, - { 0x5974, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, - { 0x5975, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, - { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, - { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, - { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, - { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, - { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5657, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, - { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, - { 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, - { 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, - { 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, - { 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, - { 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, - { 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, - { 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, - { 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, - { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, - { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, - { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, - { 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, - { 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, - { 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, - { 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, - { 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, - { 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, - { 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, - { 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x7200, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, - { 0x7210, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x7211, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, - { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, - { 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, - { 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, - { 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, - { 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 }, - { 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, - { 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, - { 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, - { 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, - { 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, - { 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, - { 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, - { 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, - { 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, - { 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, - { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, - { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, - { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, - { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, - { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, - { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, - { 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, - { 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, - { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, - { 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, - { 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, - { 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, - { 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, - { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, - { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, - { 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, - { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, - { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, -}; diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h deleted file mode 100644 index e6890be..0000000 --- a/src/radeon_chipset_gen.h +++ /dev/null @@ -1,280 +0,0 @@ -/* This file is autogenerated please do not edit */ -static SymTabRec RADEONChipsets[] = { - { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, - { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, - { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, - { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, - { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" }, - { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" }, - { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" }, - { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, - { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, - { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, - { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, - { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, - { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, - { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, - { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, - { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, - { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, - { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, - { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, - { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, - { PCI_CHIP_RV350_4155, "ATI Radeon 9650" }, - { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, - { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" }, - { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" }, - { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" }, - { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" }, - { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" }, - { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, - { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" }, - { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" }, - { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" }, - { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" }, - { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" }, - { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" }, - { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" }, - { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" }, - { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" }, - { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" }, - { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" }, - { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" }, - { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" }, - { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" }, - { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" }, - { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, - { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, - { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, - { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" }, - { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" }, - { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" }, - { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" }, - { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" }, - { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" }, - { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" }, - { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" }, - { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, - { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, - { PCI_CHIP_R360_NJ, "ATI FireGL X2 NK (AGP)" }, - { PCI_CHIP_R350_NK, "ATI Radeon 9800XT NJ (AGP)" }, - { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" }, - { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, - { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, - { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, - { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, - { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" }, - { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" }, - { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, - { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, - { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, - { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, - { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, - { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, - { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, - { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, - { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, - { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, - { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" }, - { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" }, - { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" }, - { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" }, - { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" }, - { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" }, - { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" }, - { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" }, - { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" }, - { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" }, - { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" }, - { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" }, - { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" }, - { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" }, - { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" }, - { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" }, - { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, - { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, - { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, - { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, - { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, - { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, - { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, - { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, - { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" }, - { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" }, - { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, - { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, - { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, - { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" }, - { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" }, - { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" }, - { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" }, - { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" }, - { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" }, - { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" }, - { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" }, - { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, - { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, - { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, - { PCI_CHIP_RV370_5657, "ATI Radeon X550XTX (RV370) 5657 (PCIE)" }, - { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, - { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, - { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, - { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, - { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" }, - { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" }, - { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" }, - { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" }, - { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" }, - { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" }, - { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" }, - { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" }, - { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" }, - { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" }, - { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" }, - { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" }, - { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" }, - { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, - { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, - { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, - { PCI_CHIP_R520_7100, "ATI Radeon X1800" }, - { PCI_CHIP_R520_7101, "ATI Mobility Radeon X1800 XT" }, - { PCI_CHIP_R520_7102, "ATI Mobility Radeon X1800" }, - { PCI_CHIP_R520_7103, "ATI Mobility FireGL V7200" }, - { PCI_CHIP_R520_7104, "ATI FireGL V7200" }, - { PCI_CHIP_R520_7105, "ATI FireGL V5300" }, - { PCI_CHIP_R520_7106, "ATI Mobility FireGL V7100" }, - { PCI_CHIP_R520_7108, "ATI Radeon X1800" }, - { PCI_CHIP_R520_7109, "ATI Radeon X1800" }, - { PCI_CHIP_R520_710A, "ATI Radeon X1800" }, - { PCI_CHIP_R520_710B, "ATI Radeon X1800" }, - { PCI_CHIP_R520_710C, "ATI Radeon X1800" }, - { PCI_CHIP_R520_710E, "ATI FireGL V7300" }, - { PCI_CHIP_R520_710F, "ATI FireGL V7350" }, - { PCI_CHIP_RV515_7140, "ATI Radeon X1600" }, - { PCI_CHIP_RV515_7141, "ATI RV505" }, - { PCI_CHIP_RV515_7142, "ATI Radeon X1300/X1550" }, - { PCI_CHIP_RV515_7143, "ATI Radeon X1550" }, - { PCI_CHIP_RV515_7144, "ATI M54-GL" }, - { PCI_CHIP_RV515_7145, "ATI Mobility Radeon X1400" }, - { PCI_CHIP_RV515_7146, "ATI Radeon X1300/X1550" }, - { PCI_CHIP_RV515_7147, "ATI Radeon X1550 64-bit" }, - { PCI_CHIP_RV515_7149, "ATI Mobility Radeon X1300" }, - { PCI_CHIP_RV515_714A, "ATI Mobility Radeon X1300" }, - { PCI_CHIP_RV515_714B, "ATI Mobility Radeon X1300" }, - { PCI_CHIP_RV515_714C, "ATI Mobility Radeon X1300" }, - { PCI_CHIP_RV515_714D, "ATI Radeon X1300" }, - { PCI_CHIP_RV515_714E, "ATI Radeon X1300" }, - { PCI_CHIP_RV515_714F, "ATI RV505" }, - { PCI_CHIP_RV515_7151, "ATI RV505" }, - { PCI_CHIP_RV515_7152, "ATI FireGL V3300" }, - { PCI_CHIP_RV515_7153, "ATI FireGL V3350" }, - { PCI_CHIP_RV515_715E, "ATI Radeon X1300" }, - { PCI_CHIP_RV515_715F, "ATI Radeon X1550 64-bit" }, - { PCI_CHIP_RV515_7180, "ATI Radeon X1300/X1550" }, - { PCI_CHIP_RV515_7181, "ATI Radeon X1600" }, - { PCI_CHIP_RV515_7183, "ATI Radeon X1300/X1550" }, - { PCI_CHIP_RV515_7186, "ATI Mobility Radeon X1450" }, - { PCI_CHIP_RV515_7187, "ATI Radeon X1300/X1550" }, - { PCI_CHIP_RV515_7188, "ATI Mobility Radeon X2300" }, - { PCI_CHIP_RV515_718A, "ATI Mobility Radeon X2300" }, - { PCI_CHIP_RV515_718B, "ATI Mobility Radeon X1350" }, - { PCI_CHIP_RV515_718C, "ATI Mobility Radeon X1350" }, - { PCI_CHIP_RV515_718D, "ATI Mobility Radeon X1450" }, - { PCI_CHIP_RV515_718F, "ATI Radeon X1300" }, - { PCI_CHIP_RV515_7193, "ATI Radeon X1550" }, - { PCI_CHIP_RV515_7196, "ATI Mobility Radeon X1350" }, - { PCI_CHIP_RV515_719B, "ATI FireMV 2250" }, - { PCI_CHIP_RV515_719F, "ATI Radeon X1550 64-bit" }, - { PCI_CHIP_RV530_71C0, "ATI Radeon X1600" }, - { PCI_CHIP_RV530_71C1, "ATI Radeon X1650" }, - { PCI_CHIP_RV530_71C2, "ATI Radeon X1600" }, - { PCI_CHIP_RV530_71C3, "ATI Radeon X1600" }, - { PCI_CHIP_RV530_71C4, "ATI Mobility FireGL V5200" }, - { PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" }, - { PCI_CHIP_RV530_71C6, "ATI Radeon X1650" }, - { PCI_CHIP_RV530_71C7, "ATI Radeon X1650" }, - { PCI_CHIP_RV530_71CD, "ATI Radeon X1600" }, - { PCI_CHIP_RV530_71CE, "ATI Radeon X1300 XT/X1600 Pro" }, - { PCI_CHIP_RV530_71D2, "ATI FireGL V3400" }, - { PCI_CHIP_RV530_71D4, "ATI Mobility FireGL V5250" }, - { PCI_CHIP_RV530_71D5, "ATI Mobility Radeon X1700" }, - { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" }, - { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" }, - { PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" }, - { PCI_CHIP_RV530_7200, "ATI Radeon X2300HD" }, - { PCI_CHIP_RV530_7210, "ATI Mobility Radeon HD 2300" }, - { PCI_CHIP_RV530_7211, "ATI Mobility Radeon HD 2300" }, - { PCI_CHIP_R580_7240, "ATI Radeon X1950" }, - { PCI_CHIP_R580_7243, "ATI Radeon X1900" }, - { PCI_CHIP_R580_7244, "ATI Radeon X1950" }, - { PCI_CHIP_R580_7245, "ATI Radeon X1900" }, - { PCI_CHIP_R580_7246, "ATI Radeon X1900" }, - { PCI_CHIP_R580_7247, "ATI Radeon X1900" }, - { PCI_CHIP_R580_7248, "ATI Radeon X1900" }, - { PCI_CHIP_R580_7249, "ATI Radeon X1900" }, - { PCI_CHIP_R580_724A, "ATI Radeon X1900" }, - { PCI_CHIP_R580_724B, "ATI Radeon X1900" }, - { PCI_CHIP_R580_724C, "ATI Radeon X1900" }, - { PCI_CHIP_R580_724D, "ATI Radeon X1900" }, - { PCI_CHIP_R580_724E, "ATI AMD Stream Processor" }, - { PCI_CHIP_R580_724F, "ATI Radeon X1900" }, - { PCI_CHIP_RV570_7280, "ATI Radeon X1950" }, - { PCI_CHIP_RV560_7281, "ATI RV560" }, - { PCI_CHIP_RV560_7283, "ATI RV560" }, - { PCI_CHIP_R580_7284, "ATI Mobility Radeon X1900" }, - { PCI_CHIP_RV560_7287, "ATI RV560" }, - { PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" }, - { PCI_CHIP_RV570_7289, "ATI RV570" }, - { PCI_CHIP_RV570_728B, "ATI RV570" }, - { PCI_CHIP_RV570_728C, "ATI ATI FireGL V7400" }, - { PCI_CHIP_RV560_7290, "ATI RV560" }, - { PCI_CHIP_RV560_7291, "ATI Radeon X1650" }, - { PCI_CHIP_RV560_7293, "ATI Radeon X1650" }, - { PCI_CHIP_RV560_7297, "ATI RV560" }, - { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" }, - { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, - { PCI_CHIP_RS690_791E, "ATI Radeon X1200" }, - { PCI_CHIP_RS690_791F, "ATI Radeon X1200" }, - { PCI_CHIP_RS740_796C, "ATI RS740" }, - { PCI_CHIP_RS740_796D, "ATI RS740M" }, - { PCI_CHIP_RS740_796E, "ATI RS740" }, - { PCI_CHIP_RS740_796F, "ATI RS740M" }, - { PCI_CHIP_R600_9400, "ATI Radeon HD 2900 XT" }, - { PCI_CHIP_R600_9401, "ATI Radeon HD 2900 XT" }, - { PCI_CHIP_R600_9402, "ATI Radeon HD 2900 XT" }, - { PCI_CHIP_R600_9403, "ATI Radeon HD 2900 Pro" }, - { PCI_CHIP_R600_9405, "ATI Radeon HD 2900 GT" }, - { PCI_CHIP_R600_940A, "ATI FireGL V8650" }, - { PCI_CHIP_R600_940B, "ATI FireGL V8600" }, - { PCI_CHIP_R600_940F, "ATI FireGL V7600" }, - { PCI_CHIP_RV610_94C0, "ATI RV610" }, - { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, - { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, - { PCI_CHIP_RV610_94C4, "ATI ATI Radeon HD 2400 PRO AGP" }, - { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" }, - { PCI_CHIP_RV610_94C6, "ATI RV610" }, - { PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" }, - { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" }, - { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" }, - { PCI_CHIP_RV610_94CB, "ATI ATI RADEON E2400" }, - { PCI_CHIP_RV610_94CC, "ATI RV610" }, - { PCI_CHIP_RV670_9500, "ATI RV670" }, - { PCI_CHIP_RV670_9501, "ATI Radeon HD3870" }, - { PCI_CHIP_RV670_9505, "ATI Radeon HD3850" }, - { PCI_CHIP_RV670_9507, "ATI RV670" }, - { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, - { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, - { PCI_CHIP_RV630_9580, "ATI RV630" }, - { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, - { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, - { PCI_CHIP_RV630_9586, "ATI ATI Radeon HD 2600 XT AGP" }, - { PCI_CHIP_RV630_9587, "ATI ATI Radeon HD 2600 Pro AGP" }, - { PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" }, - { PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" }, - { PCI_CHIP_RV630_958A, "ATI Gemini RV630" }, - { PCI_CHIP_RV630_958B, "ATI Gemini ATI Mobility Radeon HD 2600 XT" }, - { PCI_CHIP_RV630_958C, "ATI FireGL V5600" }, - { PCI_CHIP_RV630_958D, "ATI FireGL V3600" }, - { PCI_CHIP_RV630_958E, "ATI ATI Radeon HD 2600 LE" }, - { -1, NULL } -}; diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h deleted file mode 100644 index ab6b62a..0000000 --- a/src/radeon_pci_chipset_gen.h +++ /dev/null @@ -1,280 +0,0 @@ -/* This file is autogenerated please do not edit */ -PciChipsets RADEONPciChipsets[] = { - { PCI_CHIP_RV380_3150, PCI_CHIP_RV380_3150, RES_SHARED_VGA }, - { PCI_CHIP_RV380_3152, PCI_CHIP_RV380_3152, RES_SHARED_VGA }, - { PCI_CHIP_RV380_3154, PCI_CHIP_RV380_3154, RES_SHARED_VGA }, - { PCI_CHIP_RV380_3E50, PCI_CHIP_RV380_3E50, RES_SHARED_VGA }, - { PCI_CHIP_RV380_3E54, PCI_CHIP_RV380_3E54, RES_SHARED_VGA }, - { PCI_CHIP_RS100_4136, PCI_CHIP_RS100_4136, RES_SHARED_VGA }, - { PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA }, - { PCI_CHIP_R300_AD, PCI_CHIP_R300_AD, RES_SHARED_VGA }, - { PCI_CHIP_R300_AE, PCI_CHIP_R300_AE, RES_SHARED_VGA }, - { PCI_CHIP_R300_AF, PCI_CHIP_R300_AF, RES_SHARED_VGA }, - { PCI_CHIP_R300_AG, PCI_CHIP_R300_AG, RES_SHARED_VGA }, - { PCI_CHIP_R350_AH, PCI_CHIP_R350_AH, RES_SHARED_VGA }, - { PCI_CHIP_R350_AI, PCI_CHIP_R350_AI, RES_SHARED_VGA }, - { PCI_CHIP_R350_AJ, PCI_CHIP_R350_AJ, RES_SHARED_VGA }, - { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AQ, PCI_CHIP_RV350_AQ, RES_SHARED_VGA }, - { PCI_CHIP_RV360_AR, PCI_CHIP_RV360_AR, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AS, PCI_CHIP_RV350_AS, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AT, PCI_CHIP_RV350_AT, RES_SHARED_VGA }, - { PCI_CHIP_RV350_4155, PCI_CHIP_RV350_4155, RES_SHARED_VGA }, - { PCI_CHIP_RV350_AV, PCI_CHIP_RV350_AV, RES_SHARED_VGA }, - { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA }, - { PCI_CHIP_R200_BB, PCI_CHIP_R200_BB, RES_SHARED_VGA }, - { PCI_CHIP_R200_BC, PCI_CHIP_R200_BC, RES_SHARED_VGA }, - { PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA }, - { PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA }, - { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA }, - { PCI_CHIP_RV250_If, PCI_CHIP_RV250_If, RES_SHARED_VGA }, - { PCI_CHIP_RV250_Ig, PCI_CHIP_RV250_Ig, RES_SHARED_VGA }, - { PCI_CHIP_R420_JH, PCI_CHIP_R420_JH, RES_SHARED_VGA }, - { PCI_CHIP_R420_JI, PCI_CHIP_R420_JI, RES_SHARED_VGA }, - { PCI_CHIP_R420_JJ, PCI_CHIP_R420_JJ, RES_SHARED_VGA }, - { PCI_CHIP_R420_JK, PCI_CHIP_R420_JK, RES_SHARED_VGA }, - { PCI_CHIP_R420_JL, PCI_CHIP_R420_JL, RES_SHARED_VGA }, - { PCI_CHIP_R420_JM, PCI_CHIP_R420_JM, RES_SHARED_VGA }, - { PCI_CHIP_R420_JN, PCI_CHIP_R420_JN, RES_SHARED_VGA }, - { PCI_CHIP_R420_4A4F, PCI_CHIP_R420_4A4F, RES_SHARED_VGA }, - { PCI_CHIP_R420_JP, PCI_CHIP_R420_JP, RES_SHARED_VGA }, - { PCI_CHIP_R481_4B49, PCI_CHIP_R481_4B49, RES_SHARED_VGA }, - { PCI_CHIP_R481_4B4A, PCI_CHIP_R481_4B4A, RES_SHARED_VGA }, - { PCI_CHIP_R481_4B4B, PCI_CHIP_R481_4B4B, RES_SHARED_VGA }, - { PCI_CHIP_R481_4B4C, PCI_CHIP_R481_4B4C, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LW, PCI_CHIP_RADEON_LW, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LX, PCI_CHIP_RADEON_LX, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LY, PCI_CHIP_RADEON_LY, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_LZ, PCI_CHIP_RADEON_LZ, RES_SHARED_VGA }, - { PCI_CHIP_RV250_Ld, PCI_CHIP_RV250_Ld, RES_SHARED_VGA }, - { PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA }, - { PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA }, - { PCI_CHIP_R300_ND, PCI_CHIP_R300_ND, RES_SHARED_VGA }, - { PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA }, - { PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA }, - { PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA }, - { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA }, - { PCI_CHIP_R350_NI, PCI_CHIP_R350_NI, RES_SHARED_VGA }, - { PCI_CHIP_R360_NJ, PCI_CHIP_R360_NJ, RES_SHARED_VGA }, - { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NQ, PCI_CHIP_RV350_NQ, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NR, PCI_CHIP_RV350_NR, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NS, PCI_CHIP_RV350_NS, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NT, PCI_CHIP_RV350_NT, RES_SHARED_VGA }, - { PCI_CHIP_RV350_NV, PCI_CHIP_RV350_NV, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_QD, PCI_CHIP_RADEON_QD, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_QE, PCI_CHIP_RADEON_QE, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_QF, PCI_CHIP_RADEON_QF, RES_SHARED_VGA }, - { PCI_CHIP_RADEON_QG, PCI_CHIP_RADEON_QG, RES_SHARED_VGA }, - { PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA }, - { PCI_CHIP_R200_QL, PCI_CHIP_R200_QL, RES_SHARED_VGA }, - { PCI_CHIP_R200_QM, PCI_CHIP_R200_QM, RES_SHARED_VGA }, - { PCI_CHIP_RV200_QW, PCI_CHIP_RV200_QW, RES_SHARED_VGA }, - { PCI_CHIP_RV200_QX, PCI_CHIP_RV200_QX, RES_SHARED_VGA }, - { PCI_CHIP_RV100_QY, PCI_CHIP_RV100_QY, RES_SHARED_VGA }, - { PCI_CHIP_RV100_QZ, PCI_CHIP_RV100_QZ, RES_SHARED_VGA }, - { PCI_CHIP_RN50_515E, PCI_CHIP_RN50_515E, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5460, PCI_CHIP_RV370_5460, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5462, PCI_CHIP_RV370_5462, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5464, PCI_CHIP_RV370_5464, RES_SHARED_VGA }, - { PCI_CHIP_R423_UH, PCI_CHIP_R423_UH, RES_SHARED_VGA }, - { PCI_CHIP_R423_UI, PCI_CHIP_R423_UI, RES_SHARED_VGA }, - { PCI_CHIP_R423_UJ, PCI_CHIP_R423_UJ, RES_SHARED_VGA }, - { PCI_CHIP_R423_UK, PCI_CHIP_R423_UK, RES_SHARED_VGA }, - { PCI_CHIP_R430_554C, PCI_CHIP_R430_554C, RES_SHARED_VGA }, - { PCI_CHIP_R430_554D, PCI_CHIP_R430_554D, RES_SHARED_VGA }, - { PCI_CHIP_R430_554E, PCI_CHIP_R430_554E, RES_SHARED_VGA }, - { PCI_CHIP_R430_554F, PCI_CHIP_R430_554F, RES_SHARED_VGA }, - { PCI_CHIP_R423_5550, PCI_CHIP_R423_5550, RES_SHARED_VGA }, - { PCI_CHIP_R423_UQ, PCI_CHIP_R423_UQ, RES_SHARED_VGA }, - { PCI_CHIP_R423_UR, PCI_CHIP_R423_UR, RES_SHARED_VGA }, - { PCI_CHIP_R423_UT, PCI_CHIP_R423_UT, RES_SHARED_VGA }, - { PCI_CHIP_RV410_564A, PCI_CHIP_RV410_564A, RES_SHARED_VGA }, - { PCI_CHIP_RV410_564B, PCI_CHIP_RV410_564B, RES_SHARED_VGA }, - { PCI_CHIP_RV410_564F, PCI_CHIP_RV410_564F, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5652, PCI_CHIP_RV410_5652, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5653, PCI_CHIP_RV410_5653, RES_SHARED_VGA }, - { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA }, - { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA }, - { PCI_CHIP_RS480_5954, PCI_CHIP_RS480_5954, RES_SHARED_VGA }, - { PCI_CHIP_RS480_5955, PCI_CHIP_RS480_5955, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5964, PCI_CHIP_RV280_5964, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5965, PCI_CHIP_RV280_5965, RES_SHARED_VGA }, - { PCI_CHIP_RN50_5969, PCI_CHIP_RN50_5969, RES_SHARED_VGA }, - { PCI_CHIP_RS482_5974, PCI_CHIP_RS482_5974, RES_SHARED_VGA }, - { PCI_CHIP_RS485_5975, PCI_CHIP_RS485_5975, RES_SHARED_VGA }, - { PCI_CHIP_RS400_5A41, PCI_CHIP_RS400_5A41, RES_SHARED_VGA }, - { PCI_CHIP_RS400_5A42, PCI_CHIP_RS400_5A42, RES_SHARED_VGA }, - { PCI_CHIP_RC410_5A61, PCI_CHIP_RC410_5A61, RES_SHARED_VGA }, - { PCI_CHIP_RC410_5A62, PCI_CHIP_RC410_5A62, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B60, PCI_CHIP_RV370_5B60, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B62, PCI_CHIP_RV370_5B62, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B63, PCI_CHIP_RV370_5B63, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5657, PCI_CHIP_RV370_5657, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B64, PCI_CHIP_RV370_5B64, RES_SHARED_VGA }, - { PCI_CHIP_RV370_5B65, PCI_CHIP_RV370_5B65, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5C61, PCI_CHIP_RV280_5C61, RES_SHARED_VGA }, - { PCI_CHIP_RV280_5C63, PCI_CHIP_RV280_5C63, RES_SHARED_VGA }, - { PCI_CHIP_R430_5D48, PCI_CHIP_R430_5D48, RES_SHARED_VGA }, - { PCI_CHIP_R430_5D49, PCI_CHIP_R430_5D49, RES_SHARED_VGA }, - { PCI_CHIP_R430_5D4A, PCI_CHIP_R430_5D4A, RES_SHARED_VGA }, - { PCI_CHIP_R480_5D4C, PCI_CHIP_R480_5D4C, RES_SHARED_VGA }, - { PCI_CHIP_R480_5D4D, PCI_CHIP_R480_5D4D, RES_SHARED_VGA }, - { PCI_CHIP_R480_5D4E, PCI_CHIP_R480_5D4E, RES_SHARED_VGA }, - { PCI_CHIP_R480_5D4F, PCI_CHIP_R480_5D4F, RES_SHARED_VGA }, - { PCI_CHIP_R480_5D50, PCI_CHIP_R480_5D50, RES_SHARED_VGA }, - { PCI_CHIP_R480_5D52, PCI_CHIP_R480_5D52, RES_SHARED_VGA }, - { PCI_CHIP_R423_5D57, PCI_CHIP_R423_5D57, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5E48, PCI_CHIP_RV410_5E48, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5E4A, PCI_CHIP_RV410_5E4A, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5E4B, PCI_CHIP_RV410_5E4B, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5E4C, PCI_CHIP_RV410_5E4C, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5E4D, PCI_CHIP_RV410_5E4D, RES_SHARED_VGA }, - { PCI_CHIP_RV410_5E4F, PCI_CHIP_RV410_5E4F, RES_SHARED_VGA }, - { PCI_CHIP_R520_7100, PCI_CHIP_R520_7100, RES_SHARED_VGA }, - { PCI_CHIP_R520_7101, PCI_CHIP_R520_7101, RES_SHARED_VGA }, - { PCI_CHIP_R520_7102, PCI_CHIP_R520_7102, RES_SHARED_VGA }, - { PCI_CHIP_R520_7103, PCI_CHIP_R520_7103, RES_SHARED_VGA }, - { PCI_CHIP_R520_7104, PCI_CHIP_R520_7104, RES_SHARED_VGA }, - { PCI_CHIP_R520_7105, PCI_CHIP_R520_7105, RES_SHARED_VGA }, - { PCI_CHIP_R520_7106, PCI_CHIP_R520_7106, RES_SHARED_VGA }, - { PCI_CHIP_R520_7108, PCI_CHIP_R520_7108, RES_SHARED_VGA }, - { PCI_CHIP_R520_7109, PCI_CHIP_R520_7109, RES_SHARED_VGA }, - { PCI_CHIP_R520_710A, PCI_CHIP_R520_710A, RES_SHARED_VGA }, - { PCI_CHIP_R520_710B, PCI_CHIP_R520_710B, RES_SHARED_VGA }, - { PCI_CHIP_R520_710C, PCI_CHIP_R520_710C, RES_SHARED_VGA }, - { PCI_CHIP_R520_710E, PCI_CHIP_R520_710E, RES_SHARED_VGA }, - { PCI_CHIP_R520_710F, PCI_CHIP_R520_710F, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7140, PCI_CHIP_RV515_7140, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7141, PCI_CHIP_RV515_7141, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7142, PCI_CHIP_RV515_7142, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7143, PCI_CHIP_RV515_7143, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7144, PCI_CHIP_RV515_7144, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7145, PCI_CHIP_RV515_7145, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7146, PCI_CHIP_RV515_7146, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7147, PCI_CHIP_RV515_7147, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7149, PCI_CHIP_RV515_7149, RES_SHARED_VGA }, - { PCI_CHIP_RV515_714A, PCI_CHIP_RV515_714A, RES_SHARED_VGA }, - { PCI_CHIP_RV515_714B, PCI_CHIP_RV515_714B, RES_SHARED_VGA }, - { PCI_CHIP_RV515_714C, PCI_CHIP_RV515_714C, RES_SHARED_VGA }, - { PCI_CHIP_RV515_714D, PCI_CHIP_RV515_714D, RES_SHARED_VGA }, - { PCI_CHIP_RV515_714E, PCI_CHIP_RV515_714E, RES_SHARED_VGA }, - { PCI_CHIP_RV515_714F, PCI_CHIP_RV515_714F, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7151, PCI_CHIP_RV515_7151, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7152, PCI_CHIP_RV515_7152, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7153, PCI_CHIP_RV515_7153, RES_SHARED_VGA }, - { PCI_CHIP_RV515_715E, PCI_CHIP_RV515_715E, RES_SHARED_VGA }, - { PCI_CHIP_RV515_715F, PCI_CHIP_RV515_715F, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7180, PCI_CHIP_RV515_7180, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7181, PCI_CHIP_RV515_7181, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7183, PCI_CHIP_RV515_7183, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7186, PCI_CHIP_RV515_7186, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7187, PCI_CHIP_RV515_7187, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7188, PCI_CHIP_RV515_7188, RES_SHARED_VGA }, - { PCI_CHIP_RV515_718A, PCI_CHIP_RV515_718A, RES_SHARED_VGA }, - { PCI_CHIP_RV515_718B, PCI_CHIP_RV515_718B, RES_SHARED_VGA }, - { PCI_CHIP_RV515_718C, PCI_CHIP_RV515_718C, RES_SHARED_VGA }, - { PCI_CHIP_RV515_718D, PCI_CHIP_RV515_718D, RES_SHARED_VGA }, - { PCI_CHIP_RV515_718F, PCI_CHIP_RV515_718F, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7193, PCI_CHIP_RV515_7193, RES_SHARED_VGA }, - { PCI_CHIP_RV515_7196, PCI_CHIP_RV515_7196, RES_SHARED_VGA }, - { PCI_CHIP_RV515_719B, PCI_CHIP_RV515_719B, RES_SHARED_VGA }, - { PCI_CHIP_RV515_719F, PCI_CHIP_RV515_719F, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C0, PCI_CHIP_RV530_71C0, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C1, PCI_CHIP_RV530_71C1, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C2, PCI_CHIP_RV530_71C2, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C3, PCI_CHIP_RV530_71C3, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C4, PCI_CHIP_RV530_71C4, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C5, PCI_CHIP_RV530_71C5, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C6, PCI_CHIP_RV530_71C6, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71C7, PCI_CHIP_RV530_71C7, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71CD, PCI_CHIP_RV530_71CD, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71CE, PCI_CHIP_RV530_71CE, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71D2, PCI_CHIP_RV530_71D2, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71D4, PCI_CHIP_RV530_71D4, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71D5, PCI_CHIP_RV530_71D5, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71D6, PCI_CHIP_RV530_71D6, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71DA, PCI_CHIP_RV530_71DA, RES_SHARED_VGA }, - { PCI_CHIP_RV530_71DE, PCI_CHIP_RV530_71DE, RES_SHARED_VGA }, - { PCI_CHIP_RV530_7200, PCI_CHIP_RV530_7200, RES_SHARED_VGA }, - { PCI_CHIP_RV530_7210, PCI_CHIP_RV530_7210, RES_SHARED_VGA }, - { PCI_CHIP_RV530_7211, PCI_CHIP_RV530_7211, RES_SHARED_VGA }, - { PCI_CHIP_R580_7240, PCI_CHIP_R580_7240, RES_SHARED_VGA }, - { PCI_CHIP_R580_7243, PCI_CHIP_R580_7243, RES_SHARED_VGA }, - { PCI_CHIP_R580_7244, PCI_CHIP_R580_7244, RES_SHARED_VGA }, - { PCI_CHIP_R580_7245, PCI_CHIP_R580_7245, RES_SHARED_VGA }, - { PCI_CHIP_R580_7246, PCI_CHIP_R580_7246, RES_SHARED_VGA }, - { PCI_CHIP_R580_7247, PCI_CHIP_R580_7247, RES_SHARED_VGA }, - { PCI_CHIP_R580_7248, PCI_CHIP_R580_7248, RES_SHARED_VGA }, - { PCI_CHIP_R580_7249, PCI_CHIP_R580_7249, RES_SHARED_VGA }, - { PCI_CHIP_R580_724A, PCI_CHIP_R580_724A, RES_SHARED_VGA }, - { PCI_CHIP_R580_724B, PCI_CHIP_R580_724B, RES_SHARED_VGA }, - { PCI_CHIP_R580_724C, PCI_CHIP_R580_724C, RES_SHARED_VGA }, - { PCI_CHIP_R580_724D, PCI_CHIP_R580_724D, RES_SHARED_VGA }, - { PCI_CHIP_R580_724E, PCI_CHIP_R580_724E, RES_SHARED_VGA }, - { PCI_CHIP_R580_724F, PCI_CHIP_R580_724F, RES_SHARED_VGA }, - { PCI_CHIP_RV570_7280, PCI_CHIP_RV570_7280, RES_SHARED_VGA }, - { PCI_CHIP_RV560_7281, PCI_CHIP_RV560_7281, RES_SHARED_VGA }, - { PCI_CHIP_RV560_7283, PCI_CHIP_RV560_7283, RES_SHARED_VGA }, - { PCI_CHIP_R580_7284, PCI_CHIP_R580_7284, RES_SHARED_VGA }, - { PCI_CHIP_RV560_7287, PCI_CHIP_RV560_7287, RES_SHARED_VGA }, - { PCI_CHIP_RV570_7288, PCI_CHIP_RV570_7288, RES_SHARED_VGA }, - { PCI_CHIP_RV570_7289, PCI_CHIP_RV570_7289, RES_SHARED_VGA }, - { PCI_CHIP_RV570_728B, PCI_CHIP_RV570_728B, RES_SHARED_VGA }, - { PCI_CHIP_RV570_728C, PCI_CHIP_RV570_728C, RES_SHARED_VGA }, - { PCI_CHIP_RV560_7290, PCI_CHIP_RV560_7290, RES_SHARED_VGA }, - { PCI_CHIP_RV560_7291, PCI_CHIP_RV560_7291, RES_SHARED_VGA }, - { PCI_CHIP_RV560_7293, PCI_CHIP_RV560_7293, RES_SHARED_VGA }, - { PCI_CHIP_RV560_7297, PCI_CHIP_RV560_7297, RES_SHARED_VGA }, - { PCI_CHIP_RS350_7834, PCI_CHIP_RS350_7834, RES_SHARED_VGA }, - { PCI_CHIP_RS350_7835, PCI_CHIP_RS350_7835, RES_SHARED_VGA }, - { PCI_CHIP_RS690_791E, PCI_CHIP_RS690_791E, RES_SHARED_VGA }, - { PCI_CHIP_RS690_791F, PCI_CHIP_RS690_791F, RES_SHARED_VGA }, - { PCI_CHIP_RS740_796C, PCI_CHIP_RS740_796C, RES_SHARED_VGA }, - { PCI_CHIP_RS740_796D, PCI_CHIP_RS740_796D, RES_SHARED_VGA }, - { PCI_CHIP_RS740_796E, PCI_CHIP_RS740_796E, RES_SHARED_VGA }, - { PCI_CHIP_RS740_796F, PCI_CHIP_RS740_796F, RES_SHARED_VGA }, - { PCI_CHIP_R600_9400, PCI_CHIP_R600_9400, RES_SHARED_VGA }, - { PCI_CHIP_R600_9401, PCI_CHIP_R600_9401, RES_SHARED_VGA }, - { PCI_CHIP_R600_9402, PCI_CHIP_R600_9402, RES_SHARED_VGA }, - { PCI_CHIP_R600_9403, PCI_CHIP_R600_9403, RES_SHARED_VGA }, - { PCI_CHIP_R600_9405, PCI_CHIP_R600_9405, RES_SHARED_VGA }, - { PCI_CHIP_R600_940A, PCI_CHIP_R600_940A, RES_SHARED_VGA }, - { PCI_CHIP_R600_940B, PCI_CHIP_R600_940B, RES_SHARED_VGA }, - { PCI_CHIP_R600_940F, PCI_CHIP_R600_940F, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C0, PCI_CHIP_RV610_94C0, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C1, PCI_CHIP_RV610_94C1, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C3, PCI_CHIP_RV610_94C3, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C4, PCI_CHIP_RV610_94C4, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C5, PCI_CHIP_RV610_94C5, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C6, PCI_CHIP_RV610_94C6, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C7, PCI_CHIP_RV610_94C7, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C8, PCI_CHIP_RV610_94C8, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA }, - { PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA }, - { PCI_CHIP_RV670_9500, PCI_CHIP_RV670_9500, RES_SHARED_VGA }, - { PCI_CHIP_RV670_9501, PCI_CHIP_RV670_9501, RES_SHARED_VGA }, - { PCI_CHIP_RV670_9505, PCI_CHIP_RV670_9505, RES_SHARED_VGA }, - { PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA }, - { PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA }, - { PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9586, PCI_CHIP_RV630_9586, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9587, PCI_CHIP_RV630_9587, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9588, PCI_CHIP_RV630_9588, RES_SHARED_VGA }, - { PCI_CHIP_RV630_9589, PCI_CHIP_RV630_9589, RES_SHARED_VGA }, - { PCI_CHIP_RV630_958A, PCI_CHIP_RV630_958A, RES_SHARED_VGA }, - { PCI_CHIP_RV630_958B, PCI_CHIP_RV630_958B, RES_SHARED_VGA }, - { PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA }, - { PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA }, - { PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA }, - { -1, -1, RES_UNDEFINED } -}; diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h deleted file mode 100644 index 04393da..0000000 --- a/src/radeon_pci_device_match_gen.h +++ /dev/null @@ -1,280 +0,0 @@ -/* This file is autogenerated please do not edit */ -static const struct pci_id_match radeon_device_match[] = { - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3150, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3152, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3154, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E50, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV380_3E54, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS100_4136, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS200_4137, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_AD, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_AE, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_AF, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_AG, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R350_AH, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R350_AI, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R350_AJ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R350_AK, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_AP, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_AQ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV360_AR, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_AS, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_AT, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_4155, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_AV, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS250_4237, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R200_BB, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R200_BC, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS100_4336, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS200_4337, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS250_4437, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV250_If, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ig, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JH, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JI, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JJ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JK, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JL, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JM, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JN, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_4A4F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R420_JP, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R481_4B49, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R481_4B4C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LW, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LX, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LY, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_LZ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV250_Ld, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lf, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV250_Lg, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_ND, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_NE, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_NF, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R300_NG, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R350_NH, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R350_NI, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R360_NJ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R350_NK, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_NP, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_NQ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_NR, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_NS, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_NT, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV350_NV, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QD, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QE, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QF, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RADEON_QG, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R200_QH, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R200_QL, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R200_QM, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV200_QW, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV200_QX, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV100_QY, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV100_QZ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RN50_515E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5460, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5462, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5464, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_UH, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_UI, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_UJ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_UK, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R430_554C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R430_554D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R430_554E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R430_554F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_5550, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_UQ, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_UR, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_UT, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_564A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_564B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_564F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5652, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5653, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS300_5834, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS300_5835, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS480_5954, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS480_5955, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5960, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5961, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5962, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5964, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5965, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RN50_5969, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS482_5974, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS485_5975, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A41, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS400_5A42, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A61, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RC410_5A62, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B60, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B62, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B63, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5657, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B64, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV370_5B65, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C61, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV280_5C63, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R430_5D48, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R430_5D49, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R430_5D4A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R480_5D4F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R480_5D50, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R480_5D52, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R423_5D57, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E48, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV410_5E4F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7100, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7101, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7102, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7103, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7104, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7105, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7106, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7108, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_7109, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_710A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_710B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_710C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_710E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R520_710F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7140, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7141, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7142, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7143, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7144, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7145, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7146, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7147, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7149, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_714A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_714B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_714C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_714D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_714E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_714F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7151, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7152, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7153, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_715E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_715F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7180, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7181, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7183, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7186, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7187, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7188, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_718A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_718B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_718C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_718D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_718F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7193, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_7196, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_719B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV515_719F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C1, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C2, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C3, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C4, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C5, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C6, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71C7, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CD, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71CE, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D2, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D4, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D5, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71D6, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DA, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_71DE, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_7200, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_7210, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV530_7211, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7240, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7243, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7244, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7245, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7246, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7247, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7248, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7249, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_724A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_724B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_724C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_724D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_724E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_724F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV570_7280, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV560_7281, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV560_7283, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R580_7284, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV560_7287, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV570_7288, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV570_7289, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV570_728B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV570_728C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV560_7290, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV560_7291, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV560_7293, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV560_7297, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS350_7834, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS350_7835, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS690_791E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS690_791F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS740_796C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS740_796D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS740_796E, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RS740_796F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_9400, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_9401, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_9402, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_9403, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_9405, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_940A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_940B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_R600_940F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C0, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C1, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C3, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C4, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C5, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C6, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C7, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C8, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C9, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CB, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CC, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_9500, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_9501, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_9505, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9586, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9587, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9588, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_9589, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958A, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958B, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ), - ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ), - { 0, 0, 0 } -}; |