Add definitions for the SMI 501/502 "command list interpreter".

  This also changes some bit operations to use a "bitfield" equivalent
one, with named fields, that should make it easier to understand what
is being tested.

  The enum smi_cli_cmd_code in smi_501.h is code that was added to a
experimental smi_drm.h, but the hardware only supports basic 2d accel,
and to compensate for the extra overhead for maintaining a command
list (assuming it worked correctly) it would be required to have a
special handling, like calling an ioctl to do the "busy loop" in the
kernel (that is, should wait for an irq or a timeout).

  The problem is that even if waiting for a idle engine before crafting
a command, and waiting again after submitting the command, there would
be corruption on screen after some time. So, the "busy loop" in the
kernel would only be useful if still using direct writes to mmio
registers.

1 files changed, 6 insertions, 5 deletions

diff --git a/src/smi_501.c b/src/smi_501.c
index 3aa81de..a392eb0 100644
--- a/src/smi_501.c
+++ b/src/smi_501.c
@@ -605,25 +605,26 @@ SMI501_PrintRegs(ScrnInfoPtr pScrn)
 void
 SMI501_WaitVSync(SMIPtr pSmi, int vsync_count)
 {
-    int32_t	status, timeout;
+    MSOCCmdStatusRec	status;
+    int32_t		timeout;
 
     while (vsync_count-- > 0) {
 	/* Wait for end of vsync */
 	timeout = 0;
 	do {
 	    /* bit 11: vsync active *if set* */
-	    status = READ_SCR(pSmi, CMD_STATUS);
+	    status.value = READ_SCR(pSmi, CMD_STATUS);
 	    if (++timeout == 10000)
 		break;
-	} while (status & (1 << 11));
+	} while (status.f.pvsync);
 
 	/* Wait for start of vsync */
 	timeout = 0;
 	do {
-	    status = READ_SCR(pSmi, CMD_STATUS);
+	    status.value = READ_SCR(pSmi, CMD_STATUS);
 	    if (++timeout == 10000)
 		break;
-	} while (!(status & (1 << 11)));
+	} while (!status.f.pvsync);
     }
 }