vmwgfx, saa: Initial import

This imports the vmwgfx driver, based on the Gallium3D Xorg state tracker,
as well as the saa library. A "Shadow Acceleration Architecture", which is
optimized for the case where transfers between system (shadow) and hw memory
is very costly.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>

1 files changed, 868 insertions, 375 deletions

diff --git a/src/svga_reg.h b/src/svga_reg.h
index 4fa363a..5d36029 100644
--- a/src/svga_reg.h
+++ b/src/svga_reg.h
@@ -1,52 +1,72 @@
-/* **********************************************************
- * Copyright 1998 VMware, Inc.  All rights reserved.
- * **********************************************************/
+/**********************************************************
+ * Copyright 1998-2009 VMware, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ **********************************************************/
 
 /*
  * svga_reg.h --
  *
- * SVGA hardware definitions
+ *    Virtual hardware definitions for the VMware SVGA II device.
  */
 
 #ifndef _SVGA_REG_H_
 #define _SVGA_REG_H_
 
-#define INCLUDE_ALLOW_USERLEVEL
-#define INCLUDE_ALLOW_VMMEXT
-#define INCLUDE_ALLOW_VMCORE
-#include "includeCheck.h"
-
 /*
- * Memory and port addresses and fundamental constants
+ * PCI device IDs.
  */
+#define PCI_VENDOR_ID_VMWARE            0x15AD
+#define PCI_DEVICE_ID_VMWARE_SVGA2      0x0405
 
 /*
- * Note-- MAX_WIDTH and MAX_HEIGHT are largely ignored by the code.  This
- * isn't such a bad thing for forward compatibility. --Jeremy.
+ * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
+ * cursor bypass mode. This is still supported, but no new guest
+ * drivers should use it.
  */
-#define SVGA_MAX_WIDTH			2360
-#define SVGA_MAX_HEIGHT			1770
-#define SVGA_MAX_BITS_PER_PIXEL		32
-#define SVGA_MAX_DEPTH                  24
-#define SVGA_MAX_DISPLAYS               10
+#define SVGA_CURSOR_ON_HIDE            0x0   /* Must be 0 to maintain backward compatibility */
+#define SVGA_CURSOR_ON_SHOW            0x1   /* Must be 1 to maintain backward compatibility */
+#define SVGA_CURSOR_ON_REMOVE_FROM_FB  0x2   /* Remove the cursor from the framebuffer because we need to see what's under it */
+#define SVGA_CURSOR_ON_RESTORE_TO_FB   0x3   /* Put the cursor back in the framebuffer so the user can see it */
 
 /*
- * The maximum size of the onscreen framebuffer.  The size of the
- * changeMap in the monitor is proportional to this number since it's
- * the amount of memory we need to trace in VESA mode.  Therefore, we'd
+ * The maximum framebuffer size that can traced for e.g. guests in VESA mode.
+ * The changeMap in the monitor is proportional to this number. Therefore, we'd
  * like to keep it as small as possible to reduce monitor overhead (using
- * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area
- * by over 4k!).
+ * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
+ * 4k!).
+ *
+ * NB: For compatibility reasons, this value must be greater than 0xff0000.
+ *     See bug 335072.
  */
- 
-#define SVGA_FB_MAX_SIZE \
-   ((((SVGA_MAX_WIDTH * SVGA_MAX_HEIGHT *                                    \
-       SVGA_MAX_BITS_PER_PIXEL / 8) >> PAGE_SHIFT) + 1) << PAGE_SHIFT)
+#define SVGA_FB_MAX_TRACEABLE_SIZE      0x1000000
 
-#define SVGA_MAX_PSEUDOCOLOR_DEPTH	8
-#define SVGA_MAX_PSEUDOCOLORS		(1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
+#define SVGA_MAX_PSEUDOCOLOR_DEPTH      8
+#define SVGA_MAX_PSEUDOCOLORS           (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
 #define SVGA_NUM_PALETTE_REGS           (3 * SVGA_MAX_PSEUDOCOLORS)
 
+/* Base and Offset gets us headed the right way for PCI Base Addr Registers */
+#define SVGA_LEGACY_BASE_PORT	0x4560
+
 #define SVGA_MAGIC         0x900000UL
 #define SVGA_MAKE_ID(ver)  (SVGA_MAGIC << 8 | (ver))
 
@@ -63,19 +83,14 @@
 #define SVGA_VERSION_0     0
 #define SVGA_ID_0          SVGA_MAKE_ID(SVGA_VERSION_0)
 
-/* Invalid SVGA_ID_ */
+/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
 #define SVGA_ID_INVALID    0xFFFFFFFF
 
-/* More backwards compatibility, old location of color map: */
-#define SVGA_OLD_PALETTE_BASE	 17
-
-/* Base and Offset gets us headed the right way for PCI Base Addr Registers */
-#define SVGA_LEGACY_BASE_PORT	0x4560
-#define SVGA_INDEX_PORT		0x0
-#define SVGA_VALUE_PORT		0x1
-#define SVGA_BIOS_PORT		0x2
-#define SVGA_NUM_PORTS		0x3
-#define SVGA_IRQSTATUS_PORT	0x8
+/* Port offsets, relative to BAR0 */
+#define SVGA_INDEX_PORT         0x0
+#define SVGA_VALUE_PORT         0x1
+#define SVGA_BIOS_PORT          0x2
+#define SVGA_IRQSTATUS_PORT     0x8
 
 /*
  * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
@@ -87,15 +102,6 @@
 #define SVGA_IRQFLAG_FIFO_PROGRESS        0x2    /* Made forward progress in the FIFO */
 #define SVGA_IRQFLAG_FENCE_GOAL           0x4    /* SVGA_FIFO_FENCE_GOAL reached */
 
-/* This port is deprecated, but retained because of old drivers. */
-#define SVGA_LEGACY_ACCEL_PORT	0x3
-
-/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
-#define SVGA_CURSOR_ON_HIDE               0x0    /* Must be 0 to maintain backward compatibility */
-#define SVGA_CURSOR_ON_SHOW               0x1    /* Must be 1 to maintain backward compatibility */
-#define SVGA_CURSOR_ON_REMOVE_FROM_FB     0x2    /* Remove the cursor from the framebuffer because we need to see what's under it */
-#define SVGA_CURSOR_ON_RESTORE_TO_FB      0x3    /* Put the cursor back in the framebuffer so the user can see it */
-
 /*
  * Registers
  */
@@ -108,13 +114,13 @@ enum {
    SVGA_REG_MAX_WIDTH = 4,
    SVGA_REG_MAX_HEIGHT = 5,
    SVGA_REG_DEPTH = 6,
-   SVGA_REG_BITS_PER_PIXEL = 7,     /* Current bpp in the guest */
+   SVGA_REG_BITS_PER_PIXEL = 7,       /* Current bpp in the guest */
    SVGA_REG_PSEUDOCOLOR = 8,
    SVGA_REG_RED_MASK = 9,
    SVGA_REG_GREEN_MASK = 10,
    SVGA_REG_BLUE_MASK = 11,
    SVGA_REG_BYTES_PER_LINE = 12,
-   SVGA_REG_FB_START = 13,
+   SVGA_REG_FB_START = 13,            /* (Deprecated) */
    SVGA_REG_FB_OFFSET = 14,
    SVGA_REG_VRAM_SIZE = 15,
    SVGA_REG_FB_SIZE = 16,
@@ -122,33 +128,44 @@ enum {
    /* ID 0 implementation only had the above registers, then the palette */
 
    SVGA_REG_CAPABILITIES = 17,
-   SVGA_REG_MEM_START = 18,	   /* Memory for command FIFO and bitmaps */
+   SVGA_REG_MEM_START = 18,           /* (Deprecated) */
    SVGA_REG_MEM_SIZE = 19,
-   SVGA_REG_CONFIG_DONE = 20,      /* Set when memory area configured */
-   SVGA_REG_SYNC = 21,             /* See "FIFO Synchronization Registers" */
-   SVGA_REG_BUSY = 22,             /* See "FIFO Synchronization Registers" */
-   SVGA_REG_GUEST_ID = 23,	   /* Set guest OS identifier */
-   SVGA_REG_CURSOR_ID = 24,	   /* ID of cursor */
-   SVGA_REG_CURSOR_X = 25,	   /* Set cursor X position */
-   SVGA_REG_CURSOR_Y = 26,	   /* Set cursor Y position */
-   SVGA_REG_CURSOR_ON = 27,	   /* Turn cursor on/off */
-   SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
-   SVGA_REG_SCRATCH_SIZE = 29,     /* Number of scratch registers */
-   SVGA_REG_MEM_REGS = 30,         /* Number of FIFO registers */
-   SVGA_REG_NUM_DISPLAYS = 31,     /* Number of guest displays */
-   SVGA_REG_PITCHLOCK = 32,        /* Fixed pitch for all modes */
-   SVGA_REG_IRQMASK = 33,          /* Interrupt mask */
+   SVGA_REG_CONFIG_DONE = 20,         /* Set when memory area configured */
+   SVGA_REG_SYNC = 21,                /* See "FIFO Synchronization Registers" */
+   SVGA_REG_BUSY = 22,                /* See "FIFO Synchronization Registers" */
+   SVGA_REG_GUEST_ID = 23,            /* Set guest OS identifier */
+   SVGA_REG_CURSOR_ID = 24,           /* (Deprecated) */
+   SVGA_REG_CURSOR_X = 25,            /* (Deprecated) */
+   SVGA_REG_CURSOR_Y = 26,            /* (Deprecated) */
+   SVGA_REG_CURSOR_ON = 27,           /* (Deprecated) */
+   SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
+   SVGA_REG_SCRATCH_SIZE = 29,        /* Number of scratch registers */
+   SVGA_REG_MEM_REGS = 30,            /* Number of FIFO registers */
+   SVGA_REG_NUM_DISPLAYS = 31,        /* (Deprecated) */
+   SVGA_REG_PITCHLOCK = 32,           /* Fixed pitch for all modes */
+   SVGA_REG_IRQMASK = 33,             /* Interrupt mask */
+
+   /* Legacy multi-monitor support */
    SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
-   SVGA_REG_DISPLAY_ID = 35,        /* The display ID for the following display attributes */
+   SVGA_REG_DISPLAY_ID = 35,        /* Display ID for the following display attributes */
    SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
    SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
    SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
    SVGA_REG_DISPLAY_WIDTH = 39,     /* The display's width */
    SVGA_REG_DISPLAY_HEIGHT = 40,    /* The display's height */
-   SVGA_REG_TOP = 41,               /* Must be 1 more than the last register */
 
-   SVGA_PALETTE_BASE = 1024,	    /* Base of SVGA color map */
+   /* See "Guest memory regions" below. */
+   SVGA_REG_GMR_ID = 41,
+   SVGA_REG_GMR_DESCRIPTOR = 42,
+   SVGA_REG_GMR_MAX_IDS = 43,
+   SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
+
+   SVGA_REG_TRACES = 45,            /* Enable trace-based updates even when FIFO is on */
+   SVGA_REG_TOP = 46,               /* Must be 1 more than the last register */
+
+   SVGA_PALETTE_BASE = 1024,        /* Base of SVGA color map */
    /* Next 768 (== 256*3) registers exist for colormap */
+
    SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
                                     /* Base of scratch registers */
    /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
@@ -156,126 +173,231 @@ enum {
       the use of the current SVGA driver. */
 };
 
+/*
+ *  Macros to compute variable length items (sizes in 32-bit words, except
+ *  for SVGA_GLYPH_SCANLINE_SIZE, which is in bytes).
+ */
+#define SVGA_BITMAP_SIZE(w,h) ((((w)+31) >> 5) * (h))
+#define SVGA_PIXMAP_SIZE(w,h,bpp) ((( ((w)*(bpp))+31 ) >> 5) * (h))
+#define SVGA_BITMAP_INCREMENT(w) ((( (w)+31 ) >> 5) * sizeof (uint32))
+#define SVGA_PIXMAP_INCREMENT(w,bpp) ((( ((w)*(bpp))+31 ) >> 5) * sizeof (uint32))
 
 /*
- *  Capabilities
+ * Guest memory regions (GMRs):
+ *
+ * This is a new memory mapping feature available in SVGA devices
+ * which have the SVGA_CAP_GMR bit set. Previously, there were two
+ * fixed memory regions available with which to share data between the
+ * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
+ * are our name for an extensible way of providing arbitrary DMA
+ * buffers for use between the driver and the SVGA device. They are a
+ * new alternative to framebuffer memory, usable for both 2D and 3D
+ * graphics operations.
+ *
+ * Since GMR mapping must be done synchronously with guest CPU
+ * execution, we use a new pair of SVGA registers:
+ *
+ *   SVGA_REG_GMR_ID --
+ *
+ *     Read/write.
+ *     This register holds the 32-bit ID (a small positive integer)
+ *     of a GMR to create, delete, or redefine. Writing this register
+ *     has no side-effects.
+ *
+ *   SVGA_REG_GMR_DESCRIPTOR --
+ *
+ *     Write-only.
+ *     Writing this register will create, delete, or redefine the GMR
+ *     specified by the above ID register. If this register is zero,
+ *     the GMR is deleted. Any pointers into this GMR (including those
+ *     currently being processed by FIFO commands) will be
+ *     synchronously invalidated.
+ *
+ *     If this register is nonzero, it must be the physical page
+ *     number (PPN) of a data structure which describes the physical
+ *     layout of the memory region this GMR should describe. The
+ *     descriptor structure will be read synchronously by the SVGA
+ *     device when this register is written. The descriptor need not
+ *     remain allocated for the lifetime of the GMR.
+ *
+ *     The guest driver should write SVGA_REG_GMR_ID first, then
+ *     SVGA_REG_GMR_DESCRIPTOR.
+ *
+ *   SVGA_REG_GMR_MAX_IDS --
+ *
+ *     Read-only.
+ *     The SVGA device may choose to support a maximum number of
+ *     user-defined GMR IDs. This register holds the number of supported
+ *     IDs. (The maximum supported ID plus 1)
+ *
+ *   SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
+ *
+ *     Read-only.
+ *     The SVGA device may choose to put a limit on the total number
+ *     of SVGAGuestMemDescriptor structures it will read when defining
+ *     a single GMR.
+ *
+ * The descriptor structure is an array of SVGAGuestMemDescriptor
+ * structures. Each structure may do one of three things:
+ *
+ *   - Terminate the GMR descriptor list.
+ *     (ppn==0, numPages==0)
+ *
+ *   - Add a PPN or range of PPNs to the GMR's virtual address space.
+ *     (ppn != 0, numPages != 0)
+ *
+ *   - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
+ *     support multi-page GMR descriptor tables without forcing the
+ *     driver to allocate physically contiguous memory.
+ *     (ppn != 0, numPages == 0)
+ *
+ * Note that each physical page of SVGAGuestMemDescriptor structures
+ * can describe at least 2MB of guest memory. If the driver needs to
+ * use more than one page of descriptor structures, it must use one of
+ * its SVGAGuestMemDescriptors to point to an additional page.  The
+ * device will never automatically cross a page boundary.
+ *
+ * Once the driver has described a GMR, it is immediately available
+ * for use via any FIFO command that uses an SVGAGuestPtr structure.
+ * These pointers include a GMR identifier plus an offset into that
+ * GMR.
+ *
+ * The driver must check the SVGA_CAP_GMR bit before using the GMR
+ * registers.
  */
 
-#define SVGA_CAP_NONE               0x00000000
-#define SVGA_CAP_RECT_FILL	    0x00000001
-#define SVGA_CAP_RECT_COPY	    0x00000002
-#define SVGA_CAP_RECT_PAT_FILL      0x00000004
-#define SVGA_CAP_LEGACY_OFFSCREEN   0x00000008
-#define SVGA_CAP_RASTER_OP	    0x00000010
-#define SVGA_CAP_CURSOR		    0x00000020
-#define SVGA_CAP_CURSOR_BYPASS	    0x00000040
-#define SVGA_CAP_CURSOR_BYPASS_2    0x00000080
-#define SVGA_CAP_8BIT_EMULATION     0x00000100
-#define SVGA_CAP_ALPHA_CURSOR       0x00000200
-#define SVGA_CAP_GLYPH              0x00000400
-#define SVGA_CAP_GLYPH_CLIPPING     0x00000800
-#define SVGA_CAP_OFFSCREEN_1        0x00001000
-#define SVGA_CAP_ALPHA_BLEND        0x00002000
-#define SVGA_CAP_3D                 0x00004000
-#define SVGA_CAP_EXTENDED_FIFO      0x00008000
-#define SVGA_CAP_MULTIMON           0x00010000
-#define SVGA_CAP_PITCHLOCK          0x00020000
-#define SVGA_CAP_IRQMASK            0x00040000
-#define SVGA_CAP_DISPLAY_TOPOLOGY   0x00080000
+/*
+ * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
+ * memory as well.  In the future, these IDs could even be used to
+ * allow legacy memory regions to be redefined by the guest as GMRs.
+ *
+ * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
+ * is being phased out. Please try to use user-defined GMRs whenever
+ * possible.
+ */
+#define SVGA_GMR_NULL         ((uint32) -1)
+#define SVGA_GMR_FRAMEBUFFER  ((uint32) -2)  // Guest Framebuffer (GFB)
+
+typedef
+struct SVGAGuestMemDescriptor {
+   uint32 ppn;
+   uint32 numPages;
+} SVGAGuestMemDescriptor;
+
+typedef
+struct SVGAGuestPtr {
+   uint32 gmrId;
+   uint32 offset;
+} SVGAGuestPtr;
 
 
 /*
- *  Raster op codes (same encoding as X) used by FIFO drivers.
+ * SVGAGMRImageFormat --
+ *
+ *    This is a packed representation of the source 2D image format
+ *    for a GMR-to-screen blit. Currently it is defined as an encoding
+ *    of the screen's color depth and bits-per-pixel, however, 16 bits
+ *    are reserved for future use to identify other encodings (such as
+ *    RGBA or higher-precision images).
+ *
+ *    Currently supported formats:
+ *
+ *       bpp depth  Format Name
+ *       --- -----  -----------
+ *        32    24  32-bit BGRX
+ *        24    24  24-bit BGR
+ *        16    16  RGB 5-6-5
+ *        16    15  RGB 5-5-5
+ *
  */
 
-#define SVGA_ROP_CLEAR          0x00     /* 0 */
-#define SVGA_ROP_AND            0x01     /* src AND dst */
-#define SVGA_ROP_AND_REVERSE    0x02     /* src AND NOT dst */
-#define SVGA_ROP_COPY           0x03     /* src */
-#define SVGA_ROP_AND_INVERTED   0x04     /* NOT src AND dst */
-#define SVGA_ROP_NOOP           0x05     /* dst */
-#define SVGA_ROP_XOR            0x06     /* src XOR dst */
-#define SVGA_ROP_OR             0x07     /* src OR dst */
-#define SVGA_ROP_NOR            0x08     /* NOT src AND NOT dst */
-#define SVGA_ROP_EQUIV          0x09     /* NOT src XOR dst */
-#define SVGA_ROP_INVERT         0x0a     /* NOT dst */
-#define SVGA_ROP_OR_REVERSE     0x0b     /* src OR NOT dst */
-#define SVGA_ROP_COPY_INVERTED  0x0c     /* NOT src */
-#define SVGA_ROP_OR_INVERTED    0x0d     /* NOT src OR dst */
-#define SVGA_ROP_NAND           0x0e     /* NOT src OR NOT dst */
-#define SVGA_ROP_SET            0x0f     /* 1 */
-#define SVGA_ROP_UNSUPPORTED    0x10
+typedef
+struct SVGAGMRImageFormat {
+   union {
+      struct {
+         uint32 bitsPerPixel : 8;
+         uint32 colorDepth   : 8;
+         uint32 reserved     : 16;  // Must be zero
+      };
 
-#define SVGA_NUM_SUPPORTED_ROPS   16
-#define SVGA_ROP_ALL            (MASK(SVGA_NUM_SUPPORTED_ROPS))
-#define SVGA_IS_VALID_ROP(rop)  (rop < SVGA_NUM_SUPPORTED_ROPS)
+      uint32 value;
+   };
+} SVGAGMRImageFormat;
+
+/*
+ * SVGAColorBGRX --
+ *
+ *    A 24-bit color format (BGRX), which does not depend on the
+ *    format of the legacy guest framebuffer (GFB) or the current
+ *    GMRFB state.
+ */
+
+typedef
+struct SVGAColorBGRX {
+   union {
+      struct {
+         uint32 b : 8;
+         uint32 g : 8;
+         uint32 r : 8;
+         uint32 x : 8;  // Unused
+      };
+
+      uint32 value;
+   };
+} SVGAColorBGRX;
 
-#define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
 
 /*
- *  Ops
- *  For each pixel, the four channels of the image are computed with: 
- *
- *	C = Ca * Fa + Cb * Fb
- *
- *  where C, Ca, Cb are the values of the respective channels and Fa 
- *  and Fb come from the following table: 
- *
- *	BlendOp		Fa			Fb
- *	------------------------------------------
- *	Clear		0			0
- *	Src		1			0
- *	Dst		0			1
- *	Over		1			1-Aa
- *	OverReverse	1-Ab			1
- *	In		Ab			0
- *	InReverse	0			Aa
- *	Out		1-Ab			0
- *	OutReverse	0			1-Aa
- *	Atop		Ab			1-Aa
- *	AtopReverse	1-Ab			Aa
- *	Xor		1-Ab			1-Aa
- *	Add		1			1
- *	Saturate	min(1,(1-Ab)/Aa)	1
- *
- *  Flags
- *  You can use the following flags to achieve additional affects:
- * 
- *      Flag                    Effect
- *	------------------------------------------
- *      ConstantSourceAlpha     Ca = Ca * Param0
- *      ConstantDestAlpha       Cb = Cb * Param1
- *
- *  Flag effects resolve before the op.  For example
- *  BlendOp == Add && Flags == ConstantSourceAlpha |
- *  ConstantDestAlpha results in:
- *
- *       C = (Ca * Param0) + (Cb * Param1)
- */
-
-#define SVGA_BLENDOP_CLEAR                      0
-#define SVGA_BLENDOP_SRC                        1
-#define SVGA_BLENDOP_DST                        2
-#define SVGA_BLENDOP_OVER                       3
-#define SVGA_BLENDOP_OVER_REVERSE               4
-#define SVGA_BLENDOP_IN                         5
-#define SVGA_BLENDOP_IN_REVERSE                 6
-#define SVGA_BLENDOP_OUT                        7
-#define SVGA_BLENDOP_OUT_REVERSE                8
-#define SVGA_BLENDOP_ATOP                       9 
-#define SVGA_BLENDOP_ATOP_REVERSE               10
-#define SVGA_BLENDOP_XOR                        11
-#define SVGA_BLENDOP_ADD                        12
-#define SVGA_BLENDOP_SATURATE                   13
-
-#define SVGA_NUM_BLENDOPS                       14
-#define SVGA_IS_VALID_BLENDOP(op)               (op >= 0 && op < SVGA_NUM_BLENDOPS)
-
-#define SVGA_BLENDFLAG_CONSTANT_SOURCE_ALPHA    0x01
-#define SVGA_BLENDFLAG_CONSTANT_DEST_ALPHA      0x02
-#define SVGA_NUM_BLENDFLAGS                     2
-#define SVGA_BLENDFLAG_ALL                      (MASK(SVGA_NUM_BLENDFLAGS))
-#define SVGA_IS_VALID_BLENDFLAG(flag)           ((flag & ~SVGA_BLENDFLAG_ALL) == 0)
+ * SVGASignedRect --
+ * SVGASignedPoint --
+ *
+ *    Signed rectangle and point primitives. These are used by the new
+ *    2D primitives for drawing to Screen Objects, which can occupy a
+ *    signed virtual coordinate space.
+ *
+ *    SVGASignedRect specifies a half-open interval: the (left, top)
+ *    pixel is part of the rectangle, but the (right, bottom) pixel is
+ *    not.
+ */
+
+typedef
+struct SVGASignedRect {
+   int32  left;
+   int32  top;
+   int32  right;
+   int32  bottom;
+} SVGASignedRect;
+
+typedef
+struct SVGASignedPoint {
+   int32  x;
+   int32  y;
+} SVGASignedPoint;
+
+
+/*
+ *  Capabilities
+ *
+ *  Note the holes in the bitfield. Missing bits have been deprecated,
+ *  and must not be reused. Those capabilities will never be reported
+ *  by new versions of the SVGA device.
+ */
+
+#define SVGA_CAP_NONE               0x00000000
+#define SVGA_CAP_RECT_COPY          0x00000002
+#define SVGA_CAP_CURSOR             0x00000020
+#define SVGA_CAP_CURSOR_BYPASS      0x00000040   // Legacy (Use Cursor Bypass 3 instead)
+#define SVGA_CAP_CURSOR_BYPASS_2    0x00000080   // Legacy (Use Cursor Bypass 3 instead)
+#define SVGA_CAP_8BIT_EMULATION     0x00000100
+#define SVGA_CAP_ALPHA_CURSOR       0x00000200
+#define SVGA_CAP_3D                 0x00004000
+#define SVGA_CAP_EXTENDED_FIFO      0x00008000
+#define SVGA_CAP_MULTIMON           0x00010000   // Legacy multi-monitor support
+#define SVGA_CAP_PITCHLOCK          0x00020000
+#define SVGA_CAP_IRQMASK            0x00040000
+#define SVGA_CAP_DISPLAY_TOPOLOGY   0x00080000   // Legacy multi-monitor support
+#define SVGA_CAP_GMR                0x00100000
+#define SVGA_CAP_TRACES             0x00200000
 
 
 /*
@@ -320,7 +442,7 @@ enum {
 
    SVGA_FIFO_CAPABILITIES = 4,
    SVGA_FIFO_FLAGS,
-   /* Valid with SVGA_FIFO_CAP_FENCE: */
+   // Valid with SVGA_FIFO_CAP_FENCE:
    SVGA_FIFO_FENCE,
 
    /*
@@ -332,19 +454,33 @@ enum {
     * These in block 3a, the VMX currently considers mandatory for the
     * extended FIFO.
     */
-   
-   /* Valid if exists (i.e. if extended FIFO enabled): */
+
+   // Valid if exists (i.e. if extended FIFO enabled):
    SVGA_FIFO_3D_HWVERSION,       /* See SVGA3dHardwareVersion in svga3d_reg.h */
-   /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */
+   // Valid with SVGA_FIFO_CAP_PITCHLOCK:
    SVGA_FIFO_PITCHLOCK,
-   /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */
+
+   // Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3:
    SVGA_FIFO_CURSOR_ON,          /* Cursor bypass 3 show/hide register */
    SVGA_FIFO_CURSOR_X,           /* Cursor bypass 3 x register */
    SVGA_FIFO_CURSOR_Y,           /* Cursor bypass 3 y register */
    SVGA_FIFO_CURSOR_COUNT,       /* Incremented when any of the other 3 change */
    SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
-   /* Valid with SVGA_FIFO_CAP_RESERVE: */
+
+   // Valid with SVGA_FIFO_CAP_RESERVE:
    SVGA_FIFO_RESERVED,           /* Bytes past NEXT_CMD with real contents */
+
+   /*
+    * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT:
+    *
+    * By default this is SVGA_ID_INVALID, to indicate that the cursor
+    * coordinates are specified relative to the virtual root. If this
+    * is set to a specific screen ID, cursor position is reinterpreted
+    * as a signed offset relative to that screen's origin. This is the
+    * only way to place the cursor on a non-rooted screen.
+    */
+   SVGA_FIFO_CURSOR_SCREEN_ID,
+
    /*
     * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
     * registers, but this must be done carefully and with judicious use of
@@ -361,6 +497,7 @@ enum {
     * before 3D_CAPS, needs to reason about something other than
     * SVGA_FIFO_MIN.
     */
+
    /*
     * 3D caps block space; valid with 3D hardware version >=
     * SVGA3D_HWVERSION_WS6_B1.
@@ -382,7 +519,7 @@ enum {
     * sets SVGA_FIFO_MIN high enough to leave room for them.
     */
 
-   /* Valid if register exists: */
+   // Valid if register exists:
    SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
    SVGA_FIFO_FENCE_GOAL,         /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
    SVGA_FIFO_BUSY,               /* See "FIFO Synchronization Registers" */
@@ -533,6 +670,56 @@ enum {
  *      Pitch Lock -- Pitch lock register is supported
  *      Video -- SVGA Video overlay units are supported
  *      Escape -- Escape command is supported
+ *
+ * XXX: Add longer descriptions for each capability, including a list
+ *      of the new features that each capability provides.
+ *
+ * SVGA_FIFO_CAP_SCREEN_OBJECT --
+ *
+ *    Provides dynamic multi-screen rendering, for improved Unity and
+ *    multi-monitor modes. With Screen Object, the guest can
+ *    dynamically create and destroy 'screens', which can represent
+ *    Unity windows or virtual monitors. Screen Object also provides
+ *    strong guarantees that DMA operations happen only when
+ *    guest-initiated. Screen Object deprecates the BAR1 guest
+ *    framebuffer (GFB) and all commands that work only with the GFB.
+ *
+ *    New registers:
+ *       FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
+ *
+ *    New 2D commands:
+ *       DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
+ *       BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
+ *
+ *    New 3D commands:
+ *       BLIT_SURFACE_TO_SCREEN
+ *
+ *    New guarantees:
+ *
+ *       - The host will not read or write guest memory, including the GFB,
+ *         except when explicitly initiated by a DMA command.
+ *
+ *       - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
+ *         is guaranteed to complete before any subsequent FENCEs.
+ *
+ *       - All legacy commands which affect a Screen (UPDATE, PRESENT,
+ *         PRESENT_READBACK) as well as new Screen blit commands will
+ *         all behave consistently as blits, and memory will be read
+ *         or written in FIFO order.
+ *
+ *         For example, if you PRESENT from one SVGA3D surface to multiple
+ *         places on the screen, the data copied will always be from the
+ *         SVGA3D surface at the time the PRESENT was issued in the FIFO.
+ *         This was not necessarily true on devices without Screen Object.
+ *
+ *         This means that on devices that support Screen Object, the
+ *         PRESENT_READBACK command should not be necessary unless you
+ *         actually want to read back the results of 3D rendering into
+ *         system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
+ *         command provides a strict superset of functionality.)
+ *
+ *       - When a screen is resized, either using Screen Object commands or
+ *         legacy multimon registers, its contents are preserved.
  */
 
 #define SVGA_FIFO_CAP_NONE                  0
@@ -543,6 +730,7 @@ enum {
 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3   (1<<4)
 #define SVGA_FIFO_CAP_ESCAPE            (1<<5)
 #define SVGA_FIFO_CAP_RESERVE           (1<<6)
+#define SVGA_FIFO_CAP_SCREEN_OBJECT     (1<<7)
 
 
 /*
@@ -553,7 +741,7 @@ enum {
 
 #define SVGA_FIFO_FLAG_NONE                 0
 #define SVGA_FIFO_FLAG_ACCELFRONT       (1<<0)
-#define SVGA_FIFO_FLAG_RESERVED        (1<<31) /* Internal use only */
+#define SVGA_FIFO_FLAG_RESERVED        (1<<31) // Internal use only
 
 /*
  * FIFO reservation sentinel value
@@ -586,20 +774,22 @@ enum {
    SVGA_VIDEO_DATA_OFFSET,
    SVGA_VIDEO_FORMAT,
    SVGA_VIDEO_COLORKEY,
-   SVGA_VIDEO_SIZE,
+   SVGA_VIDEO_SIZE,          // Deprecated
    SVGA_VIDEO_WIDTH,
    SVGA_VIDEO_HEIGHT,
    SVGA_VIDEO_SRC_X,
    SVGA_VIDEO_SRC_Y,
    SVGA_VIDEO_SRC_WIDTH,
    SVGA_VIDEO_SRC_HEIGHT,
-   SVGA_VIDEO_DST_X,
-   SVGA_VIDEO_DST_Y,
+   SVGA_VIDEO_DST_X,         // Signed int32
+   SVGA_VIDEO_DST_Y,         // Signed int32
    SVGA_VIDEO_DST_WIDTH,
    SVGA_VIDEO_DST_HEIGHT,
    SVGA_VIDEO_PITCH_1,
    SVGA_VIDEO_PITCH_2,
    SVGA_VIDEO_PITCH_3,
+   SVGA_VIDEO_DATA_GMRID,    // Optional, defaults to SVGA_GMR_FRAMEBUFFER
+   SVGA_VIDEO_DST_SCREEN_ID, // Optional, defaults to virtual coords (SVGA_ID_INVALID)
    SVGA_VIDEO_NUM_REGS
 };
 
@@ -625,242 +815,545 @@ typedef struct SVGAOverlayUnit {
    uint32 srcY;
    uint32 srcWidth;
    uint32 srcHeight;
-   uint32 dstX;
-   uint32 dstY;
+   int32  dstX;
+   int32  dstY;
    uint32 dstWidth;
    uint32 dstHeight;
    uint32 pitches[3];
+   uint32 dataGMRId;
+   uint32 dstScreenId;
 } SVGAOverlayUnit;
 
 
 /*
- *  Drawing object ID's, in the range 0 to SVGA_MAX_ID
+ * SVGAScreenObject --
+ *
+ *    This is a new way to represent a guest's multi-monitor screen or
+ *    Unity window. Screen objects are only supported if the
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
+ *
+ *    If Screen Objects are supported, they can be used to fully
+ *    replace the functionality provided by the framebuffer registers
+ *    (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
+ *
+ *    The screen object is a struct with guaranteed binary
+ *    compatibility. New flags can be added, and the struct may grow,
+ *    but existing fields must retain their meaning.
+ *
  */
 
-#define	 SVGA_MAX_ID	      499
+#define SVGA_SCREEN_HAS_ROOT    (1 << 0)  // Screen is present in the virtual coord space
+#define SVGA_SCREEN_IS_PRIMARY  (1 << 1)  // Guest considers this screen to be 'primary'
+#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)   // Guest is running a fullscreen app here
+
+typedef
+struct SVGAScreenObject {
+   uint32 structSize;   // sizeof(SVGAScreenObject)
+   uint32 id;
+   uint32 flags;
+   struct {
+      uint32 width;
+      uint32 height;
+   } size;
+   struct {
+      int32 x;
+      int32 y;
+   } root;              // Only used if SVGA_SCREEN_HAS_ROOT is set.
+} SVGAScreenObject;
+
 
 /*
- *  Macros to compute variable length items (sizes in 32-bit words, except
- *  for SVGA_GLYPH_SCANLINE_SIZE, which is in bytes).
+ *  Commands in the command FIFO:
+ *
+ *  Command IDs defined below are used for the traditional 2D FIFO
+ *  communication (not all commands are available for all versions of the
+ *  SVGA FIFO protocol).
+ *
+ *  Note the holes in the command ID numbers: These commands have been
+ *  deprecated, and the old IDs must not be reused.
+ *
+ *  Command IDs from 1000 to 1999 are reserved for use by the SVGA3D
+ *  protocol.
+ *
+ *  Each command's parameters are described by the comments and
+ *  structs below.
  */
 
-#define SVGA_BITMAP_SIZE(w,h) ((((w)+31) >> 5) * (h))
-#define SVGA_BITMAP_SCANLINE_SIZE(w) (( (w)+31 ) >> 5)
-#define SVGA_PIXMAP_SIZE(w,h,bpp) ((( ((w)*(bpp))+31 ) >> 5) * (h))
-#define SVGA_PIXMAP_SCANLINE_SIZE(w,bpp) (( ((w)*(bpp))+31 ) >> 5)
-#define SVGA_GLYPH_SIZE(w,h) ((((((w) + 7) >> 3) * (h)) + 3) >> 2)
-#define SVGA_GLYPH_SCANLINE_SIZE(w) (((w) + 7) >> 3)
-#define SVGA_ESCAPE_SIZE(s) (((s) + 3) >> 2)
+typedef enum {
+   SVGA_CMD_INVALID_CMD           = 0,
+   SVGA_CMD_UPDATE                = 1,
+   SVGA_CMD_RECT_COPY             = 3,
+   SVGA_CMD_DEFINE_CURSOR         = 19,
+   SVGA_CMD_DEFINE_ALPHA_CURSOR   = 22,
+   SVGA_CMD_UPDATE_VERBOSE        = 25,
+   SVGA_CMD_FRONT_ROP_FILL        = 29,
+   SVGA_CMD_FENCE                 = 30,
+   SVGA_CMD_ESCAPE                = 33,
+   SVGA_CMD_DEFINE_SCREEN         = 34,
+   SVGA_CMD_DESTROY_SCREEN        = 35,
+   SVGA_CMD_DEFINE_GMRFB          = 36,
+   SVGA_CMD_BLIT_GMRFB_TO_SCREEN  = 37,
+   SVGA_CMD_BLIT_SCREEN_TO_GMRFB  = 38,
+   SVGA_CMD_ANNOTATION_FILL       = 39,
+   SVGA_CMD_ANNOTATION_COPY       = 40,
+   SVGA_CMD_MAX
+} SVGAFifoCmdId;
+
+#define SVGA_CMD_MAX_ARGS           64
+
 
 /*
- *  Increment from one scanline to the next of a bitmap or pixmap
+ * SVGA_CMD_UPDATE --
+ *
+ *    This is a DMA transfer which copies from the Guest Framebuffer
+ *    (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
+ *    intersect with the provided virtual rectangle.
+ *
+ *    This command does not support using arbitrary guest memory as a
+ *    data source- it only works with the pre-defined GFB memory.
+ *    This command also does not support signed virtual coordinates.
+ *    If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
+ *    negative root x/y coordinates, the negative portion of those
+ *    screens will not be reachable by this command.
+ *
+ *    This command is not necessary when using framebuffer
+ *    traces. Traces are automatically enabled if the SVGA FIFO is
+ *    disabled, and you may explicitly enable/disable traces using
+ *    SVGA_REG_TRACES. With traces enabled, any write to the GFB will
+ *    automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
+ *
+ *    Traces and SVGA_CMD_UPDATE are the only supported ways to render
+ *    pseudocolor screen updates. The newer Screen Object commands
+ *    only support true color formats.
+ *
+ * Availability:
+ *    Always available.
  */
-#define SVGA_BITMAP_INCREMENT(w) ((( (w)+31 ) >> 5) * sizeof (uint32))
-#define SVGA_PIXMAP_INCREMENT(w,bpp) ((( ((w)*(bpp))+31 ) >> 5) * sizeof (uint32))
+
+typedef
+struct {
+   uint32 x;
+   uint32 y;
+   uint32 width;
+   uint32 height;
+} SVGAFifoCmdUpdate;
+
 
 /*
- *  Transparent color for DRAW_GLYPH_CLIPPED
+ * SVGA_CMD_RECT_COPY --
+ *
+ *    Perform a rectangular DMA transfer from one area of the GFB to
+ *    another, and copy the result to any screens which intersect it.
+ *
+ * Availability:
+ *    SVGA_CAP_RECT_COPY
  */
-#define SVGA_COLOR_TRANSPARENT (~0)
+
+typedef
+struct {
+   uint32 srcX;
+   uint32 srcY;
+   uint32 destX;
+   uint32 destY;
+   uint32 width;
+   uint32 height;
+} SVGAFifoCmdRectCopy;
+
 
 /*
- *  Commands in the command FIFO
+ * SVGA_CMD_DEFINE_CURSOR --
+ *
+ *    Provide a new cursor image, as an AND/XOR mask.
+ *
+ *    The recommended way to position the cursor overlay is by using
+ *    the SVGA_FIFO_CURSOR_* registers, supported by the
+ *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
+ *
+ * Availability:
+ *    SVGA_CAP_CURSOR
  */
 
-#define	 SVGA_CMD_INVALID_CMD		   0
-	 /* FIFO layout:
-            <nothing> (well, undefined) */
+typedef
+struct {
+   uint32 id;             // Reserved, must be zero.
+   uint32 hotspotX;
+   uint32 hotspotY;
+   uint32 width;
+   uint32 height;
+   uint32 andMaskDepth;   // Value must be 1 or equal to BITS_PER_PIXEL
+   uint32 xorMaskDepth;   // Value must be 1 or equal to BITS_PER_PIXEL
+   /*
+    * Followed by scanline data for AND mask, then XOR mask.
+    * Each scanline is padded to a 32-bit boundary.
+   */
+} SVGAFifoCmdDefineCursor;
+
+
+/*
+ * SVGA_CMD_DEFINE_ALPHA_CURSOR --
+ *
+ *    Provide a new cursor image, in 32-bit BGRA format.
+ *
+ *    The recommended way to position the cursor overlay is by using
+ *    the SVGA_FIFO_CURSOR_* registers, supported by the
+ *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
+ *
+ * Availability:
+ *    SVGA_CAP_ALPHA_CURSOR
+ */
+
+typedef
+struct {
+   uint32 id;             // Reserved, must be zero.
+   uint32 hotspotX;
+   uint32 hotspotY;
+   uint32 width;
+   uint32 height;
+   /* Followed by scanline data */
+} SVGAFifoCmdDefineAlphaCursor;
+
+
+/*
+ * SVGA_CMD_UPDATE_VERBOSE --
+ *
+ *    Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
+ *    'reason' value, an opaque cookie which is used by internal
+ *    debugging tools. Third party drivers should not use this
+ *    command.
+ *
+ * Availability:
+ *    SVGA_CAP_EXTENDED_FIFO
+ */
+
+typedef
+struct {
+   uint32 x;
+   uint32 y;
+   uint32 width;
+   uint32 height;
+   uint32 reason;
+} SVGAFifoCmdUpdateVerbose;
+
+
+/*
+ * SVGA_CMD_FRONT_ROP_FILL --
+ *
+ *    This is a hint which tells the SVGA device that the driver has
+ *    just filled a rectangular region of the GFB with a solid
+ *    color. Instead of reading these pixels from the GFB, the device
+ *    can assume that they all equal 'color'. This is primarily used
+ *    for remote desktop protocols.
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_ACCELFRONT
+ */
+
+#define  SVGA_ROP_COPY                    0x03
+
+#define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
+
+typedef
+struct {
+   uint32 color;     // In the same format as the GFB
+   uint32 x;
+   uint32 y;
+   uint32 width;
+   uint32 height;
+   uint32 rop;       // Must be SVGA_ROP_COPY
+} SVGAFifoCmdFrontRopFill;
+
+
+/*
+ * SVGA_CMD_FENCE --
+ *
+ *    Insert a synchronization fence.  When the SVGA device reaches
+ *    this command, it will copy the 'fence' value into the
+ *    SVGA_FIFO_FENCE register. It will also compare the fence against
+ *    SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
+ *    SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
+ *    raise this interrupt.
+ *
+ * Availability:
+ *    SVGA_FIFO_FENCE for this command,
+ *    SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
+ */
 
-#define	 SVGA_CMD_UPDATE		   1
-	 /* FIFO layout:
-	    X, Y, Width, Height */
+typedef
+struct {
+   uint32 fence;
+} SVGAFifoCmdFence;
 
-#define	 SVGA_CMD_RECT_FILL		   2
-	 /* FIFO layout:
-	    Color, X, Y, Width, Height */
 
-#define	 SVGA_CMD_RECT_COPY		   3
-	 /* FIFO layout:
-	    Source X, Source Y, Dest X, Dest Y, Width, Height */
+/*
+ * SVGA_CMD_ESCAPE --
+ *
+ *    Send an extended or vendor-specific variable length command.
+ *    This is used for video overlay, third party plugins, and
+ *    internal debugging tools. See svga_escape.h
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_ESCAPE
+ */
 
-#define	 SVGA_CMD_DEFINE_BITMAP		   4
-	 /* FIFO layout:
-	    Pixmap ID, Width, Height, <scanlines> */
+typedef
+struct {
+   uint32 nsid;
+   uint32 size;
+   /* followed by 'size' bytes of data */
+} SVGAFifoCmdEscape;
 
-#define	 SVGA_CMD_DEFINE_BITMAP_SCANLINE   5
-	 /* FIFO layout:
-	    Pixmap ID, Width, Height, Line #, scanline */
 
-#define	 SVGA_CMD_DEFINE_PIXMAP		   6
-	 /* FIFO layout:
-	    Pixmap ID, Width, Height, Depth, <scanlines> */
+/*
+ * SVGA_CMD_DEFINE_SCREEN --
+ *
+ *    Define or redefine an SVGAScreenObject. See the description of
+ *    SVGAScreenObject above.  The video driver is responsible for
+ *    generating new screen IDs. They should be small positive
+ *    integers. The virtual device will have an implementation
+ *    specific upper limit on the number of screen IDs
+ *    supported. Drivers are responsible for recycling IDs. The first
+ *    valid ID is zero.
+ *
+ *    - Interaction with other registers:
+ *
+ *    For backwards compatibility, when the GFB mode registers (WIDTH,
+ *    HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
+ *    deletes all screens other than screen #0, and redefines screen
+ *    #0 according to the specified mode. Drivers that use
+ *    SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
+ *
+ *    If you use screen objects, do not use the legacy multi-mon
+ *    registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT
+ */
 
-#define	 SVGA_CMD_DEFINE_PIXMAP_SCANLINE   7
-	 /* FIFO layout:
-	    Pixmap ID, Width, Height, Depth, Line #, scanline */
+typedef
+struct {
+   SVGAScreenObject screen;   // Variable-length according to version
+} SVGAFifoCmdDefineScreen;
 
-#define	 SVGA_CMD_RECT_BITMAP_FILL	   8
-	 /* FIFO layout:
-	    Bitmap ID, X, Y, Width, Height, Foreground, Background */
 
-#define	 SVGA_CMD_RECT_PIXMAP_FILL	   9
-	 /* FIFO layout:
-	    Pixmap ID, X, Y, Width, Height */
+/*
+ * SVGA_CMD_DESTROY_SCREEN --
+ *
+ *    Destroy an SVGAScreenObject. Its ID is immediately available for
+ *    re-use.
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT
+ */
 
-#define	 SVGA_CMD_RECT_BITMAP_COPY	  10
-	 /* FIFO layout:
-	    Bitmap ID, Source X, Source Y, Dest X, Dest Y,
-	    Width, Height, Foreground, Background */
+typedef
+struct {
+   uint32 screenId;
+} SVGAFifoCmdDestroyScreen;
 
-#define	 SVGA_CMD_RECT_PIXMAP_COPY	  11
-	 /* FIFO layout:
-	    Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width, Height */
 
-#define	 SVGA_CMD_FREE_OBJECT		  12
-	 /* FIFO layout:
-	    Object (pixmap, bitmap, ...) ID */
+/*
+ * SVGA_CMD_DEFINE_GMRFB --
+ *
+ *    This command sets a piece of SVGA device state called the
+ *    Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
+ *    piece of light-weight state which identifies the location and
+ *    format of an image in guest memory or in BAR1. The GMRFB has
+ *    an arbitrary size, and it doesn't need to match the geometry
+ *    of the GFB or any screen object.
+ *
+ *    The GMRFB can be redefined as often as you like. You could
+ *    always use the same GMRFB, you could redefine it before
+ *    rendering from a different guest screen, or you could even
+ *    redefine it before every blit.
+ *
+ *    There are multiple ways to use this command. The simplest way is
+ *    to use it to move the framebuffer either to elsewhere in the GFB
+ *    (BAR1) memory region, or to a user-defined GMR. This lets a
+ *    driver use a framebuffer allocated entirely out of normal system
+ *    memory, which we encourage.
+ *
+ *    Another way to use this command is to set up a ring buffer of
+ *    updates in GFB memory. If a driver wants to ensure that no
+ *    frames are skipped by the SVGA device, it is important that the
+ *    driver not modify the source data for a blit until the device is
+ *    done processing the command. One efficient way to accomplish
+ *    this is to use a ring of small DMA buffers. Each buffer is used
+ *    for one blit, then we move on to the next buffer in the
+ *    ring. The FENCE mechanism is used to protect each buffer from
+ *    re-use until the device is finished with that buffer's
+ *    corresponding blit.
+ *
+ *    This command does not affect the meaning of SVGA_CMD_UPDATE.
+ *    UPDATEs always occur from the legacy GFB memory area. This
+ *    command has no support for pseudocolor GMRFBs. Currently only
+ *    true-color 15, 16, and 24-bit depths are supported. Future
+ *    devices may expose capabilities for additional framebuffer
+ *    formats.
+ *
+ *    The default GMRFB value is undefined. Drivers must always send
+ *    this command at least once before performing any blit from the
+ *    GMRFB.
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT
+ */
 
-#define	 SVGA_CMD_RECT_ROP_FILL           13
-         /* FIFO layout:
-            Color, X, Y, Width, Height, ROP */
+typedef
+struct {
+   SVGAGuestPtr        ptr;
+   uint32              bytesPerLine;
+   SVGAGMRImageFormat  format;
+} SVGAFifoCmdDefineGMRFB;
 
-#define	 SVGA_CMD_RECT_ROP_COPY           14
-         /* FIFO layout:
-            Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
 
-#define	 SVGA_CMD_RECT_ROP_BITMAP_FILL    15
-         /* FIFO layout:
-            ID, X, Y, Width, Height, Foreground, Background, ROP */
+/*
+ * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
+ *
+ *    This is a guest-to-host blit. It performs a DMA operation to
+ *    copy a rectangular region of pixels from the current GMRFB to
+ *    one or more Screen Objects.
+ *
+ *    The destination coordinate may be specified relative to a
+ *    screen's origin (if a screen ID is specified) or relative to the
+ *    virtual coordinate system's origin (if the screen ID is
+ *    SVGA_ID_INVALID). The actual destination may span zero or more
+ *    screens, in the case of a virtual destination rect or a rect
+ *    which extends off the edge of the specified screen.
+ *
+ *    This command writes to the screen's "base layer": the underlying
+ *    framebuffer which exists below any cursor or video overlays. No
+ *    action is necessary to explicitly hide or update any overlays
+ *    which exist on top of the updated region.
+ *
+ *    The SVGA device is guaranteed to finish reading from the GMRFB
+ *    by the time any subsequent FENCE commands are reached.
+ *
+ *    This command consumes an annotation. See the
+ *    SVGA_CMD_ANNOTATION_* commands for details.
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT
+ */
 
-#define	 SVGA_CMD_RECT_ROP_PIXMAP_FILL    16
-         /* FIFO layout:
-            ID, X, Y, Width, Height, ROP */
+typedef
+struct {
+   SVGASignedPoint  srcOrigin;
+   SVGASignedRect   destRect;
+   uint32           destScreenId;
+} SVGAFifoCmdBlitGMRFBToScreen;
 
-#define	 SVGA_CMD_RECT_ROP_BITMAP_COPY    17
-         /* FIFO layout:
-            ID, Source X, Source Y,
-            Dest X, Dest Y, Width, Height, Foreground, Background, ROP */
 
-#define	 SVGA_CMD_RECT_ROP_PIXMAP_COPY    18
-         /* FIFO layout:
-            ID, Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
+/*
+ * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
+ *
+ *    This is a host-to-guest blit. It performs a DMA operation to
+ *    copy a rectangular region of pixels from a single Screen Object
+ *    back to the current GMRFB.
+ *
+ *    Usage note: This command should be used rarely. It will
+ *    typically be inefficient, but it is necessary for some types of
+ *    synchronization between 3D (GPU) and 2D (CPU) rendering into
+ *    overlapping areas of a screen.
+ *
+ *    The source coordinate is specified relative to a screen's
+ *    origin. The provided screen ID must be valid. If any parameters
+ *    are invalid, the resulting pixel values are undefined.
+ *
+ *    This command reads the screen's "base layer". Overlays like
+ *    video and cursor are not included, but any data which was sent
+ *    using a blit-to-screen primitive will be available, no matter
+ *    whether the data's original source was the GMRFB or the 3D
+ *    acceleration hardware.
+ *
+ *    Note that our guest-to-host blits and host-to-guest blits aren't
+ *    symmetric in their current implementation. While the parameters
+ *    are identical, host-to-guest blits are a lot less featureful.
+ *    They do not support clipping: If the source parameters don't
+ *    fully fit within a screen, the blit fails. They must originate
+ *    from exactly one screen. Virtual coordinates are not directly
+ *    supported.
+ *
+ *    Host-to-guest blits do support the same set of GMRFB formats
+ *    offered by guest-to-host blits.
+ *
+ *    The SVGA device is guaranteed to finish writing to the GMRFB by
+ *    the time any subsequent FENCE commands are reached.
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT
+ */
 
-#define	SVGA_CMD_DEFINE_CURSOR		  19
-	/* FIFO layout:
-	   ID, Hotspot X, Hotspot Y, Width, Height,
-	   Depth for AND mask, Depth for XOR mask,
-	   <scanlines for AND mask>, <scanlines for XOR mask> */
+typedef
+struct {
+   SVGASignedPoint  destOrigin;
+   SVGASignedRect   srcRect;
+   uint32           srcScreenId;
+} SVGAFifoCmdBlitScreenToGMRFB;
 
-#define	SVGA_CMD_DISPLAY_CURSOR		  20
-	/* FIFO layout:
-	   ID, On/Off (1 or 0) */
 
-#define	SVGA_CMD_MOVE_CURSOR		  21
-	/* FIFO layout:
-	   X, Y */
+/*
+ * SVGA_CMD_ANNOTATION_FILL --
+ *
+ *    This is a blit annotation. This command stores a small piece of
+ *    device state which is consumed by the next blit-to-screen
+ *    command. The state is only cleared by commands which are
+ *    specifically documented as consuming an annotation. Other
+ *    commands (such as ESCAPEs for debugging) may intervene between
+ *    the annotation and its associated blit.
+ *
+ *    This annotation is a promise about the contents of the next
+ *    blit: The video driver is guaranteeing that all pixels in that
+ *    blit will have the same value, specified here as a color in
+ *    SVGAColorBGRX format.
+ *
+ *    The SVGA device can still render the blit correctly even if it
+ *    ignores this annotation, but the annotation may allow it to
+ *    perform the blit more efficiently, for example by ignoring the
+ *    source data and performing a fill in hardware.
+ *
+ *    This annotation is most important for performance when the
+ *    user's display is being remoted over a network connection.
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT
+ */
 
-#define SVGA_CMD_DEFINE_ALPHA_CURSOR      22
-	/* FIFO layout:
-	   ID, Hotspot X, Hotspot Y, Width, Height,
-	   <scanlines> */
+typedef
+struct {
+   SVGAColorBGRX  color;
+} SVGAFifoCmdAnnotationFill;
 
-#define SVGA_CMD_DRAW_GLYPH               23
-	/* FIFO layout:
-	   X, Y, W, H, FGCOLOR, <stencil buffer> */
-
-#define SVGA_CMD_DRAW_GLYPH_CLIPPED       24
-	/* FIFO layout:
-	   X, Y, W, H, FGCOLOR, BGCOLOR, <cliprect>, <stencil buffer>
-           Transparent color expands are done by setting BGCOLOR to ~0 */
-
-#define	SVGA_CMD_UPDATE_VERBOSE	          25
-        /* FIFO layout:
-	   X, Y, Width, Height, Reason */
-
-#define SVGA_CMD_SURFACE_FILL             26
-        /* FIFO layout:
-	   color, dstSurfaceOffset, x, y, w, h, rop */
-
-#define SVGA_CMD_SURFACE_COPY             27
-        /* FIFO layout:
-	   srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
-           destX, destY, w, h, rop */
-
-#define SVGA_CMD_SURFACE_ALPHA_BLEND      28
-        /* FIFO layout:
-	   srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
-           destX, destY, w, h, op (SVGA_BLENDOP*), flags (SVGA_BLENDFLAGS*), 
-           param1, param2 */
-
-#define	 SVGA_CMD_FRONT_ROP_FILL          29
-         /* FIFO layout:
-            Color, X, Y, Width, Height, ROP */
-
-#define	 SVGA_CMD_FENCE                   30
-         /* FIFO layout:
-            Fence value */
-
-#define SVGA_CMD_VIDEO_PLAY_OBSOLETE      31
-         /* Obsolete; do not use. */
- 
-#define SVGA_CMD_VIDEO_END_OBSOLETE       32
-         /* Obsolete; do not use. */
-
-#define SVGA_CMD_ESCAPE                   33
-         /* FIFO layout:
-            Namespace ID, size(bytes), data */
-
-#define	SVGA_CMD_MAX                      34
-
-#define SVGA_CMD_MAX_ARGS                 64
-
-/*
- * Location and size of SVGA frame buffer and the FIFO.
- */
-#define SVGA_VRAM_MIN_SIZE   (4 * 640 * 480)  /* bytes */
-#define SVGA_VRAM_MAX_SIZE   (128 * 1024 * 1024)
-
-#define SVGA_VRAM_SIZE_WS       (16 * 1024 * 1024) /* 16 MB */
-#define SVGA_MEM_SIZE_WS        (2  * 1024 * 1024) /* 2  MB */
-#define SVGA_VRAM_SIZE_SERVER   (4  * 1024 * 1024) /* 4  MB */
-#define SVGA_MEM_SIZE_SERVER    (256 * 1024)       /* 256 KB */
-
-#if /* defined(VMX86_WGS) || */ defined(VMX86_SERVER)
-#define SVGA_VRAM_SIZE         SVGA_VRAM_SIZE_SERVER
-#define SVGA_MEM_SIZE          SVGA_MEM_SIZE_SERVER
-#else
-#define SVGA_VRAM_SIZE         SVGA_VRAM_SIZE_WS
-#define SVGA_MEM_SIZE          SVGA_MEM_SIZE_WS
-#endif
 
 /*
- * SVGA_FB_START is the default starting address of the SVGA frame
- * buffer in the guest's physical address space.
- * SVGA_FB_START_BIGMEM is the starting address of the SVGA frame
- * buffer for VMs that have a large amount of physical memory.
- *
- * The address of SVGA_FB_START is set to 2GB - (SVGA_FB_MAX_SIZE + SVGA_MEM_SIZE), 
- * thus the SVGA frame buffer sits at [SVGA_FB_START .. 2GB-1] in the
- * physical address space.  Our older SVGA drivers for NT treat the
- * address of the frame buffer as a signed integer.  For backwards
- * compatibility, we keep the default location of the frame buffer
- * at under 2GB in the address space.  This restricts VMs to have "only"
- * up to ~2031MB (i.e., up to SVGA_FB_START) of physical memory.
- *
- * For VMs that want more memory than the ~2031MB, we place the SVGA
- * frame buffer at SVGA_FB_START_BIGMEM.  This allows VMs to have up
- * to 3584MB, at least as far as the SVGA frame buffer is concerned
- * (note that there may be other issues that limit the VM memory
- * size).  PCI devices use high memory addresses, so we have to put
- * SVGA_FB_START_BIGMEM low enough so that it doesn't overlap with any
- * of these devices.  Placing SVGA_FB_START_BIGMEM at 0xE0000000
- * should leave plenty of room for the PCI devices.
- *
- * NOTE: All of that is only true for the 0710 chipset.  As of the 0405
- * chipset, the framebuffer start is determined solely based on the value
- * the guest BIOS or OS programs into the PCI base address registers.
- */
-#define SVGA_FB_LEGACY_START		0x7EFC0000
-#define SVGA_FB_LEGACY_START_BIGMEM	0xE0000000
+ * SVGA_CMD_ANNOTATION_COPY --
+ *
+ *    This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
+ *    information about annotations.
+ *
+ *    This annotation is a promise about the contents of the next
+ *    blit: The video driver is guaranteeing that all pixels in that
+ *    blit will have the same value as those which already exist at an
+ *    identically-sized region on the same or a different screen.
+ *
+ *    Note that the source pixels for the COPY in this annotation are
+ *    sampled before applying the anqnotation's associated blit. They
+ *    are allowed to overlap with the blit's destination pixels.
+ *
+ *    The copy source rectangle is specified the same way as the blit
+ *    destination: it can be a rectangle which spans zero or more
+ *    screens, specified relative to either a screen or to the virtual
+ *    coordinate system's origin. If the source rectangle includes
+ *    pixels which are not from exactly one screen, the results are
+ *    undefined.
+ *
+ * Availability:
+ *    SVGA_FIFO_CAP_SCREEN_OBJECT
+ */
+
+typedef
+struct {
+   SVGASignedPoint  srcOrigin;
+   uint32           srcScreenId;
+} SVGAFifoCmdAnnotationCopy;
 
 #endif