diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2022-01-02 03:41:09 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2022-01-02 03:41:09 +0000 |
| commit | 11cb66a0724a4db8d160d16ca7e626c43938b3e6 (patch) | |
| tree | 42687e11ea2bc53060d43689c707f10b9d0ea257 | |
| parent | b2d5afcb804124bd4c6f10ba9bb744c6984bd93e (diff) | |
addres -> address
| -rw-r--r-- | sys/arch/i386/i386/acpi_wakecode.S | 2 | ||||
| -rw-r--r-- | sys/arch/riscv64/riscv64/locore.S | 4 | ||||
| -rw-r--r-- | sys/dev/pci/if_skreg.h | 4 | ||||
| -rw-r--r-- | sys/dev/pci/pci.c | 4 |
4 files changed, 7 insertions, 7 deletions
diff --git a/sys/arch/i386/i386/acpi_wakecode.S b/sys/arch/i386/i386/acpi_wakecode.S index 3bab0535fce..f0bd7338920 100644 --- a/sys/arch/i386/i386/acpi_wakecode.S +++ b/sys/arch/i386/i386/acpi_wakecode.S @@ -157,7 +157,7 @@ _ACPI_TRMP_OFFSET(.Lacpi_s3_vector_real) * Force CPU into protected mode * by making an intersegment jump (to ourselves, just a few lines * down from here. We rely on the kernel to fixup the jump - * target addres previously. + * target address previously. * */ ljmpl $0x8, $.Lacpi_protected_mode_trampoline diff --git a/sys/arch/riscv64/riscv64/locore.S b/sys/arch/riscv64/riscv64/locore.S index adfb81cd551..f454768b481 100644 --- a/sys/arch/riscv64/riscv64/locore.S +++ b/sys/arch/riscv64/riscv64/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.13 2021/07/02 10:42:22 kettenis Exp $ */ +/* $OpenBSD: locore.S,v 1.14 2022/01/02 03:41:08 jsg Exp $ */ /*- * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> @@ -208,7 +208,7 @@ va: sd t0, RISCV_BOOTPARAMS_DTBP_VIRT(sp) sd a1, RISCV_BOOTPARAMS_DTBP_PHYS(sp) - /* Set esym to virtual addres of symbol table end */ + /* Set esym to virtual address of symbol table end */ lla t0, esym sub t1, a0, s9 li t2, KERNBASE diff --git a/sys/dev/pci/if_skreg.h b/sys/dev/pci/if_skreg.h index 6caa99126a1..48d553b3aa4 100644 --- a/sys/dev/pci/if_skreg.h +++ b/sys/dev/pci/if_skreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: if_skreg.h,v 1.61 2017/04/08 03:36:50 jmatthew Exp $ */ +/* $OpenBSD: if_skreg.h,v 1.62 2022/01/02 03:41:08 jsg Exp $ */ /* * Copyright (c) 1997, 1998, 1999, 2000 @@ -1821,7 +1821,7 @@ struct msk_status_desc { /* SMI Data Register (SMIDR) */ #define YUKON_SMIDR 0x0084 -/* PHY Addres Register (PAR) */ +/* PHY Address Register (PAR) */ #define YUKON_PAR 0x0088 #define YU_PAR_MIB_CLR 0x0020 /* MIB Counters Clear Mode */ diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c index 14f91e51408..43a73bf666d 100644 --- a/sys/dev/pci/pci.c +++ b/sys/dev/pci/pci.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pci.c,v 1.120 2021/07/23 00:29:14 jmatthew Exp $ */ +/* $OpenBSD: pci.c,v 1.121 2022/01/02 03:41:08 jsg Exp $ */ /* $NetBSD: pci.c,v 1.31 1997/06/06 23:48:04 thorpej Exp $ */ /* @@ -1353,7 +1353,7 @@ pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) splx(s); /* - * Section 6.2.5.2 `Expansion ROM Base Addres Register', + * Section 6.2.5.2 `Expansion ROM Base Address Register', * * tells us that only the upper 21 bits are writable. * This means that the size of a ROM must be a |