Modified to use mii layer for hme

9 files changed, 186 insertions, 801 deletions

diff --git a/sys/arch/sparc/conf/GENERIC b/sys/arch/sparc/conf/GENERIC
index 50294904ca0..63ac9a13eb0 100644
--- a/sys/arch/sparc/conf/GENERIC
+++ b/sys/arch/sparc/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.31 1998/07/11 05:44:02 deraadt Exp $
+#	$OpenBSD: GENERIC,v 1.32 1998/09/10 17:34:30 jason Exp $
 # 	$NetBSD: GENERIC,v 1.48 1997/08/23 19:19:01 mjacob Exp $
 
 # Machine architecture; required by config(8)
@@ -161,6 +161,10 @@ ie4	at vmes0 addr 0xff2dff02 level 5 vect 0x7c
 # HappyMeal ethernet
 hme*	at sbus? slot ? offset ?
 
+# Media Independent Interface (mii) drivers
+nsphy*	at mii? phy ?				# NS and compatible PHYs
+qsphy*	at mii? phy ?				# Quality Semi QS6612 PHYs
+
 # Xylogics 753 or 7053 VME SMD disk controllers and disks, found
 # on sun4 systems.
 xdc0	at vmel0 addr 0xffffee80 level 3 vect 0x44
diff --git a/sys/arch/sparc/conf/GENERIC_SCSI3 b/sys/arch/sparc/conf/GENERIC_SCSI3
index ad345f77267..511f9c16edc 100644
--- a/sys/arch/sparc/conf/GENERIC_SCSI3
+++ b/sys/arch/sparc/conf/GENERIC_SCSI3
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC_SCSI3,v 1.21 1998/05/22 08:25:29 deraadt Exp $
+#	$OpenBSD: GENERIC_SCSI3,v 1.22 1998/09/10 17:34:30 jason Exp $
 # 	$NetBSD: GENERIC,v 1.28.2.1 1996/07/02 23:55:22 jtc Exp $
 
 # Machine architecture; required by config(8)
@@ -149,6 +149,13 @@ ie2	at vmes0 addr 0xff31ff02 level 5 vect 0x76
 ie3	at vmes0 addr 0xff35ff02 level 5 vect 0x77
 ie4	at vmes0 addr 0xff2dff02 level 5 vect 0x7c
 
+# HappyMeal ethernet
+hme*	at sbus? slot ? offset ?
+
+# Media Independent Interface (mii) drivers
+nsphy*	at mii? phy ?				# NS and compatible PHYs
+qsphy*	at mii? phy ?				# Quality Semi QS6612 PHYs
+
 # Xylogics 753 or 7053 VME SMD disk controllers and disks, found
 # on sun4 systems.
 xdc0	at vmel0 addr 0xffffee80 level 3 vect 0x44
diff --git a/sys/arch/sparc/conf/RAMDISK b/sys/arch/sparc/conf/RAMDISK
index 919d54b8d29..6b517c9143a 100644
--- a/sys/arch/sparc/conf/RAMDISK
+++ b/sys/arch/sparc/conf/RAMDISK
@@ -160,6 +160,10 @@ ie0	at obio0 addr 0x06000000 level 6		# sun4/100 on-board
 # HappyMeal ethernet
 hme*	at sbus? slot ? offset ?
 
+# Media Independent Interface (mii) drivers
+nsphy*	at mii? phy ?				# NS and compatible PHYs
+qsphy*	at mii? phy ?				# Quality Semi QS6612 PHYs
+
 ie1	at vmes0 addr 0xffe88000 level 5 vect 0x75
 ie2	at vmes0 addr 0xff31ff02 level 5 vect 0x76
 ie3	at vmes0 addr 0xff35ff02 level 5 vect 0x77
diff --git a/sys/arch/sparc/conf/SUN4C b/sys/arch/sparc/conf/SUN4C
index c39c33d9fd1..f4a6196adb4 100644
--- a/sys/arch/sparc/conf/SUN4C
+++ b/sys/arch/sparc/conf/SUN4C
@@ -109,6 +109,10 @@ le*	at sbus? slot ? offset ?
 # HappyMeal ethernet
 hme*	at sbus? slot ? offset ?
 
+# Media Independent Interface (mii) drivers
+nsphy*	at mii? phy ?				# NS and compatible PHYs
+qsphy*	at mii? phy ?				# Quality Semi QS6612 PHYs
+
 #ie0	at obio0 addr 0xf6000000 level 6
 #ie0	at obio0 addr 0x06000000 level 6		# 4/100
 #ie1	at vmes0 addr 0xffe88000 level 5 vect 0x75
diff --git a/sys/arch/sparc/conf/SUN4M b/sys/arch/sparc/conf/SUN4M
index 53a8cc08ceb..3738f6ff3c2 100644
--- a/sys/arch/sparc/conf/SUN4M
+++ b/sys/arch/sparc/conf/SUN4M
@@ -1,4 +1,4 @@
-#	$OpenBSD: SUN4M,v 1.22 1998/07/10 19:20:09 jason Exp $
+#	$OpenBSD: SUN4M,v 1.23 1998/09/10 17:34:31 jason Exp $
 # 	$NetBSD: GENERIC,v 1.28.2.1 1996/07/02 23:55:22 jtc Exp $
 
 # Machine architecture; required by config(8)
@@ -90,6 +90,10 @@ le*	at lebuffer?					#
 # HappyMeal ethernet
 hme*	at sbus? slot ? offset ?
 
+# Media Independent Interface (mii) drivers
+nsphy*	at mii? phy ?				# NS and compatible PHYs
+qsphy*	at mii? phy ?				# Quality Semi QS6612 PHYs
+
 # Sun "bwtwo" black and white framebuffer, found on sun4, sun4c, and sun4m
 # systems.  If your sun4 system has a cgfour installed in the P4 slot,
 # the P4 entries for "bwtwo" will attach to the overlay plane of the
diff --git a/sys/arch/sparc/conf/files.sparc b/sys/arch/sparc/conf/files.sparc
index 9775c739b3d..ca77b4731e4 100644
--- a/sys/arch/sparc/conf/files.sparc
+++ b/sys/arch/sparc/conf/files.sparc
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.sparc,v 1.21 1998/09/01 17:36:58 jason Exp $
+#	$OpenBSD: files.sparc,v 1.22 1998/09/10 17:34:31 jason Exp $
 #	$NetBSD: files.sparc,v 1.44 1997/08/31 21:29:16 pk Exp $
 
 # @(#)files.sparc	8.1 (Berkeley) 7/19/93
@@ -76,6 +76,10 @@ device sbus { slot = -1, offset = -1 }
 attach sbus at mainbus, iommu
 file	arch/sparc/dev/sbus.c			sbus
 
+#
+# Media Indepedent Interface (mii)
+#
+include "../../../dev/mii/files.mii"
 
 #
 # Machine-independent SCSI drivers
@@ -114,7 +118,7 @@ attach	me at qec
 file	arch/sparc/dev/me.c		me
 
 # HappyMeal (hme) ethernet
-device hme
+device hme: ifnet, ether, mii
 attach hme at sbus
 file	arch/sparc/dev/hme.c		hme
 
diff --git a/sys/arch/sparc/dev/hme.c b/sys/arch/sparc/dev/hme.c
index 5dbd3de4002..cdb86d6638e 100644
--- a/sys/arch/sparc/dev/hme.c
+++ b/sys/arch/sparc/dev/hme.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: hme.c,v 1.7 1998/09/09 19:23:34 jason Exp $	*/
+/*	$OpenBSD: hme.c,v 1.8 1998/09/10 17:34:32 jason Exp $	*/
 
 /*
  * Copyright (c) 1998 Jason L. Wright (jason@thought.net)
@@ -73,6 +73,8 @@
 #include <sparc/sparc/cpuvar.h>
 #include <sparc/dev/sbusvar.h>
 #include <sparc/dev/dmareg.h>	/* for SBUS_BURST_* */
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
 #include <sparc/dev/hmereg.h>
 #include <sparc/dev/hmevar.h>
 
@@ -87,16 +89,8 @@ void	hmestop		__P((struct hme_softc *));
 void	hmeinit		__P((struct hme_softc *));
 void	hme_meminit	__P((struct hme_softc *));
 
-static void	hme_tcvr_write	    __P((struct hme_softc *, int reg,
-					u_short val));
-static int	hme_tcvr_read	    __P((struct hme_softc *, int reg));
-static void	hme_tcvr_bb_write   __P((struct hme_softc *, int reg,
-					u_short val));
-static int	hme_tcvr_bb_read    __P((struct hme_softc *, int reg));
-static void	hme_tcvr_bb_writeb  __P((struct hme_softc *, int b));
-static int	hme_tcvr_bb_readb   __P((struct hme_softc *));
-static void	hme_tcvr_check	    __P((struct hme_softc *));
-static int	hme_tcvr_reset	    __P((struct hme_softc *));
+static void	hme_tcvr_bb_writeb  __P((struct hme_softc *, int));
+static int	hme_tcvr_bb_readb   __P((struct hme_softc *, int));
 
 static void	hme_poll_stop	__P((struct hme_softc *sc));
 
@@ -105,11 +99,6 @@ static int	hme_tint	__P((struct hme_softc *));
 static int	hme_mint	__P((struct hme_softc *, u_int32_t));
 static int	hme_eint	__P((struct hme_softc *, u_int32_t));
 
-static void	hme_auto_negotiate __P((struct hme_softc *));
-static void	hme_negotiate_watchdog __P((void *));
-static void	hme_print_link_mode __P((struct hme_softc *));
-static void	hme_set_initial_advertisement	__P((struct hme_softc *));
-
 static void	hme_reset_rx		__P((struct hme_softc *));
 static void	hme_reset_tx		__P((struct hme_softc *));
 
@@ -117,8 +106,18 @@ static struct mbuf *	hme_get __P((struct hme_softc *, int, int));
 static void		hme_read __P((struct hme_softc *, int, int));
 static int		hme_put __P((struct hme_softc *, int, struct mbuf *));
 
-static int	hme_ifmedia_upd __P((struct ifnet *));
-static void	hme_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
+/*
+ * ifmedia glue
+ */
+static int	hme_mediachange __P((struct ifnet *));
+static void	hme_mediastatus __P((struct ifnet *, struct ifmediareq *));
+
+/*
+ * mii glue
+ */
+static int	hme_mii_read __P((struct device *, int, int));
+static void	hme_mii_write __P((struct device *, int, int, int));
+static void	hme_mii_statchg __P((struct device *));
 
 static void	hme_mcreset __P((struct hme_softc *));
 
@@ -195,8 +194,6 @@ hmeattach(parent, self, aux)
 
 	hme_meminit(sc);
 
-	hme_set_initial_advertisement(sc);
-
 	sbus_establish(&sc->sc_sd, &sc->sc_dev);
 
 	sc->sc_ih.ih_fun = hmeintr;
@@ -212,6 +209,18 @@ hmeattach(parent, self, aux)
 		myetheraddr(sc->sc_arpcom.ac_enaddr);
 	}
 
+	printf(" pri %d: address %s rev %d\n", pri,
+		ether_sprintf(sc->sc_arpcom.ac_enaddr), sc->sc_rev);
+
+	sc->sc_mii.mii_ifp = ifp;
+	sc->sc_mii.mii_readreg = hme_mii_read;
+	sc->sc_mii.mii_writereg = hme_mii_write;
+	sc->sc_mii.mii_statchg = hme_mii_statchg;
+	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, hme_mediachange,
+	    hme_mediastatus);
+	mii_phy_probe(self, &sc->sc_mii, 0xffffffff);
+	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE);
+
 	bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_start = hmestart;
@@ -224,12 +233,6 @@ hmeattach(parent, self, aux)
 	if_attach(ifp);
 	ether_ifattach(ifp);
 
-	sc->sc_an_state = HME_TIMER_DONE;
-	sc->sc_an_ticks = 0;
-
-	printf(" pri %d: address %s rev %d\n", pri,
-		ether_sprintf(sc->sc_arpcom.ac_enaddr), sc->sc_rev);
-
 #if NBPFILTER > 0
 	bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header));
 #endif
@@ -308,6 +311,7 @@ hmestop(sc)
 		DELAY(20);
 	if (tries == MAX_STOP_TRIES)
 		printf("%s: stop failed\n", sc->sc_dev.dv_xname);
+	sc->sc_mii.mii_media_status &= ~IFM_ACTIVE;
 }
 
 /*
@@ -443,7 +447,7 @@ hmeioctl(ifp, cmd, data)
 		break;
 	case SIOCGIFMEDIA:
 	case SIOCSIFMEDIA:
-		error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
+		error = ifmedia_ioctl(ifp, ifr,  &sc->sc_mii.mii_media, cmd);
 		break;
 	default:
 		error = EINVAL;
@@ -514,20 +518,6 @@ hmeinit(sc)
 	else
 		tcvr->cfg = c | TCVR_CFG_BENABLE;
 
-	hme_tcvr_check(sc);
-	switch (sc->sc_tcvr_type) {
-	case HME_TCVR_NONE:
-		printf("%s: no transceiver type!\n", sc->sc_dev.dv_xname);
-		return;
-	case HME_TCVR_INTERNAL:
-		cr->xif_cfg = 0;
-		break;
-	case HME_TCVR_EXTERNAL:
-		cr->xif_cfg = CR_XCFG_MIIDISAB;
-		break;
-	}
-	hme_tcvr_reset(sc);
-
 	hme_reset_tx(sc);
 	hme_reset_rx(sc);
 
@@ -588,242 +578,17 @@ hmeinit(sc)
 	cr->rx_cfg = CR_RXCFG_HENABLE;
 	DELAY(10);
 
-	c = CR_TXCFG_DGIVEUP;
-	if (sc->sc_flags & HME_FLAG_FULL)
-		c |= CR_TXCFG_FULLDPLX;
-	cr->tx_cfg = c;
+	cr->tx_cfg |= CR_TXCFG_DGIVEUP;
 
 	c = CR_XCFG_ODENABLE;
 	if (sc->sc_flags & HME_FLAG_LANCE)
 		c |= (HME_DEFAULT_IPKT_GAP0 << 5) | CR_XCFG_LANCE;
-	if (sc->sc_tcvr_type == HME_TCVR_EXTERNAL)
-		c |= CR_XCFG_MIIDISAB;
 	cr->xif_cfg = c;
 
 	cr->tx_cfg |= CR_TXCFG_ENABLE;	/* enable tx */
 	cr->rx_cfg |= CR_RXCFG_ENABLE;	/* enable rx */
 
-	hme_ifmedia_upd(&sc->sc_arpcom.ac_if);
-}
-
-static void
-hme_set_initial_advertisement(sc)
-	struct hme_softc *sc;
-{
-	hmestop(sc);
-	sc->sc_tcvr->int_mask = 0xffff;
-	if (sc->sc_flags & HME_FLAG_FENABLE)
-		sc->sc_tcvr->cfg &= ~(TCVR_CFG_BENABLE);
-	else
-		sc->sc_tcvr->cfg |= TCVR_CFG_BENABLE;
-
-	hme_tcvr_check(sc);
-	switch (sc->sc_tcvr_type) {
-	case HME_TCVR_NONE:
-		return;
-	case HME_TCVR_INTERNAL:
-		sc->sc_cr->xif_cfg = 0;
-		break;
-	case HME_TCVR_EXTERNAL:
-		sc->sc_cr->xif_cfg = CR_XCFG_MIIDISAB;
-		break;
-	}
-	if (hme_tcvr_reset(sc))
-		return;
-
-	/* grab the supported modes and advertised modes */
-	sc->sc_sw.bmsr = hme_tcvr_read(sc, DP83840_BMSR);
-	sc->sc_sw.anar = hme_tcvr_read(sc, DP83840_ANAR);
-
-	ifmedia_init(&sc->sc_ifmedia, 0, hme_ifmedia_upd, hme_ifmedia_sts);
-
-	/* If 10BaseT Half duplex supported, advertise it, and so on... */
-	if (sc->sc_sw.bmsr & BMSR_10BASET_HALF) {
-		ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
-		ifmedia_add(&sc->sc_ifmedia,
-		    IFM_ETHER | IFM_10_T | IFM_HDX, 0, NULL);
-		sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
-		sc->sc_sw.anar |= ANAR_10;
-	}
-	else
-		sc->sc_sw.anar &= ~(ANAR_10);
-
-	if (sc->sc_sw.bmsr & BMSR_10BASET_FULL) {
-		ifmedia_add(&sc->sc_ifmedia,
-		    IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
-		sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
-		sc->sc_sw.anar |= ANAR_10_FD;
-	}
-	else
-		sc->sc_sw.anar &= ~(ANAR_10_FD);
-
-	if (sc->sc_sw.bmsr & BMSR_100BASETX_HALF) {
-		ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
-		ifmedia_add(&sc->sc_ifmedia,
-		    IFM_ETHER | IFM_100_TX | IFM_HDX, 0, NULL);
-		sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
-		sc->sc_sw.anar |= ANAR_TX;
-	}
-	else
-		sc->sc_sw.anar &= ~(ANAR_TX);
-
-	if (sc->sc_sw.bmsr & BMSR_100BASETX_FULL) {
-		ifmedia_add(&sc->sc_ifmedia,
-		    IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
-		sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
-		sc->sc_sw.anar |= ANAR_TX_FD;
-	}
-	else
-		sc->sc_sw.anar &= ~(ANAR_TX_FD);
-
-	if (sc->sc_sw.bmsr & BMSR_ANC) {
-		ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
-		sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
-	}
-
-	ifmedia_set(&sc->sc_ifmedia, sc->sc_ifmedia.ifm_media);
-
-	/* Inform card about what it should advertise */
-	hme_tcvr_write(sc, DP83840_ANAR, sc->sc_sw.anar);
-}
-
-#define XCVR_RESET_TRIES	16
-#define XCVR_UNISOLATE_TRIES	32
-
-static int
-hme_tcvr_reset(sc)
-	struct hme_softc *sc;
-{
-	struct hme_tcvr *tcvr = sc->sc_tcvr;
-	u_int32_t cfg;
-	int result, tries = XCVR_RESET_TRIES;
-
-	cfg = tcvr->cfg;
-	if (sc->sc_tcvr_type == HME_TCVR_EXTERNAL) {
-		tcvr->cfg = cfg & ~(TCVR_CFG_PSELECT);
-		sc->sc_tcvr_type = HME_TCVR_INTERNAL;
-		sc->sc_phyaddr = TCVR_PHYADDR_ITX;
-		hme_tcvr_write(sc, DP83840_BMCR,
-			(BMCR_LOOPBACK | BMCR_PDOWN | BMCR_ISOLATE));
-		result = hme_tcvr_read(sc, DP83840_BMCR);
-		if (result == TCVR_FAILURE) {
-			printf("%s: tcvr_reset failed\n", sc->sc_dev.dv_xname);
-			return -1;
-		}
-		tcvr->cfg = cfg | TCVR_CFG_PSELECT;
-		sc->sc_tcvr_type = HME_TCVR_EXTERNAL;
-		sc->sc_phyaddr = TCVR_PHYADDR_ETX;
-	}
-	else {
-		if (cfg & TCVR_CFG_MDIO1) {
-			tcvr->cfg = cfg | TCVR_CFG_PSELECT;
-			hme_tcvr_write(sc, DP83840_BMCR,
-				(BMCR_LOOPBACK | BMCR_PDOWN | BMCR_ISOLATE));
-			result = hme_tcvr_read(sc, DP83840_BMCR);
-			if (result == TCVR_FAILURE) {
-				printf("%s: tcvr_reset failed\n",
-					sc->sc_dev.dv_xname);
-				return -1;
-			}
-			tcvr->cfg = cfg & ~(TCVR_CFG_PSELECT);
-			sc->sc_tcvr_type = HME_TCVR_INTERNAL;
-			sc->sc_phyaddr = TCVR_PHYADDR_ITX;
-		}
-	}
-
-	hme_tcvr_write(sc, DP83840_BMCR, BMCR_RESET);
-
-	while (--tries) {
-		result = hme_tcvr_read(sc, DP83840_BMCR);
-		if (result == TCVR_FAILURE)
-			return -1;
-		sc->sc_sw.bmcr = result;
-		if (!(result & BMCR_RESET))
-			break;
-		DELAY(20);
-	}
-	if (!tries) {
-		printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname);
-		return -1;
-	}
-
-	sc->sc_sw.bmsr = hme_tcvr_read(sc, DP83840_BMSR);
-	sc->sc_sw.phyidr1 = hme_tcvr_read(sc, DP83840_PHYIDR1);
-	sc->sc_sw.phyidr2 = hme_tcvr_read(sc, DP83840_PHYIDR2);
-	sc->sc_sw.anar = hme_tcvr_read(sc, DP83840_BMSR);
-
-	sc->sc_sw.bmcr &= ~(BMCR_ISOLATE);
-	hme_tcvr_write(sc, DP83840_BMCR, sc->sc_sw.bmcr);
-
-	tries = XCVR_UNISOLATE_TRIES;
-	while (--tries) {
-		result = hme_tcvr_read(sc, DP83840_BMCR);
-		if (result == TCVR_FAILURE)
-			return -1;
-		if (!(result & BMCR_ISOLATE))
-			break;
-		DELAY(20);
-	}
-	if (!tries) {
-		printf("%s: bmcr unisolate failed\n", sc->sc_dev.dv_xname);
-		return -1;
-	}
-
-	result = hme_tcvr_read(sc, DP83840_PCR);
-	hme_tcvr_write(sc, DP83840_PCR, (result | PCR_CIM_DIS));
-	return 0;
-}
-
-
-/*
- * We need to know whether we are using an internal or external transceiver.
- */
-static void
-hme_tcvr_check(sc)
-	struct hme_softc *sc;
-{
-	struct hme_tcvr *tcvr = sc->sc_tcvr;
-	u_int32_t cfg = tcvr->cfg;
-
-	/* polling? */
-	if (sc->sc_flags & HME_FLAG_POLL) {
-		if (sc->sc_tcvr_type == HME_TCVR_INTERNAL) {
-			hme_poll_stop(sc);
-			sc->sc_phyaddr = TCVR_PHYADDR_ETX;
-			sc->sc_tcvr_type = HME_TCVR_EXTERNAL;
-			cfg &= ~(TCVR_CFG_PENABLE);
-			cfg |= TCVR_CFG_PSELECT;
-			tcvr->cfg = cfg;
-		}
-		else {
-			if (!(tcvr->status >> 16)) {
-				hme_poll_stop(sc);
-				sc->sc_phyaddr = TCVR_PHYADDR_ITX;
-				sc->sc_tcvr_type = HME_TCVR_INTERNAL;
-				cfg &= ~(TCVR_CFG_PSELECT);
-				tcvr->cfg = cfg;
-			}
-		}
-	}
-	else {
-		u_int32_t cfg2 = tcvr->cfg;
-
-		if (cfg2 & TCVR_CFG_MDIO1) {
-			tcvr->cfg = cfg | TCVR_CFG_PSELECT;
-			sc->sc_phyaddr = TCVR_PHYADDR_ETX;
-			sc->sc_tcvr_type = HME_TCVR_EXTERNAL;
-		}
-		else {
-			if (cfg2 & TCVR_CFG_MDIO0) {
-				tcvr->cfg = cfg & ~(TCVR_CFG_PSELECT);
-				sc->sc_phyaddr = TCVR_PHYADDR_ITX;
-				sc->sc_tcvr_type = HME_TCVR_INTERNAL;
-			}
-			else {
-				sc->sc_tcvr_type = HME_TCVR_NONE;
-			}
-		}
-	}
+	mii_mediachg(&sc->sc_mii);
 }
 
 static void
@@ -841,69 +606,7 @@ hme_poll_stop(sc)
 	tcvr->int_mask = 0xffff;
         tcvr->cfg &= ~(TCVR_CFG_PENABLE);
 	sc->sc_flags &= ~(HME_FLAG_POLL);
-	DELAY(20);
-}
-
-#define XCVR_WRITE_TRIES	16
-
-static void
-hme_tcvr_write(sc, reg, val)
-	struct hme_softc *sc;
-	int reg;
-	u_short val;
-{
-	struct hme_tcvr *tcvr = sc->sc_tcvr;
-	int tries = XCVR_WRITE_TRIES;
-
-	/* Use the bitbang? */
-	if (! (sc->sc_flags & HME_FLAG_FENABLE))
-		return hme_tcvr_bb_write(sc, reg, val);
-
-	/* No, good... we just write to the tcvr frame */
-	tcvr->frame = (FRAME_WRITE | sc->sc_phyaddr << 23) |
-		      ((reg & 0xff) << 18) |
-		      (val & 0xffff);
-	while (!(tcvr->frame & 0x10000) && (tries != 0)) {
-		tries--;
-		DELAY(20);
-	}
-
-	if (!tries)
-		printf("%s: tcvr_write failed\n", sc->sc_dev.dv_xname);
-}
-
-#define XCVR_READ_TRIES	16
-
-static int
-hme_tcvr_read(sc, reg)
-	struct hme_softc *sc;
-	int reg;
-{
-	struct hme_tcvr *tcvr = sc->sc_tcvr;
-	int tries = XCVR_READ_TRIES;
-
-	if (sc->sc_tcvr_type == HME_TCVR_NONE) {
-		printf("%s: no transceiver type\n", sc->sc_dev.dv_xname);
-		return TCVR_FAILURE;
-	}
-
-	/* Use the bitbang? */
-	if (! (sc->sc_flags & HME_FLAG_FENABLE))
-		return hme_tcvr_bb_read(sc, reg);
-
-	/* No, good... we just write/read to the tcvr frame */
-	tcvr->frame = (FRAME_READ | sc->sc_phyaddr << 23) |
-		      ((reg & 0xff) << 18);
-	while (!(tcvr->frame & 0x10000) && (tries != 0)) {
-		tries--;
-		DELAY(20);
-	}
-
-	if (!tries) {
-		printf("%s: tcvr_write failed\n", sc->sc_dev.dv_xname);
-		return TCVR_FAILURE;
-	}
-	return (tcvr->frame & 0xffff);
+	DELAY(200);
 }
 
 /*
@@ -921,200 +624,22 @@ hme_tcvr_bb_writeb(sc, b)
 }
 
 static int
-hme_tcvr_bb_readb(sc)
+hme_tcvr_bb_readb(sc, phy)
 	struct hme_softc *sc;
+	int phy;
 {
 	int ret;
 
 	sc->sc_tcvr->bb_clock = 0;
 	DELAY(10);
-	if (sc->sc_tcvr_type == HME_TCVR_INTERNAL)
+	if (phy == TCVR_PHYADDR_ITX)
 		ret = sc->sc_tcvr->cfg & TCVR_CFG_MDIO0;
-	else
+	if (phy == TCVR_PHYADDR_ETX)
 		ret = sc->sc_tcvr->cfg & TCVR_CFG_MDIO1;
 	sc->sc_tcvr->bb_clock = 1;
 	return ((ret) ? 1 : 0);
 }
 
-static void
-hme_tcvr_bb_write(sc, reg, val)
-	struct hme_softc *sc;
-	int reg;
-	u_short val;
-{
-	struct hme_tcvr *tcvr = sc->sc_tcvr;
-	int i;
-
-	tcvr->bb_oenab = 1;	                /* turn on bitbang intrs */
-
-	for (i = 0; i < 32; i++)		/* make bitbang idle */
-		hme_tcvr_bb_writeb(sc, 1);
-
-	hme_tcvr_bb_writeb(sc, 0);		/* 0101 signals a write */
-	hme_tcvr_bb_writeb(sc, 1);
-	hme_tcvr_bb_writeb(sc, 0);
-	hme_tcvr_bb_writeb(sc, 1);
-
-	for (i = 4; i >= 0; i--)		/* send PHY addr */
-		hme_tcvr_bb_writeb(sc, ((sc->sc_phyaddr & 0xff) >> i) & 0x1);
-
-	for (i = 4; i >= 0; i--)		/* send register num */
-		hme_tcvr_bb_writeb(sc, ((reg & 0xff) >> i) & 0x1);
-
-	hme_tcvr_bb_writeb(sc, 1);		/* get ready for data */
-	hme_tcvr_bb_writeb(sc, 0);
-
-	for (i = 15; i >= 0; i--)		/* send new value */
-		hme_tcvr_bb_writeb(sc, (val >> i) & 0x1);
-
-	tcvr->bb_oenab = 0;	                /* turn off bitbang intrs */
-}
-
-static int
-hme_tcvr_bb_read(sc, reg)
-	struct hme_softc *sc;
-	int reg;
-{
-	struct hme_tcvr *tcvr = sc->sc_tcvr;
-	int ret = 0, i;
-
-	tcvr->bb_oenab = 1;                	/* turn on bitbang intrs */
-
-	for (i = 0; i < 32; i++)		/* make bitbang idle */
-		hme_tcvr_bb_writeb(sc, 1);
-
-	hme_tcvr_bb_writeb(sc, 0);		/* 0110 signals a read */
-	hme_tcvr_bb_writeb(sc, 1);
-	hme_tcvr_bb_writeb(sc, 1);
-	hme_tcvr_bb_writeb(sc, 0);
-
-	for (i = 4; i >= 0; i--)		/* send PHY addr */
-		hme_tcvr_bb_writeb(sc, ((sc->sc_phyaddr & 0xff) >> i) & 0x1);
-
-	for (i = 4; i >= 0; i--)		/* send register num */
-		hme_tcvr_bb_writeb(sc, ((reg & 0xff) >> i) & 0x1);
-
-	tcvr->bb_oenab = 0;	                /* turn off bitbang intrs */
-
-	hme_tcvr_bb_readb(sc);			/* ignore... */
-
-	for (i = 15; i >= 15; i--)		/* read value */
-		ret |= hme_tcvr_bb_readb(sc) << i;
-
-	hme_tcvr_bb_readb(sc);			/* ignore... */
-	hme_tcvr_bb_readb(sc);			/* ignore... */
-	hme_tcvr_bb_readb(sc);			/* ignore... */
-
-	return ret;
-}
-
-static void
-hme_auto_negotiate(sc)
-	struct hme_softc *sc;
-{
-	int tries;
-
-	/* grab all of the registers */
-	sc->sc_sw.bmsr =	hme_tcvr_read(sc, DP83840_BMSR);
-	sc->sc_sw.bmcr =	hme_tcvr_read(sc, DP83840_BMCR);
-	sc->sc_sw.phyidr1 =	hme_tcvr_read(sc, DP83840_PHYIDR1);
-	sc->sc_sw.phyidr2 =	hme_tcvr_read(sc, DP83840_PHYIDR2);
-	sc->sc_sw.anar =	hme_tcvr_read(sc, DP83840_ANAR);
-
-	/* can this board autonegotiate? No, die. */
-	if (! (sc->sc_sw.bmsr & BMSR_ANC))
-		return;
-
-	/* Start autonegoiation */
-	sc->sc_sw.bmcr |= BMCR_ANE;	/* enable auto-neg */
-	hme_tcvr_write(sc, DP83840_BMCR, sc->sc_sw.bmcr);
-	sc->sc_sw.bmcr |= BMCR_RAN;	/* force a restart */
-	hme_tcvr_write(sc, DP83840_BMCR, sc->sc_sw.bmcr);
-
-	/* BMCR_RAN clears itself when it has started negotiation... */
-	tries = 64;
-	while (--tries) {
-		int r = hme_tcvr_read(sc, DP83840_BMCR);
-		if (r == TCVR_FAILURE)
-			return;
-		sc->sc_sw.bmcr = r;
-		if (! (sc->sc_sw.bmcr & BMCR_RAN))
-			break;
-		DELAY(100);
-	}
-	if (!tries) {
-		printf("%s: failed to start auto-negotiation\n",
-			sc->sc_dev.dv_xname);
-		return;
-	}
-	sc->sc_an_state = HME_TIMER_AUTONEG;
-	sc->sc_an_ticks = 0;
-	timeout(hme_negotiate_watchdog, sc, (12 * hz)/10);
-}
-
-/*
- * If auto-negotiating, check to see if it has completed successfully.  If so,
- * wait for a link up.  If it completed unsucessfully, try the manual process.
- */
-static void
-hme_negotiate_watchdog(arg)
-	void *arg;
-{
-	struct hme_softc *sc = (struct hme_softc *)arg;
-	struct ifnet *ifp = &sc->sc_arpcom.ac_if;
-
-	sc->sc_an_ticks++;
-	switch (sc->sc_an_state) {
-	    case HME_TIMER_DONE:
-		return;
-	    case HME_TIMER_AUTONEG:
-		sc->sc_sw.bmsr = hme_tcvr_read(sc, DP83840_BMSR);
-		if (sc->sc_sw.bmsr & BMSR_ANCOMPLETE) {
-			sc->sc_an_state = HME_TIMER_LINKUP;
-			sc->sc_an_ticks = 0;
-			timeout(hme_negotiate_watchdog, sc, (12 * hz)/10);
-			return;
-		}
-		if (sc->sc_an_ticks > 10) {
-			printf("%s: auto-negotiation failed.\n",
-				sc->sc_dev.dv_xname);
-			hme_auto_negotiate(sc);
-			return;
-		}
-		timeout(hme_negotiate_watchdog, sc, (12 * hz)/10);
-		break;
-	    case HME_TIMER_LINKUP:
-		ifp->if_flags |= IFF_RUNNING;
-		ifp->if_flags &= ~IFF_OACTIVE;
-		ifp->if_timer = 0;
-		hmestart(ifp);
-		sc->sc_sw.bmsr = hme_tcvr_read(sc, DP83840_BMSR);
-		if (sc->sc_sw.bmsr & BMSR_LINKSTATUS) {
-			sc->sc_an_state = HME_TIMER_DONE;
-			sc->sc_an_ticks = 0;
-			hme_print_link_mode(sc);
-			return;
-		}
-		if ((sc->sc_an_ticks % 10) == 0) {
-			printf("%s: link down...\n", sc->sc_dev.dv_xname);
-			timeout(hme_negotiate_watchdog, sc, (12 * hz)/10);
-			return;
-		}
-	}
-}
-
-static void 
-hme_print_link_mode(sc)
-	struct hme_softc *sc;
-{
-	sc->sc_sw.bmcr = hme_tcvr_read(sc, DP83840_BMCR);
-	printf("%s: %s transceiver up %dMb/s %s duplex\n",
-	    sc->sc_dev.dv_xname,
-	    (sc->sc_tcvr_type == HME_TCVR_EXTERNAL) ? "external" : "internal",
-	    (sc->sc_sw.bmcr & BMCR_SPEED) ? 100 : 10,
-	    (sc->sc_sw.bmcr & BMCR_DUPLEX) ? "full" : "half");
-}
-
 #define RESET_TRIES	32
 
 static void
@@ -1155,19 +680,7 @@ hme_mint(sc, why)
 	struct hme_softc *sc;
 	u_int32_t why;
 {
-	sc->sc_sw.bmcr = hme_tcvr_read(sc, DP83840_BMCR);
-	sc->sc_sw.anlpar = hme_tcvr_read(sc, DP83840_ANLPAR);
-
 	printf("%s: link status changed\n", sc->sc_dev.dv_xname);
-	if (sc->sc_sw.anlpar & ANLPAR_TX_FD) {
-		sc->sc_sw.bmcr |= (BMCR_SPEED | BMCR_DUPLEX);
-	} else if (sc->sc_sw.anlpar & ANLPAR_TX) {
-		sc->sc_sw.bmcr |= BMCR_SPEED;
-	} else if (sc->sc_sw.anlpar & ANLPAR_10_FD) {
-		sc->sc_sw.bmcr |= BMCR_DUPLEX;
-	} /* else 10Mb half duplex... */
-	hme_tcvr_write(sc, DP83840_BMCR, sc->sc_sw.bmcr);
-	hme_print_link_mode(sc);
 	hme_poll_stop(sc);
 	return 1;
 }
@@ -1532,104 +1045,136 @@ hme_mcreset(sc)
 	}
 }
 
-/*
- * Get current media settings.
- */
 static void
-hme_ifmedia_sts(ifp, ifmr)
-	struct ifnet *ifp;
-	struct ifmediareq *ifmr;
+hme_mii_write(self, phy, reg, val)
+	struct device *self;
+	int phy, reg, val;
 {
-	struct hme_softc *sc = ifp->if_softc;
+	struct hme_softc *sc = (struct hme_softc *)self;
+	struct hme_tcvr *tcvr = sc->sc_tcvr;
+	int tries = 16, i;
+
+	if (sc->sc_flags & HME_FLAG_FENABLE) {
+		tcvr->frame = (FRAME_WRITE | phy << 23) |
+			      ((reg & 0xff) << 18) |
+			      (val & 0xffff);
+		while (!(tcvr->frame & 0x10000) && (tries != 0)) {
+			tries--;
+			DELAY(200);
+		}
+		if (!tries)
+			printf("%s: mii_read failed\n", sc->sc_dev.dv_xname);
+		return;
+	}
 
-	sc->sc_sw.bmcr = hme_tcvr_read(sc, DP83840_BMCR);
-	sc->sc_sw.bmsr = hme_tcvr_read(sc, DP83840_BMSR);
+	tcvr->bb_oenab = 1;
 
-	switch (sc->sc_sw.bmcr & (BMCR_SPEED | BMCR_DUPLEX)) {
-	case (BMCR_SPEED | BMCR_DUPLEX):
-		ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
-		break;
-	case BMCR_SPEED:
-		ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
-		break;
-	case BMCR_DUPLEX:
-		ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
-		break;
-	case 0:
-		ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
-		break;
-	}
+	for (i = 0; i < 32; i++)
+		hme_tcvr_bb_writeb(sc, 1);
 
-	if (sc->sc_sw.bmsr & BMSR_LINKSTATUS)
-		ifmr->ifm_status |= IFM_AVALID | IFM_ACTIVE;
-	else {
-		ifmr->ifm_status |= IFM_AVALID;
-		ifmr->ifm_status &= ~IFM_ACTIVE;
-	}
+	hme_tcvr_bb_writeb(sc, (MII_COMMAND_START >> 1) & 1);
+	hme_tcvr_bb_writeb(sc, MII_COMMAND_START & 1);
+	hme_tcvr_bb_writeb(sc, (MII_COMMAND_WRITE >> 1) & 1);
+	hme_tcvr_bb_writeb(sc, MII_COMMAND_WRITE & 1);
+
+	for (i = 4; i >= 0; i--)
+		hme_tcvr_bb_writeb(sc, (phy >> i) & 1);
+
+	for (i = 4; i >= 0; i--)
+		hme_tcvr_bb_writeb(sc, (reg >> i) & 1);
+
+	for (i = 15; i >= 0; i--)
+		hme_tcvr_bb_writeb(sc, (reg >> i) & 1);
+
+	tcvr->bb_oenab = 0;
 }
 
 static int
-hme_ifmedia_upd(ifp)
-	struct ifnet *ifp;
+hme_mii_read(self, phy, reg)
+	struct device *self;
+	int phy, reg;
 {
-	struct hme_softc *sc = ifp->if_softc;
-	struct ifmedia *ifm = &sc->sc_ifmedia;
+	struct hme_softc *sc = (struct hme_softc *)self;
+	struct hme_tcvr *tcvr = sc->sc_tcvr;
+	int tries = 16, i, ret;
+
+	/* Use the frame if possible */
+	if (sc->sc_flags & HME_FLAG_FENABLE) {
+		tcvr->frame = (FRAME_READ | phy << 23) |
+			      ((reg & 0xff) << 18);
+		while (!(tcvr->frame & 0x10000) && (tries != 0)) {
+			tries--;
+			DELAY(20);
+		}
+		if (!tries) {
+			printf("%s: mii_read failed\n", sc->sc_dev.dv_xname);
+			return 0;
+		}
+		return (tcvr->frame & 0xffff);
+	}
 
-	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
-		return (EINVAL);
+	tcvr->bb_oenab = 1;
 
-	sc->sc_sw.bmsr = hme_tcvr_read(sc, DP83840_BMSR);
+	for (i = 0; i < 32; i++)		/* make bitbang idle */
+		hme_tcvr_bb_writeb(sc, 1);
 
-	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO &&
-	    sc->sc_sw.bmsr & BMSR_ANC) {
-		
-		/* advertise -everything- supported */
-		if (sc->sc_sw.bmsr & BMSR_10BASET_HALF)
-			sc->sc_sw.anar |= ANAR_10;
-		else
-			sc->sc_sw.anar &= ~(ANAR_10);
+	hme_tcvr_bb_writeb(sc, (MII_COMMAND_START >> 1) & 1);
+	hme_tcvr_bb_writeb(sc, MII_COMMAND_START & 1);
+	hme_tcvr_bb_writeb(sc, (MII_COMMAND_READ >> 1) & 1);
+	hme_tcvr_bb_writeb(sc, MII_COMMAND_READ & 1);
 
-		if (sc->sc_sw.bmsr & BMSR_10BASET_FULL)
-			sc->sc_sw.anar |= ANAR_10_FD;
-		else
-			sc->sc_sw.anar &= ~(ANAR_10_FD);
+	for (i = 4; i >= 0; i--)
+		hme_tcvr_bb_writeb(sc, (phy >> i) & 1);
 
-		if (sc->sc_sw.bmsr & BMSR_100BASETX_HALF)
-			sc->sc_sw.anar |= ANAR_TX;
-		else
-			sc->sc_sw.anar &= ~(ANAR_TX);
+	for (i = 4; i >= 0; i--)
+		hme_tcvr_bb_writeb(sc, (reg >> i) & 1);
 
-		if (sc->sc_sw.bmsr & BMSR_100BASETX_FULL)
-			sc->sc_sw.anar |= ANAR_TX_FD;
-		else
-			sc->sc_sw.anar &= ~(ANAR_TX_FD);
+	tcvr->bb_oenab = 0;	                /* turn off bitbang intrs */
 
-		hme_tcvr_write(sc, DP83840_ANAR, sc->sc_sw.anar);
-		hme_auto_negotiate(sc);
-		return (0);
-	}
-	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
-		return (EINVAL);
+	hme_tcvr_bb_readb(sc, phy);		/* ignore... */
 
-	sc->sc_sw.anar = hme_tcvr_read(sc, DP83840_ANAR);
-	sc->sc_sw.anar &= ~(ANAR_T4 | ANAR_TX_FD | ANAR_TX
-	    | ANAR_10_FD | ANAR_10);
+	for (i = 15; i >= 15; i--)		/* read value */
+		ret |= hme_tcvr_bb_readb(sc, phy) << i;
 
-	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
-		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
-			sc->sc_sw.anar |= ANAR_TX_FD;
-		else
-			sc->sc_sw.anar |= ANAR_TX;
-	}
+	hme_tcvr_bb_readb(sc, phy);			/* ignore... */
+	hme_tcvr_bb_readb(sc, phy);			/* ignore... */
+	hme_tcvr_bb_readb(sc, phy);			/* ignore... */
 
-	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) {
-		if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
-			sc->sc_sw.anar |= ANAR_10_FD;
-		else
-			sc->sc_sw.anar |= ANAR_10;
-	}
+	return ret;
+}
 
-	hme_tcvr_write(sc, DP83840_ANAR, sc->sc_sw.anar);
-	hme_auto_negotiate(sc);
+static int
+hme_mediachange(ifp)
+	struct ifnet *ifp;
+{
+	if (ifp->if_flags & IFF_UP)
+		hmeinit(ifp->if_softc);
 	return (0);
 }
+
+static void
+hme_mediastatus(ifp, ifmr)
+	struct ifnet *ifp;
+	struct ifmediareq *ifmr;
+{
+	struct hme_softc *sc = (struct hme_softc *)ifp->if_softc;
+
+	mii_pollstat(&sc->sc_mii);
+	ifmr->ifm_active = sc->sc_mii.mii_media_active;
+	ifmr->ifm_status = sc->sc_mii.mii_media_status;
+}
+
+static void
+hme_mii_statchg(self)
+	struct device *self;
+{
+	struct hme_softc *sc = (struct hme_softc *)sc;
+	struct hme_cr *cr = sc->sc_cr;
+
+	if (sc->sc_mii.mii_media_active & IFM_FDX)
+		cr->tx_cfg |= CR_TXCFG_FULLDPLX;
+	else
+		cr->tx_cfg &= ~CR_TXCFG_FULLDPLX;
+
+	/* XXX Update ifp->if_baudrate */
+}
diff --git a/sys/arch/sparc/dev/hmereg.h b/sys/arch/sparc/dev/hmereg.h
index b54a903e407..c8c79a5d9f5 100644
--- a/sys/arch/sparc/dev/hmereg.h
+++ b/sys/arch/sparc/dev/hmereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: hmereg.h,v 1.5 1998/09/01 17:36:59 jason Exp $	*/
+/*	$OpenBSD: hmereg.h,v 1.6 1998/09/10 17:34:32 jason Exp $	*/
 
 /*
  * Copyright (c) 1998 Jason L. Wright (jason@thought.net)
@@ -398,188 +398,3 @@ struct hme_bufs {
 	char rx_buf[HME_RX_RING_SIZE][HME_RX_PKT_BUF_SZ];
 	char tx_buf[HME_TX_RING_SIZE][HME_TX_PKT_BUF_SZ];
 };
-
-/*
- * National Semiconductor DP83840A chip definitions
- * Documentation available from National at:
- *	http://www.national.com/pf/DP/DP83840A.html
- */
-
-/*
- * Register offsets
- */
-#define DP83840_BMCR	0x00	/* Basic Mode Control Register		*/
-#define DP83840_BMSR	0x01	/* Basic Mode Status Register		*/
-#define DP83840_PHYIDR1	0x02	/* PHY Identifier Register #1		*/
-#define DP83840_PHYIDR2	0x03	/* PHY Identifier Register #2		*/
-#define DP83840_ANAR	0x04	/* Auto-Negotiation Advertisement Reg	*/
-#define DP83840_ANLPAR	0x05	/* Auto-Negotiation Partner Ability Reg */
-#define DP83840_ANER	0x06	/* Auto-Negotiation Expansion Register	*/
-	/* 0x07 - 0x11 Reserved */
-#define DP83840_DCR	0x12	/* Disconnect Counter Register		*/
-#define DP83840_FCSCR	0x13	/* False Carrier Sense Counter Register	*/
-	/* 0x14 Reserved */
-#define DP83840_RECR	0x15	/* Receive Error Counter Register	*/
-#define DP83840_SRR	0x16	/* Silicon Revision Register		*/
-#define DP83840_PCR	0x17	/* PCS Sub-Layer Configuration Register	*/
-#define DP83840_LBREMR	0x18	/* Loopback,Bypass,& Receiver Error Reg	*/
-#define DP83840_PAR	0x19	/* PHY Address Register			*/
-	/* 0x1a Reserved */
-#define DP83840_10BTSR	0x1b	/* 10BaseT Status Register		*/
-#define DP83840_10BTCR	0x1c	/* 10BaseT Configuration Register	*/
-	/* 0x1d - 0x1f Reserved */
-
-/*
- * Basic Mode Control Register (BMCR)
- */
-#define BMCR_RESET		0x8000	/* Software reset		*/
-#define BMCR_LOOPBACK		0x4000	/* Lookback enable		*/
-#define BMCR_SPEED		0x2000	/* 1=100Mb, 0=10Mb		*/
-#define BMCR_ANE		0x1000	/* Auto-Negiation enable	*/
-#define BMCR_PDOWN		0x0800	/* power down the chip		*/
-#define BMCR_ISOLATE		0x0400	/* Isolate the chip		*/
-#define BMCR_RAN		0x0200	/* Restart autonegotiation	*/
-#define BMCR_DUPLEX		0x0100	/* 1=full, 0=half		*/
-#define BMCR_COLLISONTEST	0x0080	/* Create collisions on TX	*/
-
-/*
- * Basic Mode Status Register (BMSR)
- */
-#define BMSR_100BASET4		0x8000	/* 100BaseT4 capable?		*/
-#define BMSR_100BASETX_FULL	0x4000	/* 100BaseTX full duplex?	*/
-#define BMSR_100BASETX_HALF	0x2000	/* 100BaseTX half duplex?	*/
-#define BMSR_10BASET_FULL	0x1000	/* 10BaseT full duplex?		*/
-#define BMSR_10BASET_HALF	0x0800	/* 10BaseT half duplex?		*/
-#define BMSR_ANCOMPLETE		0x0020	/* auto-negotiation complete?	*/
-#define BMSR_REMOTEFAULT	0x0010	/* Fault condition seen?	*/
-#define BMSR_ANC		0x0008	/* Can auto-negotiate?		*/
-#define BMSR_LINKSTATUS		0x0004	/* Link established?		*/
-#define BMSR_JABBER		0x0002	/* Jabber detected?		*/
-#define BMSR_EXTENDED		0x0001	/* Extended registers?		*/
-
-/*
- * Auto-Negotiation Advertisement Register (ANAR)
- */
-#define ANAR_NP			0x8000	/* Next page indicator		*/
-#define ANAR_ACK		0x4000	/* Acknowledge			*/
-#define ANAR_RF			0x2000	/* Remote Fault			*/
-#define ANAR_RSRV12		0x1000	/* reserved			*/
-#define ANAR_RSRV11		0x0800	/* reserved			*/
-#define ANAR_RSRV10		0x0400	/* reserved			*/
-#define ANAR_T4			0x0200	/* 100BaseT4 support?		*/
-#define ANAR_TX_FD		0x0100	/* 100BaseTX full duplex?	*/
-#define ANAR_TX			0x0080	/* 100BaseTX half duplex?	*/
-#define ANAR_10_FD		0x0040	/* 10BaseT full duplex?		*/
-#define ANAR_10			0x0020	/* 10BaseT full duplex?		*/
-#define ANAR_SELECTOR		0x001f	/* protocol selector		*/
-
-/*
- * Auto-Negotiation Link Partner Ability Register (ANLPAR)
- */
-#define ANLPAR_NP		0x8000	/* Next page indictaion		*/
-#define ANLPAR_ACK		0x4000	/* Acknowledge			*/
-#define ANLPAR_RF		0x2000	/* Remote Fault			*/
-#define ANLPAR_RSRV12		0x1000	/* reserved			*/
-#define ANLPAR_RSRV11		0x0800	/* reserved			*/
-#define ANLPAR_RSRV10		0x0400	/* reserved			*/
-#define ANLPAR_T4		0x0200	/* 100BaseT4 support?		*/
-#define ANLPAR_TX_FD		0x0100	/* 100BaseTX full duplex?	*/
-#define ANLPAR_TX		0x0080	/* 100BaseTX half duplex?	*/
-#define ANLPAR_10_FD		0x0040	/* 10BaseT full duplex?		*/
-#define ANLPAR_10		0x0020	/* 10BaseT full duplex?		*/
-#define ANLPAR_SELECTOR		0x001f	/* protocol selector		*/
-
-/*
- * Auto-Negotiation Expansion Register (ANER)
- */
-#define ANER_RSRV15		0x8000	/* reserved			*/
-#define ANER_RSRV14		0x4000	/* reserved			*/
-#define ANER_RSRV13		0x2000	/* reserved			*/
-#define ANER_RSRV12		0x1000	/* reserved			*/
-#define ANER_RSRV11		0x0800	/* reserved			*/
-#define ANER_RSRV10		0x0400	/* reserved			*/
-#define ANER_RSRV09		0x0200	/* reserved			*/
-#define ANER_RSRV08		0x0100	/* reserved			*/
-#define ANER_RSRV07		0x0080	/* reserved			*/
-#define ANER_RSRV06		0x0040	/* reserved			*/
-#define ANER_RSRV05		0x0020	/* reserved			*/
-#define ANER_MLF		0x0010	/* Multiple link fault		*/
-#define ANER_LP_NP_ABLE		0x0008	/* Link partner next page-able	*/
-#define ANER_NP_ABLE		0x0004	/* Next page-able		*/
-#define ANER_PAGE_RX		0x0002	/* Link Code Word Page Received	*/
-#define ANER_LP_AN_ABLE		0x0001	/* Link partner auto-neg-able	*/
-
-/*
- * PCS Configuration Register (PCR)
- */
-#define PCR_NRZI_EN		0x8000	/* NRZI coding enable		*/
-#define PCR_DESCR_TO_SEL	0x4000	/* Descrambler timeout select	*/
-#define PCR_DESCR_TO_DIS	0x2000	/* Descrambler timeout disable	*/
-#define PCR_REPEATER		0x1000	/* Repeater/Node Mode		*/
-#define PCR_ENCSEL		0x0800	/* Encoder Mode select		*/
-#define PCR_RSRV10		0x0400	/* reserved			*/
-#define PCR_RSRV09		0x0200	/* reserved			*/
-#define PCR_RSRV08		0x0100	/* reserved			*/
-#define PCR_CLK25MDIS		0x0080	/* CLK25M disbable		*/
-#define PCR_F_LINK_100		0x0040	/* Force good link in 100Mb/s	*/
-#define PCR_CIM_DIS		0x0020	/* Carrier integ. mon. disable	*/
-#define PCR_TX_OFF		0x0010	/* Force transmit off		*/
-#define PCR_RSRV03		0x0008	/* reserved			*/
-#define PCR_LED1_MODE		0x0004	/* Led1 mode select		*/
-#define PCR_LED4_MODE		0x0002	/* Led4 mode select		*/
-#define PCR_RSRV00		0x0001	/* reserved			*/
-
-/*
- * Loopback, bypass, and receiver error mask register (LBREMR)
- */
-#define LBREMR_BAD_SSD_EN	0x8000	/* BAD SSD enable		*/
-#define LBREMR_BP_4B5B		0x4000	/* Bypass 4B5B and 5B4B enc/dec	*/
-#define LBREMR_BP_SCR		0x2000	/* Bypass scramble/descramble	*/
-#define LBREMR_BP_ALIGN		0x1000	/* Bypass symbol alignment func	*/
-#define LBREMR_10BT_LPBK	0x0800	/* 10BaseT enc/dec loopback	*/
-#define LBREMR_RSRV10		0x0400	/* reserved			*/
-#define LBREMR_LB1		0x0200	/* Loopback control bit #2	*/
-#define LBREMR_LB0		0x0100	/* Loopback control bit #1	*/
-#define LBREMR_RSRV07		0x0080	/* reserved			*/
-#define LBREMR_ALT_CRS		0x0040	/* Alternate CRS operation	*/
-#define LBREMR_LBK_XMT_DIS	0x0020	/* 100Mb/s tx disable in loop	*/
-#define LBREMR_CODE_ERR		0x0010	/* Code errors			*/
-#define LBREMR_PE_ERR		0x0008	/* Premature end errors		*/
-#define LBREMR_LINK_ERR		0x0004	/* Link errors			*/
-#define LBREMR_PKT_ERR		0x0002	/* Packet errors		*/
-#define LBREMR_RSRV00		0x0001	/* reserved			*/
-
-/*
- * PHY Address Register (PAR)
- */
-#define PAR_RSRV15		0x8000	/* reserved			*/
-#define PAR_RSRV14		0x4000	/* reserved			*/
-#define PAR_RSRV13		0x2000	/* reserved			*/
-#define PAR_RSRV12		0x1000	/* reserved			*/
-#define	PAR_DIS_CRS_JAB		0x0800	/* Disable CS during jabber	*/
-#define PAR_AN_EN_STAT		0x0400	/* Auto-Neg. mode status	*/
-#define PAR_RSRV09		0x0200	/* reserved			*/
-#define PAR_FEFI_EN		0x0100	/* Far end fault status enable	*/
-#define PAR_DUPLEX_STAT		0x0080	/* 1=full duplex, 0=half duplex	*/
-#define PAR_SPEED_10		0x0040	/* 1=10Mb/s, 0=100Mb/s		*/
-#define PAR_CIM_STATUS		0x0020	/* Carrier integrity mon. stat	*/
-#define PAR_PHYADDR4		0x0010	/* physical address bit 4	*/
-#define PAR_PHYADDR3		0x0008	/* physical address bit 3	*/
-#define PAR_PHYADDR2		0x0004	/* physical address bit 2	*/
-#define PAR_PHYADDR1		0x0002	/* physical address bit 1	*/
-#define PAR_PHYADDR0		0x0001	/* physical address bit 0	*/
-
-/*
- * 10BaseT status register (TENBTSR)
- */
-#define TENBTSR10BT_SER		0x0200	/* 10BaseT Serial mode?		*/
-
-/*
- * 10BaseT configuration register (TENBTCR)
- */
-#define TENBTCR_LP_EN		0x0020	/* Link pulse enable		*/
-#define	TENBTCR_HBE		0x0010	/* Heartbeat enable		*/
-#define TENBTCR_UTP_STP		0x0008	/* 1=UTP, 0=STP			*/
-#define TENBTCR_LSS		0x0004	/* Low squelch select		*/
-#define TENBTCR_RSRV01		0x0002	/* reserved			*/
-#define TENBTCR_JABEN		0x0001	/* Jabber enable		*/
diff --git a/sys/arch/sparc/dev/hmevar.h b/sys/arch/sparc/dev/hmevar.h
index ac434468678..a0ea534bff5 100644
--- a/sys/arch/sparc/dev/hmevar.h
+++ b/sys/arch/sparc/dev/hmevar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: hmevar.h,v 1.4 1998/09/08 04:48:38 jason Exp $	*/
+/*	$OpenBSD: hmevar.h,v 1.5 1998/09/10 17:34:32 jason Exp $	*/
 
 /*
  * Copyright (c) 1998 Jason L. Wright (jason@thought.net)
@@ -36,7 +36,9 @@ struct hme_softc {
 	struct	sbusdev sc_sd;		/* sbus device */
 	struct	intrhand sc_ih;		/* interrupt vectoring */
 	int	sc_node;		/* which sbus node */
-	struct	ifmedia sc_ifmedia;	/* interface media */
+
+	mii_data_t	sc_mii;		/* mii bus */
+
 	struct	arpcom sc_arpcom;	/* ethernet common */
 
 	/*
@@ -54,10 +56,6 @@ struct hme_softc {
 
 	u_int32_t	sc_flags;	/* status flags	*/
 	u_int32_t	sc_promisc;	/* are we promiscuous? */
-	u_int32_t	sc_phyaddr;	/* PHY addr */
-	int		sc_an_state;	/* state of negotiation */
-	int		sc_an_ticks;	/* how long has passed? */
-	int		sc_tcvr_type;	/* transceiver type */
 
 	/*
 	 * RX/TX ring buffers, descriptors, and counters