move master definition for the interrupt register to vaddrs.h with all

of the other special virtual addresses and also provide visibility
needed for bsd_fd.s to reference it...

2 files changed, 8 insertions, 3 deletions

diff --git a/sys/arch/sparc/sparc/locore.s b/sys/arch/sparc/sparc/locore.s
index 6453df5d0fa..e97b49ba460 100644
--- a/sys/arch/sparc/sparc/locore.s
+++ b/sys/arch/sparc/sparc/locore.s
@@ -276,10 +276,11 @@ _msgbuf = KERNBASE
  * for this, wasting a page of physical memory.
  *
  * This doesn't work for the Sun4M, which can have 5 or more pages of
- * registers. Thus we use a reserved piece of the virtual address space, set
- * up in bootstrap().
+ * registers, a system register and one for each processor.  Thus we use
+ * a reserved piece of the virtual address space, set up in bootstrap().
  */
-IE_reg_addr = KERNBASE + 8192		! this page not used; points to IEreg
+
+IE_reg_addr = INTRREG_VA	! KERNBASE + 8192 - points to IEreg
 
 /*
  * Each trap has room for four instructions, of which one perforce must
diff --git a/sys/arch/sparc/sparc/vaddrs.h b/sys/arch/sparc/sparc/vaddrs.h
index 48cad5f52e8..0beedac2545 100644
--- a/sys/arch/sparc/sparc/vaddrs.h
+++ b/sys/arch/sparc/sparc/vaddrs.h
@@ -68,12 +68,16 @@
  * use one of the two `wasted' pages at KERNBASE+_MAXNBPG (see locore.s).
  */
 
+
 #ifndef IODEV_0
 #define	IODEV_0	0xfe000000	/* must match VM_MAX_KERNEL_ADDRESS */
 
 #define _MAXNBPG	8192	/* fixed VAs, independent of actual NBPG */
 #define _MAXNCPU	4	/* fixed VA allocation allows 4 CPUs */
 
+/* [4c:] interrupt register as described above */
+#define	INTRREG_VA	(    KERNBASE + _MAXNBPG)		/* [4c] */
+
 /* [4m:] interrupt and counter registers take (1 + NCPU) pages. */
 
 #define	TIMERREG_VA	(IODEV_0)