diff options
| author | Jasper Lievisse Adriaanse <jasper@cvs.openbsd.org> | 2013-12-19 09:37:15 +0000 |
|---|---|---|
| committer | Jasper Lievisse Adriaanse <jasper@cvs.openbsd.org> | 2013-12-19 09:37:15 +0000 |
| commit | 3ed185fba1c7e6778e6bbff3d6fb4870dc375144 (patch) | |
| tree | 4107cbc4d773ff6564775db1a4143f81083cb8e7 | |
| parent | 71eccd9f92c0fb46676163b1201acf9c8f29bccc (diff) | |
recognize octeon 2 cpus; as found in the lanner mr326
ok miod@
| -rw-r--r-- | sys/arch/mips64/include/cpu.h | 3 | ||||
| -rw-r--r-- | sys/arch/mips64/mips64/cpu.c | 6 |
2 files changed, 7 insertions, 2 deletions
diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h index 7c036339265..ab6cae2eca6 100644 --- a/sys/arch/mips64/include/cpu.h +++ b/sys/arch/mips64/include/cpu.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.h,v 1.94 2013/03/12 09:37:16 mpi Exp $ */ +/* $OpenBSD: cpu.h,v 1.95 2013/12/19 09:37:13 jasper Exp $ */ /*- * Copyright (c) 1992, 1993 @@ -376,6 +376,7 @@ void cp0_calibrate(struct cpu_info *); #define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */ #define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ #define MIPS_LOONGSON2 0x63 /* STC LoongSon2/3 CPU ISA III+ */ +#define MIPS_OCTEON2 0x93 /* Cavium OCTEON II MIPS64R2 */ /* * MIPS FPU types. Only soft, rest is the same as cpu type. diff --git a/sys/arch/mips64/mips64/cpu.c b/sys/arch/mips64/mips64/cpu.c index ee6322991c6..ea848576067 100644 --- a/sys/arch/mips64/mips64/cpu.c +++ b/sys/arch/mips64/mips64/cpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cpu.c,v 1.50 2013/05/09 19:45:19 miod Exp $ */ +/* $OpenBSD: cpu.c,v 1.51 2013/12/19 09:37:14 jasper Exp $ */ /* * Copyright (c) 1997-2004 Opsycon AB (www.opsycon.se) @@ -200,6 +200,10 @@ cpuattach(struct device *parent, struct device *dev, void *aux) printf("Cavium OCTEON CPU"); fptype = MIPS_SOFT; break; + case MIPS_OCTEON2: + printf("Cavium OCTEON II CPU"); + fptype = MIPS_SOFT; + break; default: printf("Unknown CPU type (0x%x)", ch->type); break; |