new cpureg.h from NetBSD plus modifications to use the changed macro names

35 files changed, 1130 insertions, 1190 deletions

diff --git a/sys/arch/pmax/dev/bt478.c b/sys/arch/pmax/dev/bt478.c
index 738e8f92ba8..5c2cb0538c1 100644
--- a/sys/arch/pmax/dev/bt478.c
+++ b/sys/arch/pmax/dev/bt478.c
@@ -202,7 +202,7 @@ bt478InitColorMap (fi)
 	register VDACRegs *vdac = (VDACRegs *)(fi -> fi_vdac);
 	register int i;
 
-	*(volatile char *)MACH_PHYS_TO_UNCACHED
+	*(volatile char *)MIPS_PHYS_TO_KSEG1
 		(KN01_PHYS_COLMASK_START) = 0xff;	/* XXX */
 	wbflush();
 
diff --git a/sys/arch/pmax/dev/cfb.c b/sys/arch/pmax/dev/cfb.c
index 870075c9fbd..439d0a08568 100644
--- a/sys/arch/pmax/dev/cfb.c
+++ b/sys/arch/pmax/dev/cfb.c
@@ -313,7 +313,7 @@ cfbinit(fi, cfbaddr, unit, silent)
 	 * mapped into the user's address space uncached.
 	 */
 	fi->fi_fbu = (struct fbuaccess *)
-		MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&cfbu));
+		MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&cfbu));
 
 	/* This is glass-tty state but it's in the shared structure. Ick. */
 	fi->fi_fbu->scrInfo.max_row = 56;
diff --git a/sys/arch/pmax/dev/dc_ds.c b/sys/arch/pmax/dev/dc_ds.c
index c316c83a42d..0e29bde4b1a 100644
--- a/sys/arch/pmax/dev/dc_ds.c
+++ b/sys/arch/pmax/dev/dc_ds.c
@@ -49,11 +49,11 @@ dc_ds_consinit(dev)
 #if defined(DEBUG) && 1			/* XXX untested */
 	printf("dc_ds(%d,%d): serial console at 0x%x\n",
 	       minor(dev) >> 2, minor(dev) & 03,
-	       MACH_PHYS_TO_UNCACHED(KN01_SYS_DZ));
+	       MIPS_PHYS_TO_KSEG1(KN01_SYS_DZ));
 #endif
 	/* let any  pending PROM output from boot drain */
 	DELAY(100000);
-	dc_consinit(dev, (void *)MACH_PHYS_TO_UNCACHED(KN01_SYS_DZ));
+	dc_consinit(dev, (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_DZ));
 	return (1);
 }
 
@@ -93,7 +93,7 @@ dc_ds_attach(parent, self, aux)
 
 
 	dcaddr = (caddr_t)ca->ca_addr;
-	(void) dcattach(sc, (void*)MACH_PHYS_TO_UNCACHED(dcaddr),
+	(void) dcattach(sc, (void*)MIPS_PHYS_TO_KSEG1(dcaddr),
 			/* dtr/dsr mask: comm port only */
 			1 << DCCOMM_PORT,
 			/* rts/cts mask: none */
diff --git a/sys/arch/pmax/dev/dc_ioasic.c b/sys/arch/pmax/dev/dc_ioasic.c
index e1d2d38a0a4..583131ee7cd 100644
--- a/sys/arch/pmax/dev/dc_ioasic.c
+++ b/sys/arch/pmax/dev/dc_ioasic.c
@@ -49,10 +49,10 @@ dc_ioasic_consinit(dev)
 #if defined(DEBUG) && 0
 	printf("dc_ioasic(%d,%d): serial console at 0x%x\n",
 	       minor(dev) >> 2, minor(dev) & 03,
-	       MACH_PHYS_TO_UNCACHED(KN02_SYS_DZ));
+	       MIPS_PHYS_TO_KSEG1(KN02_SYS_DZ));
 	DELAY(100000);
 #endif
-	dc_consinit(dev, (void *)MACH_PHYS_TO_UNCACHED(KN02_SYS_DZ));
+	dc_consinit(dev, (void *)MIPS_PHYS_TO_KSEG1(KN02_SYS_DZ));
 	return(1);
 }
 
@@ -92,7 +92,7 @@ dc_ioasic_attach(parent, self, aux)
 
 	dcaddr = (caddr_t)d->iada_addr;
 	printf(" address %p", dcaddr);
-	(void) dcattach(sc, (void*)MACH_PHYS_TO_UNCACHED(dcaddr),
+	(void) dcattach(sc, (void*)MIPS_PHYS_TO_KSEG1(dcaddr),
 	/* dtr/dsr mask */	  (1<< DCPRINTER_PORT) + (1 << DCCOMM_PORT),
 #ifdef HW_FLOW_CONTROL
 	/* rts/cts mask */	  (1<< DCPRINTER_PORT) + (1 << DCCOMM_PORT),
diff --git a/sys/arch/pmax/dev/dtop.c b/sys/arch/pmax/dev/dtop.c
index f402dabe87f..c9057fa1995 100644
--- a/sys/arch/pmax/dev/dtop.c
+++ b/sys/arch/pmax/dev/dtop.c
@@ -251,7 +251,7 @@ dtopattach(parent, self, aux)
 	int i;
 
 
-	sc->poll = (poll_reg_t)MACH_PHYS_TO_UNCACHED(XINE_REG_INTR);
+	sc->poll = (poll_reg_t)MIPS_PHYS_TO_KSEG1(XINE_REG_INTR);
 	sc->data = (data_reg_t)d->iada_addr;
 
 	for (i = 0; i < DTOP_MAX_DEVICES; i++)
diff --git a/sys/arch/pmax/dev/fb_usrreq.c b/sys/arch/pmax/dev/fb_usrreq.c
index b183c32c742..f312dd66ae8 100644
--- a/sys/arch/pmax/dev/fb_usrreq.c
+++ b/sys/arch/pmax/dev/fb_usrreq.c
@@ -252,9 +252,9 @@ fbmmap(dev, off, prot)
 	len = mips_round_page(((vm_offset_t)fi->fi_fbu & PGOFSET)
 			      + sizeof(*fi->fi_fbu));
 	if (off < len)
-		return (int)mips_btop(MACH_CACHED_TO_PHYS(fi->fi_fbu) + off);
+		return (int)mips_btop(MIPS_KSEG0_TO_PHYS(fi->fi_fbu) + off);
 	off -= len;
 	if (off >= fi->fi_type.fb_size)
 		return (-1);
-	return (int)mips_btop(MACH_UNCACHED_TO_PHYS(fi->fi_pixels) + off);
+	return (int)mips_btop(MIPS_KSEG1_TO_PHYS(fi->fi_pixels) + off);
 }
diff --git a/sys/arch/pmax/dev/mfb.c b/sys/arch/pmax/dev/mfb.c
index ac6123a6f67..535be032dd9 100644
--- a/sys/arch/pmax/dev/mfb.c
+++ b/sys/arch/pmax/dev/mfb.c
@@ -336,7 +336,7 @@ mfbinit(fi, mfbaddr, unit, silent)
 	 * mapped into the user's address space uncached.
 	 */
 	fi->fi_fbu = (struct fbuaccess *)
-		MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&mfbu));
+		MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&mfbu));
 
 	/* This is glass-tty state but it's in the shared structure. Ick. */
 	fi->fi_fbu->scrInfo.max_row = 67;
diff --git a/sys/arch/pmax/dev/pm_ds.c b/sys/arch/pmax/dev/pm_ds.c
index 8435563d59d..64144ed32d8 100644
--- a/sys/arch/pmax/dev/pm_ds.c
+++ b/sys/arch/pmax/dev/pm_ds.c
@@ -162,16 +162,16 @@ pminit(fi, unit, cold_console_flag)
 
 	/* Set address of frame buffer... */
 	fi->fi_unit = unit;
-	fi->fi_pixels = (caddr_t)MACH_PHYS_TO_UNCACHED(KN01_PHYS_FBUF_START);
-	fi->fi_base = (caddr_t)MACH_PHYS_TO_UNCACHED(KN01_SYS_PCC);
-	fi->fi_vdac = (caddr_t)MACH_PHYS_TO_UNCACHED(KN01_SYS_VDAC);
+	fi->fi_pixels = (caddr_t)MIPS_PHYS_TO_KSEG1(KN01_PHYS_FBUF_START);
+	fi->fi_base = (caddr_t)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC);
+	fi->fi_vdac = (caddr_t)MIPS_PHYS_TO_KSEG1(KN01_SYS_VDAC);
 
 	/* check for no frame buffer */
 	if (badaddr((char *)fi->fi_pixels, 4))
 		return (0);
 
 	/* Fill in the stuff that differs from monochrome to color. */
-	if (*(volatile u_short *)MACH_PHYS_TO_UNCACHED(KN01_SYS_CSR) &
+	if (*(volatile u_short *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) &
 	    KN01_CSR_MONO) {
 		fi->fi_type.fb_depth = 1;
 	}
@@ -188,7 +188,7 @@ pminit(fi, unit, cold_console_flag)
 	 * XXX can go away when MI support for d_mmap entrypoints added.
 	 */
 	fi->fi_fbu = (struct fbuaccess *)
-		MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&pmu));
+		MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&pmu));
 
 	fi->fi_glasstty = &pmfb;
 
diff --git a/sys/arch/pmax/dev/sfb.c b/sys/arch/pmax/dev/sfb.c
index cfb003811df..ac77d9884de 100644
--- a/sys/arch/pmax/dev/sfb.c
+++ b/sys/arch/pmax/dev/sfb.c
@@ -291,7 +291,7 @@ sfbinit(fi, base, unit, silent)
 	 * mapped into the user's address space uncached.
 	 */
 	fi->fi_fbu = (struct fbuaccess *)
-		MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&sfbu));
+		MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&sfbu));
 
 	/* This is glass-tty state but it's in the shared structure. Ick. */
 	fi->fi_fbu->scrInfo.max_row = 67;
diff --git a/sys/arch/pmax/dev/sii.c b/sys/arch/pmax/dev/sii.c
index b010abfccd4..37df3adda90 100644
--- a/sys/arch/pmax/dev/sii.c
+++ b/sys/arch/pmax/dev/sii.c
@@ -239,7 +239,7 @@ old_siiattach(parent, self, aux)
 	register struct confargs *ca = aux;
 	register struct siisoftc *sc = (struct siisoftc *) self;
 
-	sc->sc_regs = (SIIRegs *)MACH_PHYS_TO_UNCACHED(ca->ca_addr);
+	sc->sc_regs = (SIIRegs *)MIPS_PHYS_TO_KSEG1(ca->ca_addr);
 	sc->sc_flags = sc->sc_dev.dv_cfdata->cf_flags;
 
 	siiattach(sc);
diff --git a/sys/arch/pmax/dev/sii_ds.c b/sys/arch/pmax/dev/sii_ds.c
index 5d5789bd3c3..53601cda2ba 100644
--- a/sys/arch/pmax/dev/sii_ds.c
+++ b/sys/arch/pmax/dev/sii_ds.c
@@ -43,7 +43,7 @@ struct cfattach sii_ds_ca = {
 
 
 /* define a safe address in the SCSI buffer for doing status & message DMA */
-#define SII_BUF_ADDR	(MACH_PHYS_TO_UNCACHED(KN01_SYS_SII_B_START) \
+#define SII_BUF_ADDR	(MIPS_PHYS_TO_KSEG1(KN01_SYS_SII_B_START) \
 		+ SII_MAX_DMA_XFER_LENGTH * 14)
 
 /*
@@ -64,10 +64,10 @@ sii_ds_match(parent, match, aux)
 
 	/* XXX check for bad address, untested */
 	siiaddr = (void *)ca->ca_addr;
-	if (siiaddr != (void *)MACH_PHYS_TO_UNCACHED(KN01_SYS_SII)) {
+	if (siiaddr != (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_SII)) {
 		printf("(siimatch: bad addr %x, substituting %x\n",
-			ca->ca_addr, MACH_PHYS_TO_UNCACHED(KN01_SYS_SII));
-		siiaddr = (void *)MACH_PHYS_TO_UNCACHED(KN01_SYS_SII);
+			ca->ca_addr, MIPS_PHYS_TO_KSEG1(KN01_SYS_SII));
+		siiaddr = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_SII);
 	}
 	if (badaddr(siiaddr, 4))
 		return (0);
@@ -83,10 +83,10 @@ sii_ds_attach(parent, self, aux)
 	register struct confargs *ca = aux;
 	register struct siisoftc *sc = (struct siisoftc *) self;
 
-	sc->sc_regs = (SIIRegs *)MACH_PHYS_TO_UNCACHED(ca->ca_addr);
+	sc->sc_regs = (SIIRegs *)MIPS_PHYS_TO_KSEG1(ca->ca_addr);
 
 	/* set up scsi buffer.  XXX Why statically allocated? */
-	sc->sc_buf = (void*)(MACH_PHYS_TO_UNCACHED(KN01_SYS_SII_B_START));
+	sc->sc_buf = (void*)(MIPS_PHYS_TO_KSEG1(KN01_SYS_SII_B_START));
 
 siiattach(sc);
 
diff --git a/sys/arch/pmax/dev/xcfb.c b/sys/arch/pmax/dev/xcfb.c
index e51d8d9a1ae..34aba63174d 100644
--- a/sys/arch/pmax/dev/xcfb.c
+++ b/sys/arch/pmax/dev/xcfb.c
@@ -243,7 +243,7 @@ xcfbinit(fi, base, unit, silent)
 	 * runs faster in cached address space, but the X server is going
 	 * to blow away the data cache whenever it updates the screen, so..
 	 */
-	base = (char *) MACH_PHYS_TO_UNCACHED(XINE_PHYS_CFB_START);
+	base = (char *) MIPS_PHYS_TO_KSEG1(XINE_PHYS_CFB_START);
 	
 	/* Fill in main frame buffer info struct. */
 	fi->fi_unit = unit;
@@ -272,7 +272,7 @@ xcfbinit(fi, base, unit, silent)
 	 * mapped into the user's address space uncached.
 	 */
 	fi->fi_fbu = (struct fbuaccess *)
-		MACH_PHYS_TO_UNCACHED(MACH_CACHED_TO_PHYS(&xcfbu));
+		MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(&xcfbu));
 
 	/* This is glass-tty state but it's in the shared structure. Ick. */
 	fi->fi_fbu->scrInfo.max_row = 50;
diff --git a/sys/arch/pmax/include/cpu.h b/sys/arch/pmax/include/cpu.h
index f1d1b07af6e..d1fec14aa49 100644
--- a/sys/arch/pmax/include/cpu.h
+++ b/sys/arch/pmax/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.6 1998/05/08 19:32:49 millert Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.7 1998/05/18 00:28:11 millert Exp $	*/
 /*	$NetBSD: cpu.h,v 1.15 1996/03/23 20:28:19 jonathan Exp $	*/
 
 /*-
@@ -45,10 +45,29 @@
 #include <machine/machConst.h>
 
 /*
- * Exported definitions unique to NetBSD/mips cpu support.
+ * Exported definitions unique to OpenBSD/mips cpu support.
  */
 
 /*
+ * Macros to find the CPU architecture we're on at run-time,
+ * or if possible, at compile-time.
+ */
+
+#if (MIPS1 + MIPS3) == 1
+#ifdef MIPS1
+# define CPUISMIPS3	0
+#endif /* mips1 */
+
+#ifdef MIPS3
+#  define CPUISMIPS3	 1
+#endif /* mips1 */
+
+#else /* run-time test */
+extern int cpu_arch;
+#define CPUISMIPS3	(cpu_arch == 3)
+#endif /* run-time test */
+
+/*
  * definitions of cpu-dependent requirements
  * referenced in generic code
  */
@@ -73,14 +92,14 @@ struct clockframe {
  */
 
 /* r3000 versions */
-#define	CLKF_USERMODE_R3K(framep)	((framep)->sr & MACH_SR_KU_PREV)
+#define	CLKF_USERMODE_R3K(framep)	((framep)->sr & MIPS_SR_KU_PREV)
 #define	CLKF_BASEPRI_R3K(framep)	\
-	((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) == 0)
+	((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0)
 
 /* r4000 versions */
-#define	CLKF_USERMODE_R4K(framep)	((framep)->sr & MACH_SR_KSU_USER)
+#define	CLKF_USERMODE_R4K(framep)	((framep)->sr & MIPS_SR_KSU_USER)
 #define	CLKF_BASEPRI_R4K(framep)	\
-	((~(framep)->sr & (MACH_INT_MASK | MACH_SR_INT_ENAB)) == 0)
+	((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENAB)) == 0)
 
 #define	CLKF_PC(framep)		((framep)->pc)
 #define	CLKF_INTR(framep)	(0)
diff --git a/sys/arch/pmax/include/cpuregs.h b/sys/arch/pmax/include/cpuregs.h
index a5f197211e0..8fc46792f21 100644
--- a/sys/arch/pmax/include/cpuregs.h
+++ b/sys/arch/pmax/include/cpuregs.h
@@ -1,4 +1,5 @@
-/*	$NetBSD: cpuregs.h,v 1.5 1996/03/28 11:34:05 jonathan Exp $	*/
+/*	$OpenBSD: cpuregs.h,v 1.4 1998/05/18 00:28:12 millert Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.14 1998/04/23 10:32:08 jonathan Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -57,52 +58,43 @@
  *	v 9.1 89/09/18 17:33:00 shirriff Exp  SPRITE (DECWRL)
  */
 
-#ifndef _MACHCONST
-#define _MACHCONST
+#ifndef _PMAX_CPUREGS_H_
+#define _PMAX_CPUREGS_H_
 
-#define MACH_KUSEG_ADDR			0x0
-#define MACH_CACHED_MEMORY_ADDR		0x80000000
-#define MACH_UNCACHED_MEMORY_ADDR	0xa0000000
-#define MACH_KSEG2_ADDR			0xc0000000
-#define MACH_MAX_MEM_ADDR		0xbe000000
-#define	MACH_RESERVED_ADDR		0xbfc80000
-
-/* XXX - this is just to make libkvm happy - all MACH_CAHED...
-         should be changed to CAHED etc. to be in sync with 
-         the arc
-*/
-#define	CACHED_TO_PHYS(x)	((unsigned)(x) & 0x1fffffff)
-
-#define	MACH_CACHED_TO_PHYS(x)	((unsigned)(x) & 0x1fffffff)
-#define	MACH_PHYS_TO_CACHED(x)	((unsigned)(x) | MACH_CACHED_MEMORY_ADDR)
-#define	MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
-#define	MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR)
+/*
+ * Address space.
+ * 32-bit mips CPUS partition their 32-bit address space into four segments:
+ *
+ * kuseg   0x00000000 - 0x7fffffff  User virtual mem,  mapped
+ * kseg0   0x80000000 - 0x9fffffff  Physical memory, cached, unmapped
+ * kseg1   0xa0000000 - 0xbfffffff  Physical memory, uncached, unmapped
+ * kseg2   0xc0000000 - 0xffffffff  kernel-virtual,  mapped
+ *
+ * mips1 physical memory is limited to 512Mbytes, which is
+ * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
+ * Caching of mapped addresses is controlled by bits in the TLB entry.
+ */
 
-/* Map virtual address to index in r4k virtually-indexed cache */
-#define MIPS_R4K_VA_TO_CINDEX(x) \
-		((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR)
+#define MIPS_KUSEG_START		0x0
+#define MIPS_KSEG0_START		0x80000000
+#define MIPS_KSEG1_START		0xa0000000
+#define MIPS_KSEG2_START		0xc0000000
+#define MIPS_MAX_MEM_ADDR		0xbe000000
+#define	MIPS_RESERVED_ADDR		0xbfc80000
 
-/* XXX compatibility with Pica port */
-#define MACH_VA_TO_CINDEX(x) MIPS_R4K_VA_TO_CINDEX(x)
+#define	MIPS_KSEG0_TO_PHYS(x)	((unsigned)(x) & 0x1fffffff)
+#define	MIPS_PHYS_TO_KSEG0(x)	((unsigned)(x) | MIPS_KSEG0_START)
+#define	MIPS_KSEG1_TO_PHYS(x)	((unsigned)(x) & 0x1fffffff)
+#define	MIPS_PHYS_TO_KSEG1(x)	((unsigned)(x) | MIPS_KSEG1_START)
 
+/* Map virtual address to index in mips3 r4k virtually-indexed cache */
+#define MIPS3_VA_TO_CINDEX(x) \
+		((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
 
-/*
- * XXX
- * Port-specific constants:
- * Kernel virtual address at which kernel is loaded, and
- * Kernel virtual address for user page table entries
- * (i.e., the address for the context register).
+/* XXX - this is just to make libkvm happy until other mips platforms
+ * use the new-style macros.
  */
-#ifdef pmax
-#define MACH_CODE_START			0x80030000
-#define VMMACH_PTE_BASE			0xFFC00000
-#endif	/* pmax */
-
-#ifdef pica
-#define MACH_CODE_START			0x80080000
-#define VMMACH_PTE_BASE			0xFF800000
-#endif	/* pica */
-
+#define CACHED_TO_PHYS(x)       MIPS_KSEG0_TO_PHYS(x)
 
 
 /*
@@ -110,37 +102,29 @@
  *
  * Bits common to r3000 and r4000:
  *
- *	MACH_CR_BR_DELAY	Exception happened in branch delay slot.
- *	MACH_CR_COP_ERR		Coprocessor error.
- *	MACH_CR_IP		Interrupt pending bits defined below.
+ *	MIPS_CR_BR_DELAY	Exception happened in branch delay slot.
+ *	MIPS_CR_COP_ERR		Coprocessor error.
+ *	MIPS_CR_IP		Interrupt pending bits defined below.
  *				(same meaning as in CAUSE register).
- *	MACH_CR_EXC_CODE	The exception type (see exception codes below).
+ *	MIPS_CR_EXC_CODE	The exception type (see exception codes below).
  *
  * Differences:
  *  r3k has 4 bits of execption type, r4k has 5 bits.
  */
-#define MACH_CR_BR_DELAY	0x80000000
-#define MACH_CR_COP_ERR		0x30000000
-#define MIPS_3K_CR_EXC_CODE	0x0000003C
-#define MIPS_4K_CR_EXC_CODE	0x0000007C
-#define MACH_CR_IP		0x0000FF00
-#define MACH_CR_EXC_CODE_SHIFT	2
-
-#ifdef pmax /* XXX not used any more, only to satisfy regression tests */
-#define MACH_CR_EXC_CODE	MIPS_3K_CR_EXC_CODE
-#endif	/* pmax */
-#ifdef pica
-#define MACH_CR_EXC_CODE	MIPS_4K_CR_EXC_CODE
-#endif	/* pica */
-
+#define MIPS_CR_BR_DELAY	0x80000000
+#define MIPS_CR_COP_ERR		0x30000000
+#define MIPS1_CR_EXC_CODE	0x0000003C	/* four bits */
+#define MIPS3_CR_EXC_CODE	0x0000007C	/* five bits */
+#define MIPS_CR_IP		0x0000FF00
+#define MIPS_CR_EXC_CODE_SHIFT	2
 
 /*
  * The bits in the status register.  All bits are active when set to 1.
  *
  *	R3000 status register fields:
- *	MACH_SR_CO_USABILITY	Control the usability of the four coprocessors.
- *	MACH_SR_BOOT_EXC_VEC	Use alternate exception vectors.
- *	MACH_SR_TLB_SHUTDOWN	TLB disabled.
+ *	MIPS_SR_CO_USABILITY	Control the usability of the four coprocessors.
+ *	MIPS_SR_BOOT_EXC_VEC	Use alternate exception vectors.
+ *	MIPS_SR_TLB_SHUTDOWN	TLB disabled.
  *
  *	MIPS_SR_INT_IE		Master (current) interrupt enable bit.
  *
@@ -150,23 +134,23 @@
  *	r3k has a 3-entry stack of kernel/user bits, whereas the
  *	r4k has kernel/supervisor/user.
  */
-#define MACH_SR_COP_USABILITY	0xf0000000
-#define MACH_SR_COP_0_BIT	0x10000000
-#define MACH_SR_COP_1_BIT	0x20000000
+#define MIPS_SR_COP_USABILITY	0xf0000000
+#define MIPS_SR_COP_0_BIT	0x10000000
+#define MIPS_SR_COP_1_BIT	0x20000000
 
 	/* r4k and r3k differences, see below */
 
-#define MACH_SR_BOOT_EXC_VEC	0x00400000
-#define MACH_SR_TLB_SHUTDOWN	0x00200000
+#define MIPS_SR_BOOT_EXC_VEC	0x00400000
+#define MIPS_SR_TLB_SHUTDOWN	0x00200000
 
 	/* r4k and r3k differences, see below */
 
 #define MIPS_SR_INT_IE		0x00000001
-/*#define MACH_SR_MBZ		0x0f8000c0*/	/* Never used, true for r3k */
-/*#define MACH_SR_INT_MASK	0x0000ff00*/
+/*#define MIPS_SR_MBZ		0x0f8000c0*/	/* Never used, true for r3k */
+/*#define MIPS_SR_INT_MASK	0x0000ff00*/
 
-#define MACH_SR_INT_ENAB	MIPS_SR_INT_IE	/* backwards compatibility */
-#define MACH_SR_INT_ENA_CUR	MIPS_SR_INT_IE	/* backwards compatibility */
+#define MIPS_SR_INT_ENAB	MIPS_SR_INT_IE	/* backwards compatibility */
+#define MIPS_SR_INT_ENA_CUR	MIPS_SR_INT_IE	/* backwards compatibility */
 
 
 
@@ -174,86 +158,85 @@
  * The R2000/R3000-specific status register bit definitions.
  * all bits are active when set to 1.
  *
- *	MACH_SR_PARITY_ERR	Parity error.
- *	MACH_SR_CACHE_MISS	Most recent D-cache load resulted in a miss.
- *	MACH_SR_PARITY_ZERO	Zero replaces outgoing parity bits.
- *	MACH_SR_SWAP_CACHES	Swap I-cache and D-cache.
- *	MACH_SR_ISOL_CACHES	Isolate D-cache from main memory.
+ *	MIPS_SR_PARITY_ERR	Parity error.
+ *	MIPS_SR_CACHE_MISS	Most recent D-cache load resulted in a miss.
+ *	MIPS_SR_PARITY_ZERO	Zero replaces outgoing parity bits.
+ *	MIPS_SR_SWAP_CACHES	Swap I-cache and D-cache.
+ *	MIPS_SR_ISOL_CACHES	Isolate D-cache from main memory.
  *				Interrupt enable bits defined below.
- *	MACH_SR_KU_OLD		Old kernel/user mode bit. 1 => user mode.
- *	MACH_SR_INT_ENA_OLD	Old interrupt enable bit.
- *	MACH_SR_KU_PREV		Previous kernel/user mode bit. 1 => user mode.
- *	MACH_SR_INT_ENA_PREV	Previous interrupt enable bit.
- *	MACH_SR_KU_CUR		Current kernel/user mode bit. 1 => user mode.
+ *	MIPS_SR_KU_OLD		Old kernel/user mode bit. 1 => user mode.
+ *	MIPS_SR_INT_ENA_OLD	Old interrupt enable bit.
+ *	MIPS_SR_KU_PREV		Previous kernel/user mode bit. 1 => user mode.
+ *	MIPS_SR_INT_ENA_PREV	Previous interrupt enable bit.
+ *	MIPS_SR_KU_CUR		Current kernel/user mode bit. 1 => user mode.
  */
 
-#define MIPS_3K_PARITY_ERR      0x00100000
-#define MIPS_3K_CACHE_MISS      0x00080000
-#define MIPS_3K_PARITY_ZERO     0x00040000
-#define MIPS_3K_SWAP_CACHES     0x00020000
-#define MIPS_3K_ISOL_CACHES     0x00010000
+#define MIPS1_PARITY_ERR	0x00100000
+#define MIPS1_CACHE_MISS	0x00080000
+#define MIPS1_PARITY_ZERO	0x00040000
+#define MIPS1_SWAP_CACHES	0x00020000
+#define MIPS1_ISOL_CACHES	0x00010000
 
-#define MIPS_3K_SR_KU_OLD	0x00000020	/* 2nd stacked KU/IE*/
-#define MIPS_3K_SR_INT_ENA_OLD	0x00000010	/* 2nd stacked KU/IE*/
-#define MIPS_3K_SR_KU_PREV	0x00000008	/* 1st stacked KU/IE*/
-#define MIPS_3K_SR_INT_ENA_PREV	0x00000004	/* 1st stacked KU/IE*/
-#define MIPS_3K_SR_KU_CUR	0x00000002	/* current KU */
+#define MIPS1_SR_KU_OLD		0x00000020	/* 2nd stacked KU/IE*/
+#define MIPS1_SR_INT_ENA_OLD	0x00000010	/* 2nd stacked KU/IE*/
+#define MIPS1_SR_KU_PREV	0x00000008	/* 1st stacked KU/IE*/
+#define MIPS1_SR_INT_ENA_PREV	0x00000004	/* 1st stacked KU/IE*/
+#define MIPS1_SR_KU_CUR		0x00000002	/* current KU */
 
 /* backwards compatibility */
-#define MACH_SR_PARITY_ERR	MIPS_3K_PARITY_ERR
-#define MACH_SR_CACHE_MISS	MIPS_3K_CACHE_MISS
-#define MACH_SR_PARITY_ZERO	MIPS_3K_PARITY_ZERO
-#define MACH_SR_SWAP_CACHES	MIPS_3K_SWAP_CACHES
-#define MACH_SR_ISOL_CACHES	MIPS_3K_ISOL_CACHES
-
-#define MACH_SR_KU_OLD		MIPS_3K_SR_KU_OLD
-#define MACH_SR_INT_ENA_OLD	MIPS_3K_SR_INT_ENA_OLD
-#define MACH_SR_KU_PREV		MIPS_3K_SR_KU_PREV
-#define MACH_SR_KU_CUR		MIPS_3K_SR_KU_CUR
-#define MACH_SR_INT_ENA_PREV	MIPS_3K_SR_INT_ENA_PREV
-
+#define MIPS_SR_PARITY_ERR	MIPS1_PARITY_ERR
+#define MIPS_SR_CACHE_MISS	MIPS1_CACHE_MISS
+#define MIPS_SR_PARITY_ZERO	MIPS1_PARITY_ZERO
+#define MIPS_SR_SWAP_CACHES	MIPS1_SWAP_CACHES
+#define MIPS_SR_ISOL_CACHES	MIPS1_ISOL_CACHES
+
+#define MIPS_SR_KU_OLD		MIPS1_SR_KU_OLD
+#define MIPS_SR_INT_ENA_OLD	MIPS1_SR_INT_ENA_OLD
+#define MIPS_SR_KU_PREV		MIPS1_SR_KU_PREV
+#define MIPS_SR_KU_CUR		MIPS1_SR_KU_CUR
+#define MIPS_SR_INT_ENA_PREV	MIPS1_SR_INT_ENA_PREV
 
 /*
  * R4000 status register bit definitons,
  * where different from r2000/r3000.
  */
-#define MIPS_4K_SR_RP   	0x08000000
-#define MIPS_4K_SR_FR_32	0x04000000
-#define MIPS_4K_SR_RE   	0x02000000
-
-#define MIPS_4K_SR_SOFT_RESET	0x00100000
-#define MIPS_4K_SR_DIAG_CH	0x00040000
-#define MIPS_4K_SR_DIAG_CE	0x00020000
-#define MIPS_4K_SR_DIAG_PE	0x00010000
-#define MIPS_4K_SR_KX		0x00000080
-#define MIPS_4K_SR_SX		0x00000040
-#define MIPS_4K_SR_UX		0x00000020
-#define MIPS_4K_SR_KSU_MASK	0x00000018
-#define MIPS_4K_SR_KSU_USER	0x00000010
-#define MIPS_4K_SR_KSU_SUPER	0x00000008
-#define MIPS_4K_SR_KSU_KERNEL	0x00000000
-#define MIPS_4K_SR_ERL		0x00000004
-#define MIPS_4K_SR_EXL		0x00000002
+#define MIPS3_SR_RP		0x08000000
+#define MIPS3_SR_FR_32		0x04000000
+#define MIPS3_SR_RE		0x02000000
+
+#define MIPS3_SR_SOFT_RESET	0x00100000
+#define MIPS3_SR_DIAG_CH	0x00040000
+#define MIPS3_SR_DIAG_CE	0x00020000
+#define MIPS3_SR_DIAG_PE	0x00010000
+#define MIPS3_SR_KX		0x00000080
+#define MIPS3_SR_SX		0x00000040
+#define MIPS3_SR_UX		0x00000020
+#define MIPS3_SR_KSU_MASK	0x00000018
+#define MIPS3_SR_KSU_USER	0x00000010
+#define MIPS3_SR_KSU_SUPER	0x00000008
+#define MIPS3_SR_KSU_KERNEL	0x00000000
+#define MIPS3_SR_ERL		0x00000004
+#define MIPS3_SR_EXL		0x00000002
 
 /* backwards compatibility with names used in Pica port */
-#define MACH_SR_RP		MIPS_4K_SR_RP   
-#define MACH_SR_FR_32		MIPS_4K_SR_FR_32
-#define MACH_SR_RE		MIPS_4K_SR_RE   
-
-#define MACH_SR_SOFT_RESET	MIPS_4K_SR_SOFT_RESET
-#define MACH_SR_DIAG_CH		MIPS_4K_SR_DIAG_CH
-#define MACH_SR_DIAG_CE		MIPS_4K_SR_DIAG_CE
-#define MACH_SR_DIAG_PE		MIPS_4K_SR_DIAG_PE
-#define MACH_SR_KX		MIPS_4K_SR_KX
-#define MACH_SR_SX		MIPS_4K_SR_SX
-#define MACH_SR_UX		MIPS_4K_SR_UX
-
-#define MACH_SR_KSU_MASK	MIPS_4K_SR_KSU_MASK
-#define MACH_SR_KSU_USER	MIPS_4K_SR_KSU_USER
-#define MACH_SR_KSU_SUPER	MIPS_4K_SR_KSU_SUPER
-#define MACH_SR_KSU_KERNEL	MIPS_4K_SR_KSU_KERNEL
-#define MACH_SR_ERL		MIPS_4K_SR_ERL
-#define MACH_SR_EXL		MIPS_4K_SR_EXL
+#define MIPS_SR_RP		MIPS3_SR_RP   
+#define MIPS_SR_FR_32		MIPS3_SR_FR_32
+#define MIPS_SR_RE		MIPS3_SR_RE   
+
+#define MIPS_SR_SOFT_RESET	MIPS3_SR_SOFT_RESET
+#define MIPS_SR_DIAG_CH		MIPS3_SR_DIAG_CH
+#define MIPS_SR_DIAG_CE		MIPS3_SR_DIAG_CE
+#define MIPS_SR_DIAG_PE		MIPS3_SR_DIAG_PE
+#define MIPS_SR_KX		MIPS3_SR_KX
+#define MIPS_SR_SX		MIPS3_SR_SX
+#define MIPS_SR_UX		MIPS3_SR_UX
+
+#define MIPS_SR_KSU_MASK	MIPS3_SR_KSU_MASK
+#define MIPS_SR_KSU_USER	MIPS3_SR_KSU_USER
+#define MIPS_SR_KSU_SUPER	MIPS3_SR_KSU_SUPER
+#define MIPS_SR_KSU_KERNEL	MIPS3_SR_KSU_KERNEL
+#define MIPS_SR_ERL		MIPS3_SR_ERL
+#define MIPS_SR_EXL		MIPS3_SR_EXL
 
 
 /*
@@ -261,344 +244,282 @@
  * If a bit in the mask is 1 then the interrupt is enabled (or pending).
  */
 #define MIPS_INT_MASK		0xff00
-#define MACH_INT_MASK_5		0x8000
-#define MACH_INT_MASK_4		0x4000
-#define MACH_INT_MASK_3		0x2000
-#define MACH_INT_MASK_2		0x1000
-#define MACH_INT_MASK_1		0x0800
-#define MACH_INT_MASK_0		0x0400
+#define MIPS_INT_MASK_5		0x8000
+#define MIPS_INT_MASK_4		0x4000
+#define MIPS_INT_MASK_3		0x2000
+#define MIPS_INT_MASK_2		0x1000
+#define MIPS_INT_MASK_1		0x0800
+#define MIPS_INT_MASK_0		0x0400
 #define MIPS_HARD_INT_MASK	0xfc00
-#define MACH_SOFT_INT_MASK_1	0x0200
-#define MACH_SOFT_INT_MASK_0	0x0100
-
-#ifdef pmax
-#define MACH_INT_MASK		MIPS_INT_MASK
-#define MACH_HARD_INT_MASK	MIPS_HARD_INT_MASK
-#endif
-
-/* r4000 has on-chip timer at INT_MASK_5 */
-#ifdef pica
-#define MACH_INT_MASK		(MIPS_INT_MASK &  ~MACH_INT_MASK_5)
-#define MACH_HARD_INT_MASK	(MIPS_HARD_INT_MASK & ~MACH_INT_MASK_5)
-#endif
-
+#define MIPS_SOFT_INT_MASK_1	0x0200
+#define MIPS_SOFT_INT_MASK_0	0x0100
 
 
 /*
- * The bits in the context register.
+ * nesting interrupt masks.
  */
-#define MIPS_3K_CNTXT_PTE_BASE  0xFFE00000
-#define MIPS_3K_CNTXT_BAD_VPN   0x001FFFFC
-
-#define MIPS_4K_CNTXT_PTE_BASE	0xFF800000
-#define MIPS_4K_CNTXT_BAD_VPN2	0x007FFFF0
+#define MIPS_INT_MASK_SPL_SOFT0	MIPS_SOFT_INT_MASK_0
+#define MIPS_INT_MASK_SPL_SOFT1	(MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0)
+#define MIPS_INT_MASK_SPL0	(MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1)
+#define MIPS_INT_MASK_SPL1	(MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0)
+#define MIPS_INT_MASK_SPL2	(MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1)
+#define MIPS_INT_MASK_SPL3	(MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2)
+#define MIPS_INT_MASK_SPL4	(MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3)
+#define MIPS_INT_MASK_SPL5	(MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4)
 
 /*
- * Backwards compatbility -- XXX more thought
+ * mips3 CPUs have on-chip timer at INT_MASK_5. We don't support it yet.
  */
-#ifdef pmax
-#define MACH_CNTXT_PTE_BASE	MIPS_3K_CNTXT_PTE_BASE
-#define MACH_CNTXT_BAD_VPN	MIPS_3K_CNTXT_BAD_VPN
-#endif	/* pmax */
+#define MIPS3_INT_MASK			(MIPS_INT_MASK &  ~MIPS_INT_MASK_5)
+#define MIPS3_HARD_INT_MASK		(MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
 
-#ifdef pica
-#define MACH_CNTXT_PTE_BASE	MIPS_4K_CNTXT_PTE_BASE
-#define MACH_CNTXT_BAD_VPN2	MIPS_4K_CNTXT_BAD_VPN2
-#endif	/* pica */
 
+/*
+ * The bits in the context register.
+ */
+#define MIPS1_CNTXT_PTE_BASE	0xFFE00000
+#define MIPS1_CNTXT_BAD_VPN	0x001FFFFC
 
+#define MIPS3_CNTXT_PTE_BASE	0xFF800000
+#define MIPS3_CNTXT_BAD_VPN2	0x007FFFF0
 
 /*
  * Location of exception vectors.
  *
  * Common vectors:  reset and UTLB miss.
  */
-#define MACH_RESET_EXC_VEC	0xBFC00000
-#define MACH_UTLB_MISS_EXC_VEC	0x80000000
+#define MIPS_RESET_EXC_VEC	0xBFC00000
+#define MIPS_UTLB_MISS_EXC_VEC	0x80000000
 
 /*
  * R3000 general exception vector (everything else)
  */
-#define MIPS_3K_GEN_EXC_VEC	0x80000080
+#define MIPS1_GEN_EXC_VEC	0x80000080
 
 /*
  * R4000 MIPS-III exception vectors
  */
-#define MIPS_4K_XTLB_MISS_EXC_VEC	0x80000080
-#define MIPS_4K_CACHE_ERR_EXC_VEC	0x80000100
-#define MIPS_4K_GEN_EXC_VEC		0x80000180
-
-/*
- * Backwards compatbility -- XXX more thought
- */
-#ifdef pmax
-#define MACH_GEN_EXC_VEC	MIPS_3K_GEN_EXC_VEC
-#endif	/* pmax */
-
-#ifdef pica
-#define MACH_GEN_EXC_VEC	MIPS_4K_GEN_EXC_VEC
-#define MACH_TLB_MISS_EXC_VEC	MACH_UTLB_MISS_EXC_VEC	/* locore compat */
-#define MACH_XTLB_MISS_EXC_VEC	MIPS_4K_XTLB_MISS_EXC_VEC
-#define MACH_CACHE_ERR_EXC_VEC	MIPS_4K_CACHE_ERR_EXC_VEC
-#endif	/* pica */
-
-
+#define MIPS3_XTLB_MISS_EXC_VEC	0x80000080
+#define MIPS3_CACHE_ERR_EXC_VEC	0x80000100
+#define MIPS3_GEN_EXC_VEC	0x80000180
 
 /*
  * Coprocessor 0 registers:
  *
- *	MACH_COP_0_TLB_INDEX	TLB index.
- *	MACH_COP_0_TLB_RANDOM	TLB random.
- *	MACH_COP_0_TLB_LOW	r3k TLB entry low.
- *	MACH_COP_0_TLB_LO0	r4k TLB entry low.
- *	MACH_COP_0_TLB_LO1	r4k TLB entry low, extended.
- *	MACH_COP_0_TLB_CONTEXT	TLB context.
- *	MACH_COP_0_BAD_VADDR	Bad virtual address.
- *	MACH_COP_0_TLB_HI	TLB entry high.
- *	MACH_COP_0_STATUS_REG	Status register.
- *	MACH_COP_0_CAUSE_REG	Exception cause register.
- *	MACH_COP_0_EXC_PC	Exception PC.
- *	MACH_COP_0_PRID		Processor revision identifier.
+ *	MIPS_COP_0_TLB_INDEX	TLB index.
+ *	MIPS_COP_0_TLB_RANDOM	TLB random.
+ *	MIPS_COP_0_TLB_LOW	r3k TLB entry low.
+ *	MIPS_COP_0_TLB_LO0	r4k TLB entry low.
+ *	MIPS_COP_0_TLB_LO1	r4k TLB entry low, extended.
+ *	MIPS_COP_0_TLB_CONTEXT	TLB context.
+ *	MIPS_COP_0_BAD_VADDR	Bad virtual address.
+ *	MIPS_COP_0_TLB_HI	TLB entry high.
+ *	MIPS_COP_0_STATUS_REG	Status register.
+ *	MIPS_COP_0_CAUSE_REG	Exception cause register.
+ *	MIPS_COP_0_EXC_PC	Exception PC.
+ *	MIPS_COP_0_PRID		Processor revision identifier.
  */
-#define MACH_COP_0_TLB_INDEX	$0
-#define MACH_COP_0_TLB_RANDOM	$1
+#define MIPS_COP_0_TLB_INDEX	$0
+#define MIPS_COP_0_TLB_RANDOM	$1
 	/* Name and meaning of  TLB bits for $2 differ on r3k and r4k. */
 
-#define MACH_COP_0_TLB_CONTEXT	$4
+#define MIPS_COP_0_TLB_CONTEXT	$4
 					/* $5 and $6 new with MIPS-III */
-#define MACH_COP_0_BAD_VADDR	$8
-#define MACH_COP_0_TLB_HI	$10
-#define MACH_COP_0_STATUS_REG	$12
-#define MACH_COP_0_CAUSE_REG	$13
-#define MACH_COP_0_EXC_PC	$14
-#define MACH_COP_0_PRID		$15
+#define MIPS_COP_0_BAD_VADDR	$8
+#define MIPS_COP_0_TLB_HI	$10
+#define MIPS_COP_0_STATUS_REG	$12
+#define MIPS_COP_0_CAUSE_REG	$13
+#define MIPS_COP_0_EXC_PC	$14
+#define MIPS_COP_0_PRID		$15
 
 
 /* r3k-specific */
-#define MACH_COP_0_TLB_LOW	$2
+#define MIPS_COP_0_TLB_LOW	$2
 
 /* MIPS-III additions */
-#define MACH_COP_0_TLB_LO0	$2
-#define MACH_COP_0_TLB_LO1	$3
+#define MIPS_COP_0_TLB_LO0	$2
+#define MIPS_COP_0_TLB_LO1	$3
+
+#define MIPS_COP_0_TLB_PG_MASK	$5
+#define MIPS_COP_0_TLB_WIRED	$6
 
-#define MACH_COP_0_TLB_PG_MASK	$5
-#define MACH_COP_0_TLB_WIRED	$6
+#define MIPS_COP_0_COUNT	$9
+#define MIPS_COP_0_COMPARE	$11
 
-#define MACH_COP_0_CONFIG	$16
-#define MACH_COP_0_LLADDR	$17
-#define MACH_COP_0_WATCH_LO	$18
-#define MACH_COP_0_WATCH_HI	$19
-#define MACH_COP_0_TLB_XCONTEXT	$20
-#define MACH_COP_0_ECC		$26
-#define MACH_COP_0_CACHE_ERR	$27
-#define MACH_COP_0_TAG_LO	$28
-#define MACH_COP_0_TAG_HI	$29
-#define MACH_COP_0_ERROR_PC	$30
+#define MIPS_COP_0_CONFIG	$16
+#define MIPS_COP_0_LLADDR	$17
+#define MIPS_COP_0_WATCH_LO	$18
+#define MIPS_COP_0_WATCH_HI	$19
+#define MIPS_COP_0_TLB_XCONTEXT	$20
+#define MIPS_COP_0_ECC		$26
+#define MIPS_COP_0_CACHE_ERR	$27
+#define MIPS_COP_0_TAG_LO	$28
+#define MIPS_COP_0_TAG_HI	$29
+#define MIPS_COP_0_ERROR_PC	$30
 
 
 
 /*
  * Values for the code field in a break instruction.
  */
-#define MACH_BREAK_INSTR	0x0000000d
-#define MACH_BREAK_VAL_MASK	0x03ff0000
-#define MACH_BREAK_VAL_SHIFT	16
-#define MACH_BREAK_KDB_VAL	512
-#define MACH_BREAK_SSTEP_VAL	513
-#define MACH_BREAK_BRKPT_VAL	514
-#define MACH_BREAK_SOVER_VAL	515
-#define MACH_BREAK_KDB		(MACH_BREAK_INSTR | \
-				(MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT))
-#define MACH_BREAK_SSTEP	(MACH_BREAK_INSTR | \
-				(MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT))
-#define MACH_BREAK_BRKPT	(MACH_BREAK_INSTR | \
-				(MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT))
-#define MACH_BREAK_SOVER	(MACH_BREAK_INSTR | \
-				(MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_INSTR	0x0000000d
+#define MIPS_BREAK_VAL_MASK	0x03ff0000
+#define MIPS_BREAK_VAL_SHIFT	16
+#define MIPS_BREAK_KDB_VAL	512
+#define MIPS_BREAK_SSTEP_VAL	513
+#define MIPS_BREAK_BRKPT_VAL	514
+#define MIPS_BREAK_SOVER_VAL	515
+#define MIPS_BREAK_KDB		(MIPS_BREAK_INSTR | \
+				(MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_SSTEP	(MIPS_BREAK_INSTR | \
+				(MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_BRKPT	(MIPS_BREAK_INSTR | \
+				(MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
+#define MIPS_BREAK_SOVER	(MIPS_BREAK_INSTR | \
+				(MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
 
 /*
  * Mininum and maximum cache sizes.
  */
-#define MACH_MIN_CACHE_SIZE	(16 * 1024)
-#define MACH_MAX_CACHE_SIZE	(256 * 1024)
+#define MIPS_MIN_CACHE_SIZE	(16 * 1024)
+#define MIPS_MAX_CACHE_SIZE	(256 * 1024)
 
 /*
  * The floating point version and status registers.
  */
-#define	MACH_FPC_ID	$0
-#define	MACH_FPC_CSR	$31
+#define	MIPS_FPU_ID	$0
+#define	MIPS_FPU_CSR	$31
 
 /*
  * The floating point coprocessor status register bits.
  */
-#define MACH_FPC_ROUNDING_BITS		0x00000003
-#define MACH_FPC_ROUND_RN		0x00000000
-#define MACH_FPC_ROUND_RZ		0x00000001
-#define MACH_FPC_ROUND_RP		0x00000002
-#define MACH_FPC_ROUND_RM		0x00000003
-#define MACH_FPC_STICKY_BITS		0x0000007c
-#define MACH_FPC_STICKY_INEXACT		0x00000004
-#define MACH_FPC_STICKY_UNDERFLOW	0x00000008
-#define MACH_FPC_STICKY_OVERFLOW	0x00000010
-#define MACH_FPC_STICKY_DIV0		0x00000020
-#define MACH_FPC_STICKY_INVALID		0x00000040
-#define MACH_FPC_ENABLE_BITS		0x00000f80
-#define MACH_FPC_ENABLE_INEXACT		0x00000080
-#define MACH_FPC_ENABLE_UNDERFLOW	0x00000100
-#define MACH_FPC_ENABLE_OVERFLOW	0x00000200
-#define MACH_FPC_ENABLE_DIV0		0x00000400
-#define MACH_FPC_ENABLE_INVALID		0x00000800
-#define MACH_FPC_EXCEPTION_BITS		0x0003f000
-#define MACH_FPC_EXCEPTION_INEXACT	0x00001000
-#define MACH_FPC_EXCEPTION_UNDERFLOW	0x00002000
-#define MACH_FPC_EXCEPTION_OVERFLOW	0x00004000
-#define MACH_FPC_EXCEPTION_DIV0		0x00008000
-#define MACH_FPC_EXCEPTION_INVALID	0x00010000
-#define MACH_FPC_EXCEPTION_UNIMPL	0x00020000
-#define MACH_FPC_COND_BIT		0x00800000
-#define MACH_FPC_FLUSH_BIT		0x01000000	/* r4k,  MBZ on r3k */
-#define MIPS_3K_FPC_MBZ_BITS		0xff7c0000
-#define MIPS_4K_FPC_MBZ_BITS		0xfe7c0000
+#define MIPS_FPU_ROUNDING_BITS		0x00000003
+#define MIPS_FPU_ROUND_RN		0x00000000
+#define MIPS_FPU_ROUND_RZ		0x00000001
+#define MIPS_FPU_ROUND_RP		0x00000002
+#define MIPS_FPU_ROUND_RM		0x00000003
+#define MIPS_FPU_STICKY_BITS		0x0000007c
+#define MIPS_FPU_STICKY_INEXACT		0x00000004
+#define MIPS_FPU_STICKY_UNDERFLOW	0x00000008
+#define MIPS_FPU_STICKY_OVERFLOW	0x00000010
+#define MIPS_FPU_STICKY_DIV0		0x00000020
+#define MIPS_FPU_STICKY_INVALID		0x00000040
+#define MIPS_FPU_ENABLE_BITS		0x00000f80
+#define MIPS_FPU_ENABLE_INEXACT		0x00000080
+#define MIPS_FPU_ENABLE_UNDERFLOW	0x00000100
+#define MIPS_FPU_ENABLE_OVERFLOW	0x00000200
+#define MIPS_FPU_ENABLE_DIV0		0x00000400
+#define MIPS_FPU_ENABLE_INVALID		0x00000800
+#define MIPS_FPU_EXCEPTION_BITS		0x0003f000
+#define MIPS_FPU_EXCEPTION_INEXACT	0x00001000
+#define MIPS_FPU_EXCEPTION_UNDERFLOW	0x00002000
+#define MIPS_FPU_EXCEPTION_OVERFLOW	0x00004000
+#define MIPS_FPU_EXCEPTION_DIV0		0x00008000
+#define MIPS_FPU_EXCEPTION_INVALID	0x00010000
+#define MIPS_FPU_EXCEPTION_UNIMPL	0x00020000
+#define MIPS_FPU_COND_BIT		0x00800000
+#define MIPS_FPU_FLUSH_BIT		0x01000000	/* r4k,  MBZ on r3k */
+#define MIPS1_FPC_MBZ_BITS		0xff7c0000
+#define MIPS3_FPC_MBZ_BITS		0xfe7c0000
 
 
 /*
  * Constants to determine if have a floating point instruction.
  */
-#define MACH_OPCODE_SHIFT	26
-#define MACH_OPCODE_C1		0x11
+#define MIPS_OPCODE_SHIFT	26
+#define MIPS_OPCODE_C1		0x11
 
 
 
 /*
  * The low part of the TLB entry.
  */
-#define VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT	12
-#define VMMACH_MIPS_3K_TLB_PF_NUM		0xfffff000
-#define VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT	0x00000800
-#define VMMACH_MIPS_3K_TLB_MOD_BIT		0x00000400
-#define VMMACH_MIPS_3K_TLB_VALID_BIT		0x00000200
-#define VMMACH_MIPS_3K_TLB_GLOBAL_BIT		0x00000100
-
-#define VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT	6
-#define VMMACH_MIPS_4K_TLB_PF_NUM		0x3fffffc0
-#define VMMACH_MIPS_4K_TLB_ATTR_MASK		0x00000038
-#define VMMACH_MIPS_4K_TLB_MOD_BIT		0x00000004
-#define VMMACH_MIPS_4K_TLB_VALID_BIT		0x00000002
-#define VMMACH_MIPS_4K_TLB_GLOBAL_BIT		0x00000001
-
-
-#ifdef pmax /* XXX */
-#define VMMACH_TLB_PHYS_PAGE_SHIFT	VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT
-#define VMMACH_TLB_PF_NUM		VMMACH_MIPS_3K_TLB_PF_NUM
-#define VMMACH_TLB_NON_CACHEABLE_BIT	VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT
-#define VMMACH_TLB_MOD_BIT		VMMACH_MIPS_3K_TLB_MOD_BIT
-#define VMMACH_TLB_VALID_BIT		VMMACH_MIPS_3K_TLB_VALID_BIT
-#define VMMACH_TLB_GLOBAL_BIT		VMMACH_MIPS_3K_TLB_GLOBAL_BIT
-#endif /* pmax */
-
-#ifdef pica /*  XXX */
-#define VMMACH_TLB_PHYS_PAGE_SHIFT	VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT
-#define VMMACH_TLB_PF_NUM		VMMACH_MIPS_4K_TLB_PF_NUM
-#define VMMACH_TLB_ATTR_MASK		VMMACH_MIPS_4K_TLB_ATTR_MASK
-#define VMMACH_TLB_MOD_BIT		VMMACH_MIPS_4K_TLB_MOD_BIT
-#define VMMACH_TLB_VALID_BIT		VMMACH_MIPS_4K_TLB_VALID_BIT
-#define VMMACH_TLB_GLOBAL_BIT		VMMACH_MIPS_4K_TLB_GLOBAL_BIT
-#endif	/* pica */
+#define MIPS1_TLB_PHYS_PAGE_SHIFT	12
+#define MIPS1_TLB_PF_NUM		0xfffff000
+#define MIPS1_TLB_NON_CACHEABLE_BIT	0x00000800
+#define MIPS1_TLB_MOD_BIT		0x00000400
+#define MIPS1_TLB_VALID_BIT		0x00000200
+#define MIPS1_TLB_GLOBAL_BIT		0x00000100
 
+#define MIPS3_TLB_PHYS_PAGE_SHIFT	6
+#define MIPS3_TLB_PF_NUM		0x3fffffc0
+#define MIPS3_TLB_ATTR_MASK		0x00000038
+#define MIPS3_TLB_MOD_BIT		0x00000004
+#define MIPS3_TLB_VALID_BIT		0x00000002
+#define MIPS3_TLB_GLOBAL_BIT		0x00000001
 
 
 /*
  * The high part of the TLB entry.
  */
-#define VMMACH_TLB_VIRT_PAGE_SHIFT		12
+#define MIPS_TLB_VIRT_PAGE_SHIFT	12
 
-#define VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM	0xfffff000
-#define VMMACH_TLB_MIPS_3K_PID			0x00000fc0
-#define VMMACH_TLB_MIPS_3K_PID_SHIFT		6
+#define MIPS1_TLB_VIRT_PAGE_NUM		0xfffff000
+#define MIPS1_TLB_PID			0x00000fc0
+#define MIPS1_TLB_PID_SHIFT		6
 
-#define VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM	0xffffe000
-#define VMMACH_TLB_MIPS_4K_PID			0x000000ff
-#define VMMACH_TLB_MIPS_4K_PID_SHIFT		0
+#define MIPS3_TLB_VIRT_PAGE_NUM		0xffffe000
+#define MIPS3_TLB_PID			0x000000ff
+#define MIPS3_TLB_PID_SHIFT		0
 
-/* XXX needs more thought */
-/*
- * backwards XXX needs more thought, should support runtime decisions.
- */
-
-#ifdef pmax
-#define VMMACH_TLB_VIRT_PAGE_NUM	VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM
-#define VMMACH_TLB_PID			VMMACH_TLB_MIPS_3K_PID      
-#define VMMACH_TLB_PID_SHIFT		VMMACH_TLB_MIPS_3K_PID_SHIFT
-#endif
-
-#ifdef pica
-#define VMMACH_TLB_VIRT_PAGE_NUM	VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM
-#define VMMACH_TLB_PID			VMMACH_TLB_MIPS_4K_PID      
-#define VMMACH_TLB_PID_SHIFT		VMMACH_TLB_MIPS_4K_PID_SHIFT
-#endif
 
 /*
  * r3000: shift count to put the index in the right spot.
  * (zero on r4000?) 
  */
-#define VMMACH_TLB_INDEX_SHIFT		8
+#define MIPS1_TLB_INDEX_SHIFT		8
 
 
 /*
  * The number of TLB entries and the first one that write random hits.
  */
-#define VMMACH_MIPS_3K_NUM_TLB_ENTRIES	64
-#define VMMACH_MIPS_3K_FIRST_RAND_ENTRY	8
+#define MIPS1_TLB_NUM_TLB_ENTRIES	64
+#define MIPS1_TLB_FIRST_RAND_ENTRY	8
 
-#define VMMACH_MIPS_4K_NUM_TLB_ENTRIES	48
-#define VMMACH_MIPS_4K_WIRED_ENTRIES	8
-
-/* compatibility with existing locore -- XXX more thought */
-#ifdef pmax
-#define VMMACH_NUM_TLB_ENTRIES		VMMACH_MIPS_3K_NUM_TLB_ENTRIES
-#define VMMACH_FIRST_RAND_ENTRY 	VMMACH_MIPS_3K_FIRST_RAND_ENTRY
-#endif	/* pmax */
-
-#ifdef pica
-#define VMMACH_NUM_TLB_ENTRIES		VMMACH_MIPS_4K_NUM_TLB_ENTRIES
-#define VMMACH_WIRED_ENTRIES	 	VMMACH_MIPS_4K_WIRED_ENTRIES
-#endif	/* pica */
+#define MIPS3_TLB_NUM_TLB_ENTRIES	48
+#define MIPS3_TLB_WIRED_ENTRIES		8
 
 
 /*
  * The number of process id entries.
  */
-#define	VMMACH_MIPS_3K_NUM_PIDS			64
-#define	VMMACH_MIPS_4K_NUM_PIDS			256
+#define	MIPS1_TLB_NUM_PIDS		64
+#define	MIPS3_TLB_NUM_PIDS		256
+
+/*
+ * backwards compatibility with existing locore and compile-time
+ * mips1/mips3 binding. 
+ *
+ * XXX INT_MASK and HARD_INT_MASK are here only because we dont
+ * support the mips3 on-chip timer which is tied to INT_5.
+ */
+
+#if defined(MIPS3) && !defined(MIPS1)
+#define MIPS_TLB_PID_SHIFT		MIPS3_TLB_PID_SHIFT
+#define	MIPS_TLB_NUM_PIDS		MIPS3_TLB_NUM_PIDS
+#endif
+
+#if !defined(MIPS3) && defined(MIPS1)
+#define MIPS_TLB_PID_SHIFT		MIPS1_TLB_PID_SHIFT
+#define	MIPS_TLB_NUM_PIDS		MIPS1_TLB_NUM_PIDS
+#endif
 
-#ifdef pmax
-#define	VMMACH_NUM_PIDS		VMMACH_MIPS_3K_NUM_PIDS
-#endif	/* pmax */
-#ifdef pica
-#define	VMMACH_NUM_PIDS		VMMACH_MIPS_4K_NUM_PIDS
-#endif	/* pica */
 
+#if defined(MIPS1) && defined(MIPS3)
+#define MIPS_TLB_PID_SHIFT \
+    ((CPUISMIPS3)? MIPS3_TLB_PID_SHIFT : MIPS1_TLB_PID_SHIFT)
+
+#define MIPS_TLB_NUM_PIDS \
+    ((CPUISMIPS3)? MIPS3_TLB_NUM_PIDS : MIPS1_TLB_NUM_PIDS)
+
+#endif
 
 /*
  * TLB probe return codes.
  */
-#define VMMACH_TLB_NOT_FOUND		0
-#define VMMACH_TLB_FOUND		1
-#define VMMACH_TLB_FOUND_WITH_PATCH	2
-#define VMMACH_TLB_PROBE_ERROR		3
+#define MIPS_TLB_NOT_FOUND		0
+#define MIPS_TLB_FOUND		1
+#define MIPS_TLB_FOUND_WITH_PATCH	2
+#define MIPS_TLB_PROBE_ERROR		3
 
-/* TTTTT - stuff from NetBSD mips cpuregs.h */
-/*
- * nesting interrupt masks.
- */
-#define MACH_INT_MASK_SPL_SOFT0	MACH_SOFT_INT_MASK_0
-#define MACH_INT_MASK_SPL_SOFT1	(MACH_SOFT_INT_MASK_1|MACH_INT_MASK_SPL_SOFT0)
-#define MACH_INT_MASK_SPL0	(MACH_INT_MASK_0|MACH_INT_MASK_SPL_SOFT1)
-#define MACH_INT_MASK_SPL1	(MACH_INT_MASK_1|MACH_INT_MASK_SPL0)
-#define MACH_INT_MASK_SPL2	(MACH_INT_MASK_2|MACH_INT_MASK_SPL1)
-#define MACH_INT_MASK_SPL3	(MACH_INT_MASK_3|MACH_INT_MASK_SPL2)
-#define MACH_INT_MASK_SPL4	(MACH_INT_MASK_4|MACH_INT_MASK_SPL3)
-#define MACH_INT_MASK_SPL5	(MACH_INT_MASK_5|MACH_INT_MASK_SPL4)
-/* TTTTT - end of stuff from NetBSD mips cpuregs.h */
-
-#endif /* _MACHCONST */
+#endif /* _PMAX_CPUREGS_H_ */
diff --git a/sys/arch/pmax/include/kdbparam.h b/sys/arch/pmax/include/kdbparam.h
index 9104c87aa3c..0bf7220b606 100644
--- a/sys/arch/pmax/include/kdbparam.h
+++ b/sys/arch/pmax/include/kdbparam.h
@@ -52,13 +52,13 @@
 #define LPRMODE		"%R"
 #define OFFMODE		"+%R"
 
-#define	SETBP(ins)	MACH_BREAK_BRKPT
+#define	SETBP(ins)	MIPS_BREAK_BRKPT
 
 /* return the program counter value modified if we are in a delay slot */
 #define	kdbgetpc(pcb)		(kdbvar[kdbvarchk('t')] < 0 ? \
 	(pcb).pcb_regs[34] + 4 : (pcb).pcb_regs[34])
 #define	kdbishiddenreg(p)	((p) >= &kdbreglist[33])
-#define	kdbisbreak(type)	(((type) & MACH_CR_EXC_CODE) == 0x24)
+#define	kdbisbreak(type)	(((type) & MIPS_CR_EXC_CODE) == 0x24)
 
 /* check for address wrap around */
 #define	kdbaddrwrap(addr,newaddr)	(((addr)^(newaddr)) >> 31)
diff --git a/sys/arch/pmax/include/psl.h b/sys/arch/pmax/include/psl.h
index d67c78239bb..cc349db4d61 100644
--- a/sys/arch/pmax/include/psl.h
+++ b/sys/arch/pmax/include/psl.h
@@ -40,31 +40,31 @@
 
 #include <machine/machConst.h>
 
-#define	PSL_LOWIPL	(MACH_INT_MASK | MACH_SR_INT_ENA_CUR)
+#define	PSL_LOWIPL	(MIPS_INT_MASK | MIPS_SR_INT_ENA_CUR)
 
 #define	PSL_USERSET (	\
-	MACH_SR_KU_OLD |	\
-	MACH_SR_INT_ENA_OLD |	\
-	MACH_SR_KU_PREV |	\
-	MACH_SR_INT_ENA_PREV |	\
-	MACH_INT_MASK)
+	MIPS_SR_KU_OLD |	\
+	MIPS_SR_INT_ENA_OLD |	\
+	MIPS_SR_KU_PREV |	\
+	MIPS_SR_INT_ENA_PREV |	\
+	MIPS_INT_MASK)
 
 #define	PSL_USERCLR (	\
-	MACH_SR_COP_USABILITY |	\
-	MACH_SR_BOOT_EXC_VEC |	\
-	MACH_SR_TLB_SHUTDOWN |	\
-	MACH_SR_PARITY_ERR |	\
-	MACH_SR_CACHE_MISS |	\
-	MACH_SR_PARITY_ZERO |	\
-	MACH_SR_SWAP_CACHES |	\
-	MACH_SR_ISOL_CACHES |	\
-	MACH_SR_KU_CUR |	\
-	MACH_SR_INT_ENA_CUR |	\
-	MACH_SR_MBZ)
+	MIPS_SR_COP_USABILITY |	\
+	MIPS_SR_BOOT_EXC_VEC |	\
+	MIPS_SR_TLB_SHUTDOWN |	\
+	MIPS_SR_PARITY_ERR |	\
+	MIPS_SR_CACHE_MISS |	\
+	MIPS_SR_PARITY_ZERO |	\
+	MIPS_SR_SWAP_CACHES |	\
+	MIPS_SR_ISOL_CACHES |	\
+	MIPS_SR_KU_CUR |	\
+	MIPS_SR_INT_ENA_CUR |	\
+	MIPS_SR_MBZ)
 
 /*
  * Macros to decode processor status word.
  */
-#define	USERMODE(ps)	((ps) & MACH_SR_KU_PREV)
-#define	BASEPRI(ps)	(((ps) & (MACH_INT_MASK | MACH_SR_INT_ENA_PREV)) \
-			== (MACH_INT_MASK | MACH_SR_INT_ENA_PREV))
+#define	USERMODE(ps)	((ps) & MIPS_SR_KU_PREV)
+#define	BASEPRI(ps)	(((ps) & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) \
+			== (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV))
diff --git a/sys/arch/pmax/include/tc_machdep.h b/sys/arch/pmax/include/tc_machdep.h
index 40a31833858..1bcac7d8518 100644
--- a/sys/arch/pmax/include/tc_machdep.h
+++ b/sys/arch/pmax/include/tc_machdep.h
@@ -60,7 +60,7 @@
 #ifndef __MACHINE_TC_MACHDEP_H__
 #define __MACHINE_TC_MACHDEP_H__
 
-#include <machine/cpuregs.h>		/* defines MACH_PHYS_TO_UNCACHED */
+#include <machine/cpuregs.h>		/* defines MIPS_PHYS_TO_KSEG1 */
 
 typedef int32_t		tc_addr_t;
 typedef int32_t		tc_offset_t;
@@ -78,7 +78,7 @@ typedef int32_t		tc_offset_t;
 
 #define	TC_DENSE_TO_SPARSE(addr)  (addr)
 		
-#define	TC_PHYS_TO_UNCACHED(addr) MACH_PHYS_TO_UNCACHED(addr)
+#define	TC_PHYS_TO_UNCACHED(addr) MIPS_PHYS_TO_KSEG1(addr)
 
 
 /*
diff --git a/sys/arch/pmax/pmax/clock.c b/sys/arch/pmax/pmax/clock.c
index a6d15e9b4d8..0031c8fa729 100644
--- a/sys/arch/pmax/pmax/clock.c
+++ b/sys/arch/pmax/pmax/clock.c
@@ -234,11 +234,11 @@ clockattach(parent, self, aux)
 #if NTC>0
 	if (parent->dv_cfdata->cf_driver != &mainbus_cd)
 		Mach_clock_addr = (struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(d->iada_addr);
+			MIPS_PHYS_TO_KSEG1(d->iada_addr);
 	else
 #endif
 		Mach_clock_addr = (struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(ca->ca_addr);
+			MIPS_PHYS_TO_KSEG1(ca->ca_addr);
 
 #ifdef pmax
 	printf("\n");
diff --git a/sys/arch/pmax/pmax/fp.S b/sys/arch/pmax/pmax/fp.S
index c0590efa1e8..81a5ed0ac29 100644
--- a/sys/arch/pmax/pmax/fp.S
+++ b/sys/arch/pmax/pmax/fp.S
@@ -110,10 +110,10 @@ NON_LEAF(MachEmulateFP, STAND_FRAME_SIZE, ra)
 	bgt	v0, 4 << 2, ill			# illegal format
 
 	or	v1, v1, v0
-	cfc1	a1, MACH_FPC_CSR		# get exception register
+	cfc1	a1, MIPS_FPU_CSR		# get exception register
 	lw	a3, func_fmt_tbl(v1)		# switch on FUNC & FMT
-	and	a1, a1, ~MACH_FPC_EXCEPTION_UNIMPL	# clear exception
-	ctc1	a1, MACH_FPC_CSR
+	and	a1, a1, ~MIPS_FPU_EXCEPTION_UNIMPL	# clear exception
+	ctc1	a1, MIPS_FPU_CSR
 	j	a3
 
 	.rdata
@@ -668,8 +668,8 @@ add_sub_s:
 3:
 	bne	t5, zero, result_ft_s		# if FT != 0, result=FT
 	bne	t6, zero, result_ft_s
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	bne	v0, MACH_FPC_ROUND_RM, 1f	# round to -infinity?
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	bne	v0, MIPS_FPU_ROUND_RM, 1f	# round to -infinity?
 	or	t0, t0, t4			# compute result sign
 	b	result_fs_s
 1:
@@ -727,8 +727,8 @@ add_sub_s:
 	bne	t2, t6, 2f			# if same, result=0
 	move	t1, zero			# result=0
 	move	t2, zero
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	bne	v0, MACH_FPC_ROUND_RM, 1f	# round to -infinity?
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	bne	v0, MIPS_FPU_ROUND_RM, 1f	# round to -infinity?
 	or	t0, t0, t4			# compute result sign
 	b	result_fs_s
 1:
@@ -791,8 +791,8 @@ add_sub_d:
 	bne	t5, zero, result_ft_d		# if FT != 0, result=FT
 	bne	t6, zero, result_ft_d
 	bne	t7, zero, result_ft_d
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	bne	v0, MACH_FPC_ROUND_RM, 1f	# round to -infinity?
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	bne	v0, MIPS_FPU_ROUND_RM, 1f	# round to -infinity?
 	or	t0, t0, t4			# compute result sign
 	b	result_fs_d
 1:
@@ -885,8 +885,8 @@ add_sub_d:
 	move	t1, zero			# result=0
 	move	t2, zero
 	move	t3, zero
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	bne	v0, MACH_FPC_ROUND_RM, 1f	# round to -infinity?
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	bne	v0, MIPS_FPU_ROUND_RM, 1f	# round to -infinity?
 	or	t0, t0, t4			# compute result sign
 	b	result_fs_d
 1:
@@ -1081,10 +1081,10 @@ div_s:
 3:
 	bne	t5, zero, 2f			# is FT zero?
 	bne	t6, zero, 1f
-	or	a1, a1, MACH_FPC_EXCEPTION_DIV0 | MACH_FPC_STICKY_DIV0
-	and	v0, a1, MACH_FPC_ENABLE_DIV0	# trap enabled?
+	or	a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
+	and	v0, a1, MIPS_FPU_ENABLE_DIV0	# trap enabled?
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	li	t1, SEXP_INF			# result is infinity
 	move	t2, zero
 	b	result_fs_s
@@ -1155,10 +1155,10 @@ div_d:
 	bne	t5, zero, 2f			# is FT zero?
 	bne	t6, zero, 1f
 	bne	t7, zero, 1f
-	or	a1, a1, MACH_FPC_EXCEPTION_DIV0 | MACH_FPC_STICKY_DIV0
-	and	v0, a1, MACH_FPC_ENABLE_DIV0	# trap enabled?
+	or	a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
+	and	v0, a1, MIPS_FPU_ENABLE_DIV0	# trap enabled?
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# Save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# Save exceptions
 	li	t1, DEXP_INF			# result is infinity
 	move	t2, zero
 	move	t3, zero
@@ -1507,10 +1507,10 @@ cvt_w:
  * round result (t0 is sign, t2 is integer part, t3 is fractional part).
  */
 2:
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, 3f	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, 5f	# round to zero (truncate)
-	beq	v0, MACH_FPC_ROUND_RP, 1f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, 3f	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, 5f	# round to zero (truncate)
+	beq	v0, MIPS_FPU_ROUND_RP, 1f	# round to +infinity
 	beq	t0, zero, 5f			# if sign is positive, truncate
 	b	2f
 1:
@@ -1539,10 +1539,10 @@ cvt_w:
  * Handle inexact exception.
  */
 inexact_w:
-	or	a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
-	and	v0, a1, MACH_FPC_ENABLE_INEXACT
+	or	a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+	and	v0, a1, MIPS_FPU_ENABLE_INEXACT
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	b	result_fs_w
 
 /*
@@ -1551,10 +1551,10 @@ inexact_w:
  * or generate an invalid exception.
  */
 overflow_w:
-	or	a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW
-	and	v0, a1, MACH_FPC_ENABLE_OVERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
+	and	v0, a1, MIPS_FPU_ENABLE_OVERFLOW
 	bne	v0, zero, fpe_trap
-	and	v0, a1, MACH_FPC_ENABLE_INEXACT
+	and	v0, a1, MIPS_FPU_ENABLE_INEXACT
 	bne	v0, zero, inexact_w		# inexact traps enabled?
 	b	invalid_w
 
@@ -1564,10 +1564,10 @@ overflow_w:
  * or generate an invalid exception.
  */
 underflow_w:
-	or	a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
-	and	v0, a1, MACH_FPC_ENABLE_UNDERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+	and	v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
 	bne	v0, zero, fpe_trap
-	and	v0, a1, MACH_FPC_ENABLE_INEXACT
+	and	v0, a1, MIPS_FPU_ENABLE_INEXACT
 	bne	v0, zero, inexact_w		# inexact traps enabled?
 	b	invalid_w
 
@@ -1643,29 +1643,29 @@ test_cond:
 	and	v0, v0, a0			# condition match instruction?
 set_cond:
 	bne	v0, zero, 1f
-	and	a1, a1, ~MACH_FPC_COND_BIT	# clear condition bit
+	and	a1, a1, ~MIPS_FPU_COND_BIT	# clear condition bit
 	b	2f
 1:
-	or	a1, a1, MACH_FPC_COND_BIT	# set condition bit
+	or	a1, a1, MIPS_FPU_COND_BIT	# set condition bit
 2:
-	ctc1	a1, MACH_FPC_CSR		# save condition bit
+	ctc1	a1, MIPS_FPU_CSR		# save condition bit
 	b	done
 
 unordered:
 	and	v0, a0, COND_UNORDERED		# this cmp match unordered?
 	bne	v0, zero, 1f
-	and	a1, a1, ~MACH_FPC_COND_BIT	# clear condition bit
+	and	a1, a1, ~MIPS_FPU_COND_BIT	# clear condition bit
 	b	2f
 1:
-	or	a1, a1, MACH_FPC_COND_BIT	# set condition bit
+	or	a1, a1, MIPS_FPU_COND_BIT	# set condition bit
 2:
 	and	v0, a0, COND_SIGNAL
 	beq	v0, zero, 1f			# is this a signaling cmp?
-	or	a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
-	and	v0, a1, MACH_FPC_ENABLE_INVALID
+	or	a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+	and	v0, a1, MIPS_FPU_ENABLE_INVALID
 	bne	v0, zero, fpe_trap
 1:
-	ctc1	a1, MACH_FPC_CSR		# save condition bit
+	ctc1	a1, MIPS_FPU_CSR		# save condition bit
 	b	done
 
 /*
@@ -1730,10 +1730,10 @@ norm_s:
 norm_noshift_s:
 	move	t5, t1				# save unrounded exponent
 	move	t6, t2				# save unrounded fraction
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, 3f	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, 5f	# round to zero (truncate)
-	beq	v0, MACH_FPC_ROUND_RP, 1f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, 3f	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, 5f	# round to zero (truncate)
+	beq	v0, MIPS_FPU_ROUND_RP, 1f	# round to +infinity
 	beq	t0, zero, 5f			# if sign is positive, truncate
 	b	2f
 1:
@@ -1773,10 +1773,10 @@ inexact_s:
 	and	t2, t2, ~SIMPL_ONE		# clear implied one bit
 inexact_nobias_s:
 	jal	_C_LABEL(set_fd_s)		# save result
-	or	a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
-	and	v0, a1, MACH_FPC_ENABLE_INEXACT
+	or	a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+	and	v0, a1, MIPS_FPU_ENABLE_INEXACT
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	b	done
 
 /*
@@ -1785,18 +1785,18 @@ inexact_nobias_s:
  * or generate an infinity.
  */
 overflow_s:
-	or	a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW
-	and	v0, a1, MACH_FPC_ENABLE_OVERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
+	and	v0, a1, MIPS_FPU_ENABLE_OVERFLOW
 	beq	v0, zero, 1f
 	subu	t1, t1, 192			# bias exponent
 	and	t2, t2, ~SIMPL_ONE		# clear implied one bit
 	jal	_C_LABEL(set_fd_s)		# save result
 	b	fpe_trap
 1:
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, 3f	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, 1f	# round to zero (truncate)
-	beq	v0, MACH_FPC_ROUND_RP, 2f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, 3f	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, 1f	# round to zero (truncate)
+	beq	v0, MIPS_FPU_ROUND_RP, 2f	# round to +infinity
 	bne	t0, zero, 3f
 1:
 	li	t1, SEXP_MAX			# result is max finite
@@ -1814,7 +1814,7 @@ overflow_s:
  * "loss of accuracy" is detected as "an inexact result".
  */
 underflow_s:
-	and	v0, a1, MACH_FPC_ENABLE_UNDERFLOW
+	and	v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
 	beq	v0, zero, 1f
 /*
  * Underflow is enabled so compute the result and trap.
@@ -1822,7 +1822,7 @@ underflow_s:
 	addu	t1, t1, 192			# bias exponent
 	and	t2, t2, ~SIMPL_ONE		# clear implied one bit
 	jal	_C_LABEL(set_fd_s)		# save result
-	or	a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
 	b	fpe_trap
 /*
  * Underflow is not enabled so compute the result,
@@ -1836,15 +1836,15 @@ underflow_s:
 	blt	t9, SFRAC_BITS+2, 3f		# shift all the bits out?
 	move	t1, zero			# result is inexact zero
 	move	t2, zero
-	or	a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
 /*
  * Now round the zero result.
  * Only need to worry about rounding to +- infinity when the sign matches.
  */
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, inexact_nobias_s	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, inexact_nobias_s	# round to zero
-	beq	v0, MACH_FPC_ROUND_RP, 1f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, inexact_nobias_s	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, inexact_nobias_s	# round to zero
+	beq	v0, MIPS_FPU_ROUND_RP, 1f	# round to +infinity
 	beq	t0, zero, inexact_nobias_s	# if sign is positive, truncate
 	b	2f
 1:
@@ -1862,10 +1862,10 @@ underflow_s:
 /*
  * Now round the denormalized result.
  */
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, 3f	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, 5f	# round to zero (truncate)
-	beq	v0, MACH_FPC_ROUND_RP, 1f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, 3f	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, 5f	# round to zero (truncate)
+	beq	v0, MIPS_FPU_ROUND_RP, 1f	# round to +infinity
 	beq	t0, zero, 5f			# if sign is positive, truncate
 	b	2f
 1:
@@ -1887,11 +1887,11 @@ underflow_s:
 	move	t1, zero			# denorm or zero exponent
 	jal	_C_LABEL(set_fd_s)		# save result
 	beq	t8, zero, done			# check for exact result
-	or	a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
-	or	a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
-	and	v0, a1, MACH_FPC_ENABLE_INEXACT
+	or	a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+	and	v0, a1, MIPS_FPU_ENABLE_INEXACT
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	b	done
 
 /*
@@ -1976,10 +1976,10 @@ norm_noshift_d:
 	move	t5, t1				# save unrounded exponent
 	move	t6, t2				# save unrounded fraction (MS)
 	move	t7, t3				# save unrounded fraction (LS)
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, 3f	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, 5f	# round to zero (truncate)
-	beq	v0, MACH_FPC_ROUND_RP, 1f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, 3f	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, 5f	# round to zero (truncate)
+	beq	v0, MIPS_FPU_ROUND_RP, 1f	# round to +infinity
 	beq	t0, zero, 5f			# if sign is positive, truncate
 	b	2f
 1:
@@ -2023,10 +2023,10 @@ inexact_d:
 	and	t2, t2, ~DIMPL_ONE		# clear implied one bit
 inexact_nobias_d:
 	jal	_C_LABEL(set_fd_d)		# save result
-	or	a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
-	and	v0, a1, MACH_FPC_ENABLE_INEXACT
+	or	a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+	and	v0, a1, MIPS_FPU_ENABLE_INEXACT
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	b	done
 
 /*
@@ -2035,18 +2035,18 @@ inexact_nobias_d:
  * or generate an infinity.
  */
 overflow_d:
-	or	a1, a1, MACH_FPC_EXCEPTION_OVERFLOW | MACH_FPC_STICKY_OVERFLOW
-	and	v0, a1, MACH_FPC_ENABLE_OVERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
+	and	v0, a1, MIPS_FPU_ENABLE_OVERFLOW
 	beq	v0, zero, 1f
 	subu	t1, t1, 1536			# bias exponent
 	and	t2, t2, ~DIMPL_ONE		# clear implied one bit
 	jal	_C_LABEL(set_fd_d)		# save result
 	b	fpe_trap
 1:
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, 3f	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, 1f	# round to zero (truncate)
-	beq	v0, MACH_FPC_ROUND_RP, 2f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, 3f	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, 1f	# round to zero (truncate)
+	beq	v0, MIPS_FPU_ROUND_RP, 2f	# round to +infinity
 	bne	t0, zero, 3f
 1:
 	li	t1, DEXP_MAX			# result is max finite
@@ -2066,7 +2066,7 @@ overflow_d:
  * "loss of accuracy" is detected as "an inexact result".
  */
 underflow_d:
-	and	v0, a1, MACH_FPC_ENABLE_UNDERFLOW
+	and	v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
 	beq	v0, zero, 1f
 /*
  * Underflow is enabled so compute the result and trap.
@@ -2074,7 +2074,7 @@ underflow_d:
 	addu	t1, t1, 1536			# bias exponent
 	and	t2, t2, ~DIMPL_ONE		# clear implied one bit
 	jal	_C_LABEL(set_fd_d)		# save result
-	or	a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
 	b	fpe_trap
 /*
  * Underflow is not enabled so compute the result,
@@ -2090,15 +2090,15 @@ underflow_d:
 	move	t1, zero			# result is inexact zero
 	move	t2, zero
 	move	t3, zero
-	or	a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
 /*
  * Now round the zero result.
  * Only need to worry about rounding to +- infinity when the sign matches.
  */
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, inexact_nobias_d	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, inexact_nobias_d	# round to zero
-	beq	v0, MACH_FPC_ROUND_RP, 1f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, inexact_nobias_d	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, inexact_nobias_d	# round to zero
+	beq	v0, MIPS_FPU_ROUND_RP, 1f	# round to +infinity
 	beq	t0, zero, inexact_nobias_d	# if sign is positive, truncate
 	b	2f
 1:
@@ -2130,10 +2130,10 @@ underflow_d:
  * Now round the denormalized result.
  */
 2:
-	and	v0, a1, MACH_FPC_ROUNDING_BITS	# get rounding mode
-	beq	v0, MACH_FPC_ROUND_RN, 3f	# round to nearest
-	beq	v0, MACH_FPC_ROUND_RZ, 5f	# round to zero (truncate)
-	beq	v0, MACH_FPC_ROUND_RP, 1f	# round to +infinity
+	and	v0, a1, MIPS_FPU_ROUNDING_BITS	# get rounding mode
+	beq	v0, MIPS_FPU_ROUND_RN, 3f	# round to nearest
+	beq	v0, MIPS_FPU_ROUND_RZ, 5f	# round to zero (truncate)
+	beq	v0, MIPS_FPU_ROUND_RP, 1f	# round to +infinity
 	beq	t0, zero, 5f			# if sign is positive, truncate
 	b	2f
 1:
@@ -2159,11 +2159,11 @@ underflow_d:
 	move	t1, zero			# denorm or zero exponent
 	jal	_C_LABEL(set_fd_d)		# save result
 	beq	t8, zero, done			# check for exact result
-	or	a1, a1, MACH_FPC_EXCEPTION_UNDERFLOW | MACH_FPC_STICKY_UNDERFLOW
-	or	a1, a1, MACH_FPC_EXCEPTION_INEXACT | MACH_FPC_STICKY_INEXACT
-	and	v0, a1, MACH_FPC_ENABLE_INEXACT
+	or	a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
+	or	a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
+	and	v0, a1, MIPS_FPU_ENABLE_INEXACT
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	b	done
 
 /*
@@ -2171,10 +2171,10 @@ underflow_d:
  * the result is a quiet NAN.
  */
 invalid_s:					# trap invalid operation
-	or	a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
-	and	v0, a1, MACH_FPC_ENABLE_INVALID
+	or	a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+	and	v0, a1, MIPS_FPU_ENABLE_INVALID
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	move	t0, zero			# result is a quiet NAN
 	li	t1, SEXP_INF
 	li	t2, SQUIET_NAN
@@ -2186,10 +2186,10 @@ invalid_s:					# trap invalid operation
  * the result is a quiet NAN.
  */
 invalid_d:					# trap invalid operation
-	or	a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
-	and	v0, a1, MACH_FPC_ENABLE_INVALID
+	or	a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+	and	v0, a1, MIPS_FPU_ENABLE_INVALID
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	move	t0, zero			# result is a quiet NAN
 	li	t1, DEXP_INF
 	li	t2, DQUIET_NAN0
@@ -2202,10 +2202,10 @@ invalid_d:					# trap invalid operation
  * the result is INT_MAX or INT_MIN.
  */
 invalid_w:					# trap invalid operation
-	or	a1, a1, MACH_FPC_EXCEPTION_INVALID | MACH_FPC_STICKY_INVALID
-	and	v0, a1, MACH_FPC_ENABLE_INVALID
+	or	a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
+	and	v0, a1, MIPS_FPU_ENABLE_INVALID
 	bne	v0, zero, fpe_trap
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	bne	t0, zero, 1f
 	li	t2, INT_MAX			# result is INT_MAX
 	b	result_fs_w
@@ -2218,14 +2218,14 @@ invalid_w:					# trap invalid operation
  */
 fpe_trap:
 	move	a2, a1				# code = FP CSR
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	break	0
 
 /*
  * Send an illegal instruction signal to the current process.
  */
 ill:
-	ctc1	a1, MACH_FPC_CSR		# save exceptions
+	ctc1	a1, MIPS_FPU_CSR		# save exceptions
 	move	a2, a0				# code = FP instruction
 	break	0
 
diff --git a/sys/arch/pmax/pmax/kadb.c b/sys/arch/pmax/pmax/kadb.c
index beea732ea07..908b6646d5f 100644
--- a/sys/arch/pmax/pmax/kadb.c
+++ b/sys/arch/pmax/pmax/kadb.c
@@ -202,12 +202,12 @@ kdbprinttrap(causeReg, vadr)
 	int type, pc;
 	extern char *trap_type[];
 
-	type = (causeReg & MACH_CR_EXC_CODE) >> MACH_CR_EXC_CODE_SHIFT;
+	type = (causeReg & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
 
 	/* check to see if we are entering kdb via kdbpanic() */
 	pc = kdbpcb.pcb_regs[PC];
 	if (type == T_BREAK && pc < 0) {
-		if (kdbpeek(pc) == MACH_BREAK_KDB)
+		if (kdbpeek(pc) == MIPS_BREAK_KDB)
 			kdbpcb.pcb_regs[PC] = pc + 4;
 	}
 
@@ -236,12 +236,12 @@ kdbsetsstep()
 	if ((int)va < 0) {
 		/* kernel address */
 		kdb_ss_instr = kdbpeek(va);
-		kdbpoke((caddr_t)va, MACH_BREAK_SSTEP);
+		kdbpoke((caddr_t)va, MIPS_BREAK_SSTEP);
 		return;
 	}
 
 	kdb_ss_instr = fuiword(va);
-	i = suiword((caddr_t)va, MACH_BREAK_SSTEP);
+	i = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
 	if (i < 0) {
 		register struct proc *p = curproc;
 		vm_offset_t sa, ea;
@@ -252,7 +252,7 @@ kdbsetsstep()
 		rv = vm_map_protect(&p->p_vmspace->vm_map, sa, ea,
 			VM_PROT_DEFAULT, FALSE);
 		if (rv == KERN_SUCCESS) {
-			i = suiword((caddr_t)va, MACH_BREAK_SSTEP);
+			i = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
 			(void) vm_map_protect(&p->p_vmspace->vm_map,
 				sa, ea, VM_PROT_READ|VM_PROT_EXECUTE, FALSE);
 		}
@@ -270,7 +270,7 @@ kdbclrsstep()
 
 	/* ignore this trap if it is not a break trap */
 	cr = kdbvar[kdbvarchk('t')];
-	if ((cr & MACH_CR_EXC_CODE) != (T_BREAK << MACH_CR_EXC_CODE_SHIFT))
+	if ((cr & MIPS_CR_EXC_CODE) != (T_BREAK << MIPS_CR_EXC_CODE_SHIFT))
 		return;
 
 	/* fix pc if break instruction is in the delay slot */
@@ -285,7 +285,7 @@ kdbclrsstep()
 
 	/* read break instruction */
 	instr = kdbpeek(va);
-	if (instr != MACH_BREAK_SSTEP)
+	if (instr != MIPS_BREAK_SSTEP)
 		return;
 
 	if ((int)va < 0) {
@@ -768,7 +768,7 @@ kdbprintmachdep(modif)
 	case 'P': /* print TLB entries */
 		if (kdbadrflg) {
 			i = kdbadrval;
-			if (i < 0 || i > VMMACH_NUM_TLB_ENTRIES) {
+			if (i < 0 || i > MIPS1_TLB_NUM_TLB_ENTRIES) {
 				extern char *kdbBADMOD;
 
 				kdberror(kdbBADMOD);
@@ -778,12 +778,12 @@ kdbprintmachdep(modif)
 				j = i + 1;
 			else {
 				j = i + kdbcntval;
-				if (j > VMMACH_NUM_TLB_ENTRIES)
-					j = VMMACH_NUM_TLB_ENTRIES;
+				if (j > MIPS1_TLB_NUM_TLB_ENTRIES)
+					j = MIPS1_TLB_NUM_TLB_ENTRIES;
 			}
 		} else {
 			i = 0;
-			j = VMMACH_NUM_TLB_ENTRIES;
+			j = MIPS1_TLB_NUM_TLB_ENTRIES;
 		}
 		for (; i < j; i++) {
 			MachTLBRead(i);
@@ -797,7 +797,7 @@ kdbprintmachdep(modif)
 	case 'f': /* find a TLB entry by virtaddr */
 	case 'F': /* find a TLB entry by physaddr */
 		j = kdbdot & PG_FRAME;
-		for (i = 0; i < VMMACH_NUM_TLB_ENTRIES; i++) {
+		for (i = 0; i < MIPS1_TLB_NUM_TLB_ENTRIES; i++) {
 			MachTLBRead(i);
 			if (modif == 'f') {
 				if ((tlbhi & PG_FRAME) != j)
diff --git a/sys/arch/pmax/pmax/locore.S b/sys/arch/pmax/pmax/locore.S
index 39c3a2adc61..0afc4b82c5b 100644
--- a/sys/arch/pmax/pmax/locore.S
+++ b/sys/arch/pmax/pmax/locore.S
@@ -171,19 +171,19 @@
 	.globl	_C_LABEL(kernel_text)
 	_C_LABEL(kernel_text) = start
 start:
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	li	t1, MACH_CACHED_MEMORY_ADDR	# invalid address
-	mtc0	t1, MACH_COP_0_TLB_HI		# Mark entry high as invalid
-	mtc0	zero, MACH_COP_0_TLB_LOW	# Zero out low entry.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	li	t1, MIPS_KSEG0_START	# invalid address
+	mtc0	t1, MIPS_COP_0_TLB_HI		# Mark entry high as invalid
+	mtc0	zero, MIPS_COP_0_TLB_LOW	# Zero out low entry.
 /*
  * Clear the TLB (just to be safe).
  * Align the starting value (t1), the increment (t2) and the upper bound (t3).
  */
 	move	t1, zero
-	li	t2, 1 << VMMACH_TLB_INDEX_SHIFT
-	li	t3, VMMACH_NUM_TLB_ENTRIES << VMMACH_TLB_INDEX_SHIFT
+	li	t2, 1 << MIPS1_TLB_INDEX_SHIFT
+	li	t3, MIPS1_TLB_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT
 1:
-	mtc0	t1, MACH_COP_0_TLB_INDEX	# Set the index register.
+	mtc0	t1, MIPS_COP_0_TLB_INDEX	# Set the index register.
 	addu	t1, t1, t2			# Increment index.
 	bne	t1, t3, 1b			# NB: always executes next
 	tlbwi					# Write the TLB entry.
@@ -199,16 +199,16 @@ start:
 	jal	_C_LABEL(mach_init)		# mach_init(argc, argv, envp)
 	sw	zero, START_FRAME - 8(sp)	# Zero out old fp for debugger
 
-	li	t0, MACH_SR_COP_1_BIT		# Disable interrupts and
-	mtc0	t0, MACH_COP_0_STATUS_REG	#   enable the fp coprocessor
+	li	t0, MIPS_SR_COP_1_BIT		# Disable interrupts and
+	mtc0	t0, MIPS_COP_0_STATUS_REG	#   enable the fp coprocessor
 	li	sp, KERNELSTACK - START_FRAME	# switch to standard stack
-	mfc0	t0, MACH_COP_0_PRID		# read processor ID register
+	mfc0	t0, MIPS_COP_0_PRID		# read processor ID register
 
 	nop					# XXX r4000 pipeline:
 	nop					# wait for new status to
 	nop					# to be effective
 	nop
-	cfc1	t1, MACH_FPC_ID			# read FPU ID register
+	cfc1	t1, MIPS_FPU_ID			# read FPU ID register
 	sw	t0, _C_LABEL(cpu_id)		# save PRID register
 	sw	t1, _C_LABEL(fpu_id)		# save FPU ID register
 	jal	_C_LABEL(main)			# main(regs)
@@ -219,7 +219,7 @@ start:
  */
 	.set	noat
 	li	v0, PSL_USERSET
-	mtc0	v0, MACH_COP_0_STATUS_REG	# switch to user mode
+	mtc0	v0, MIPS_COP_0_STATUS_REG	# switch to user mode
 	lw	a0, UADDR+U_PCB_REGS+(SR * 4)
 	lw	t0, UADDR+U_PCB_REGS+(MULLO * 4)
 	lw	t1, UADDR+U_PCB_REGS+(MULHI * 4)
@@ -507,7 +507,7 @@ ALEAF(savectx)
 	sw	s1, U_PCB_CONTEXT+4(a0)
 	sw	s2, U_PCB_CONTEXT+8(a0)
 	sw	s3, U_PCB_CONTEXT+12(a0)
-	mfc0	v0, MACH_COP_0_STATUS_REG
+	mfc0	v0, MIPS_COP_0_STATUS_REG
 	sw	s4, U_PCB_CONTEXT+16(a0)
 	sw	s5, U_PCB_CONTEXT+20(a0)
 	sw	s6, U_PCB_CONTEXT+24(a0)
@@ -613,15 +613,15 @@ LEAF(switch_exit)
 	lw	t0, P_UPTE+0(v1)		# t0 = first u. pte
 	lw	t1, P_UPTE+4(v1)		# t1 = 2nd u. pte
 	li	v0, UADDR			# v0 = first HI entry
-	mtc0	zero, MACH_COP_0_TLB_INDEX	# set the index register
-	mtc0	v0, MACH_COP_0_TLB_HI		# init high entry
-	mtc0	t0, MACH_COP_0_TLB_LOW		# init low entry
-	li	t0, 1 << VMMACH_TLB_INDEX_SHIFT
+	mtc0	zero, MIPS_COP_0_TLB_INDEX	# set the index register
+	mtc0	v0, MIPS_COP_0_TLB_HI		# init high entry
+	mtc0	t0, MIPS_COP_0_TLB_LOW		# init low entry
+	li	t0, 1 << MIPS1_TLB_INDEX_SHIFT
 	tlbwi					# Write the TLB entry.
 	addu	v0, v0, NBPG			# 2nd HI entry
-	mtc0	t0, MACH_COP_0_TLB_INDEX	# set the index register
-	mtc0	v0, MACH_COP_0_TLB_HI		# init high entry
-	mtc0	t1, MACH_COP_0_TLB_LOW		# init low entry
+	mtc0	t0, MIPS_COP_0_TLB_INDEX	# set the index register
+	mtc0	v0, MIPS_COP_0_TLB_HI		# init high entry
+	mtc0	t1, MIPS_COP_0_TLB_LOW		# init low entry
 	sw	zero, _C_LABEL(curproc)
 	tlbwi					# Write the TLB entry.
 	b	_C_LABEL(cpu_switch)
@@ -635,8 +635,8 @@ END(switch_exit)
  * profiling.
  */
 LEAF(idle)
-	li	t0, (MACH_INT_MASK | MIPS_SR_INT_IE)
-	mtc0	t0, MACH_COP_0_STATUS_REG	# enable all interrupts
+	li	t0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# enable all interrupts
 	sw	zero, _C_LABEL(curproc)		# set curproc NULL for stats
 1:
 	lw	t0, _C_LABEL(whichqs)		# look for non-empty queue
@@ -644,7 +644,7 @@ LEAF(idle)
 	beq	t0, zero, 1b
 	nop
 	b	sw1
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable all interrupts
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable all interrupts
 END(idle)
 
 /*
@@ -662,7 +662,7 @@ NON_LEAF(cpu_switch, STAND_FRAME_SIZE, ra)
 	sw	s1, UADDR+U_PCB_CONTEXT+4
 	sw	s2, UADDR+U_PCB_CONTEXT+8
 	sw	s3, UADDR+U_PCB_CONTEXT+12
-	mfc0	t0, MACH_COP_0_STATUS_REG	# t0 = saved status register
+	mfc0	t0, MIPS_COP_0_STATUS_REG	# t0 = saved status register
 	sw	s4, UADDR+U_PCB_CONTEXT+16
 	sw	s5, UADDR+U_PCB_CONTEXT+20
 	sw	s6, UADDR+U_PCB_CONTEXT+24
@@ -673,7 +673,7 @@ NON_LEAF(cpu_switch, STAND_FRAME_SIZE, ra)
 	addu	t2, t2, 1
 	sw	t2, _C_LABEL(cnt)+V_SWTCH
 	beq	t1, zero, _C_LABEL(idle)	# if none, idle
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable all interrupts
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable all interrupts
 sw1:
 	nop					# wait for intrs disabled
 	nop
@@ -717,7 +717,7 @@ sw1:
 	jal	_C_LABEL(pmap_alloc_tlbpid)	# v0 = TLB PID
 	move	s0, a0				# BDSLOT: save p
 	sw	s0, _C_LABEL(curproc)		# set curproc
-	sll	v0, v0, VMMACH_TLB_PID_SHIFT	# v0 = aligned PID
+	sll	v0, v0, MIPS_TLB_PID_SHIFT	# v0 = aligned PID
 	lw	t0, P_UPTE+0(s0)		# t0 = first u. pte
 	lw	t1, P_UPTE+4(s0)		# t1 = 2nd u. pte
 	or	v0, v0, UADDR			# v0 = first HI entry
@@ -726,15 +726,15 @@ sw1:
  * NOTE: This is hard coded to UPAGES == 2.
  * Also, there should be no TLB faults at this point.
  */
-	mtc0	zero, MACH_COP_0_TLB_INDEX	# set the index register
-	mtc0	v0, MACH_COP_0_TLB_HI		# init high entry
-	mtc0	t0, MACH_COP_0_TLB_LOW		# init low entry
-	li	t0, 1 << VMMACH_TLB_INDEX_SHIFT
+	mtc0	zero, MIPS_COP_0_TLB_INDEX	# set the index register
+	mtc0	v0, MIPS_COP_0_TLB_HI		# init high entry
+	mtc0	t0, MIPS_COP_0_TLB_LOW		# init low entry
+	li	t0, 1 << MIPS1_TLB_INDEX_SHIFT
 	tlbwi					# Write the TLB entry.
 	addu	v0, v0, NBPG			# 2nd HI entry
-	mtc0	t0, MACH_COP_0_TLB_INDEX	# set the index register
-	mtc0	v0, MACH_COP_0_TLB_HI		# init high entry
-	mtc0	t1, MACH_COP_0_TLB_LOW		# init low entry
+	mtc0	t0, MIPS_COP_0_TLB_INDEX	# set the index register
+	mtc0	v0, MIPS_COP_0_TLB_HI		# init high entry
+	mtc0	t1, MIPS_COP_0_TLB_LOW		# init low entry
 	nop
 	tlbwi					# Write the TLB entry.
 /*
@@ -753,7 +753,7 @@ sw1:
 	lw	s7, UADDR+U_PCB_CONTEXT+28
 	lw	sp, UADDR+U_PCB_CONTEXT+32
 	lw	s8, UADDR+U_PCB_CONTEXT+36
-	mtc0	v0, MACH_COP_0_STATUS_REG
+	mtc0	v0, MIPS_COP_0_STATUS_REG
 	j	ra
 	li	v0, 1				# possible return to 'savectx()'
 END(cpu_switch)
@@ -932,56 +932,56 @@ END(_remque)
  */
 
 LEAF(setsoftclock)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# save status register
-	mtc0	zero, MACH_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
 	nop
-	mfc0	v0, MACH_COP_0_CAUSE_REG	# read cause register
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
 	nop
-	or	v0, v0, MACH_SOFT_INT_MASK_0	# set soft clock interrupt
-	mtc0	v0, MACH_COP_0_CAUSE_REG	# save it
-	mtc0	v1, MACH_COP_0_STATUS_REG
+	or	v0, v0, MIPS_SOFT_INT_MASK_0	# set soft clock interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
 	j	ra
 	nop
 END(setsoftclock)
 
 LEAF(clearsoftclock)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# save status register
-	mtc0	zero, MACH_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
 	nop
 	nop
-	mfc0	v0, MACH_COP_0_CAUSE_REG	# read cause register
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
 	nop
-	and	v0, v0, ~MACH_SOFT_INT_MASK_0	# clear soft clock interrupt
-	mtc0	v0, MACH_COP_0_CAUSE_REG	# save it
-	mtc0	v1, MACH_COP_0_STATUS_REG
+	and	v0, v0, ~MIPS_SOFT_INT_MASK_0	# clear soft clock interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
 	j	ra
 	nop
 END(clearsoftclock)
 
 LEAF(setsoftnet)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# save status register
-	mtc0	zero, MACH_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
 	nop
 	nop
-	mfc0	v0, MACH_COP_0_CAUSE_REG	# read cause register
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
 	nop
-	or	v0, v0, MACH_SOFT_INT_MASK_1	# set soft net interrupt
-	mtc0	v0, MACH_COP_0_CAUSE_REG	# save it
-	mtc0	v1, MACH_COP_0_STATUS_REG
+	or	v0, v0, MIPS_SOFT_INT_MASK_1	# set soft net interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
 	j	ra
 	nop
 END(setsoftnet)
 
 LEAF(clearsoftnet)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# save status register
-	mtc0	zero, MACH_COP_0_STATUS_REG	# disable interrupts (2 cycles)
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# save status register
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable interrupts (2 cycles)
 	nop
 	nop
-	mfc0	v0, MACH_COP_0_CAUSE_REG	# read cause register
+	mfc0	v0, MIPS_COP_0_CAUSE_REG	# read cause register
 	nop
-	and	v0, v0, ~MACH_SOFT_INT_MASK_1	# clear soft net interrupt
-	mtc0	v0, MACH_COP_0_CAUSE_REG	# save it
-	mtc0	v1, MACH_COP_0_STATUS_REG
+	and	v0, v0, ~MIPS_SOFT_INT_MASK_1	# clear soft net interrupt
+	mtc0	v0, MIPS_COP_0_CAUSE_REG	# save it
+	mtc0	v1, MIPS_COP_0_STATUS_REG
 	j	ra
 	nop
 END(clearsoftnet)
@@ -991,41 +991,41 @@ END(clearsoftnet)
  */
 
 LEAF(MachEnableIntr)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
 	nop
 	or	v0, v0, MIPS_SR_INT_IE
-	mtc0	v0, MACH_COP_0_STATUS_REG	# enable all interrupts
+	mtc0	v0, MIPS_COP_0_STATUS_REG	# enable all interrupts
 	j	ra
 	nop
 END(MachEnableIntr)
 
 LEAF(spl0)
 ALEAF(spllow)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
 	nop
-	or	t0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
-	mtc0	t0, MACH_COP_0_STATUS_REG	# enable all interrupts
+	or	t0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# enable all interrupts
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(spl0)
 
 LEAF(splsoftclock)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~MACH_SOFT_INT_MASK_0	# disable soft clock
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~MIPS_SOFT_INT_MASK_0	# disable soft clock
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(splsoftclock)
 
 LEAF(splsoftnet)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(splsoftnet)
 
 /*
@@ -1038,67 +1038,67 @@ END(splsoftnet)
  * Block out int2 (hardware interrupt 0) and lower mips levels.
  */
 LEAF(cpu_spl0)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_SPL0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(cpu_spl0)
 
 /*
  * Block out Int3 (hardware interrupt 1) and lower mips levels.
  */
 LEAF(cpu_spl1)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_SPL1)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL1)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(cpu_spl1)
 
 LEAF(cpu_spl2)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_SPL2)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL2)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(cpu_spl2)
 
 LEAF(cpu_spl3)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_SPL3)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL3)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(cpu_spl3)
 
 LEAF(cpu_spl4)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_SPL4)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL4)
 
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(cpu_spl4)
 
 LEAF(cpu_spl5)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_SPL5)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_SPL5)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(cpu_spl5)
 
 /*
@@ -1111,63 +1111,63 @@ END(cpu_spl5)
  * XXX  the spl handling really needs re-writing from scratch.
  */
 LEAF(Mach_spl0)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_0|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(Mach_spl0)
 
 LEAF(Mach_spl1)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_1|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(Mach_spl1)
 
 LEAF(Mach_spl2)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_2|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(Mach_spl2)
 
 LEAF(Mach_spl3)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_3|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(Mach_spl3)
 
 LEAF(Mach_spl4)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_4|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(Mach_spl4)
 
 LEAF(Mach_spl5)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
-	li	t0, ~(MACH_INT_MASK_5|MACH_SOFT_INT_MASK_1|MACH_SOFT_INT_MASK_0)
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
+	li	t0, ~(MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK_1|MIPS_SOFT_INT_MASK_0)
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(Mach_spl5)
 
 
@@ -1177,13 +1177,13 @@ END(Mach_spl5)
  */
 LEAF(splhigh)
 ALEAF(_splhigh)
-	mfc0	v0, MACH_COP_0_STATUS_REG	# read status register
+	mfc0	v0, MIPS_COP_0_STATUS_REG	# read status register
 	li	t0, ~MIPS_SR_INT_IE	# disable all interrupts
 	and	t0, t0, v0
-	mtc0	t0, MACH_COP_0_STATUS_REG	# save it
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# save it
 	nop					# 3 ins to disable on r4x00
 	j	ra
-	and	v0, v0, (MACH_INT_MASK | MIPS_SR_INT_IE)
+	and	v0, v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)
 END(splhigh)
 
 /*
@@ -1191,11 +1191,11 @@ END(splhigh)
  */
 LEAF(splx)
 ALEAF(_splx)
-	mfc0	v0, MACH_COP_0_STATUS_REG
-	li	t0, ~(MACH_INT_MASK | MIPS_SR_INT_IE)
+	mfc0	v0, MIPS_COP_0_STATUS_REG
+	li	t0, ~(MIPS_INT_MASK | MIPS_SR_INT_IE)
 	and	t0, t0, v0
 	or	t0, t0, a0
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 	nop					# 3 ins to disable
 	j	ra
 	nop
@@ -1250,7 +1250,7 @@ END(MachEmptyWriteBuffer)
  *----------------------------------------------------------------------------
  */
 LEAF(MachGetCauseReg)
-	mfc0	v0, MACH_COP_0_CAUSE_REG
+	mfc0	v0, MIPS_COP_0_CAUSE_REG
 	j	ra
 	nop
 END(MachGetCauseReg)
@@ -1274,9 +1274,9 @@ END(MachGetCauseReg)
  *----------------------------------------------------------------------------
  */
 LEAF(MachSwitchFPState)
-	mfc0	t1, MACH_COP_0_STATUS_REG	# Save old SR
-	li	t0, MACH_SR_COP_1_BIT		# enable the coprocessor
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mfc0	t1, MIPS_COP_0_STATUS_REG	# Save old SR
+	li	t0, MIPS_SR_COP_1_BIT		# enable the coprocessor
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 
 	beq	a0, zero, 1f			# skip save if NULL pointer
 	nop
@@ -1285,9 +1285,9 @@ LEAF(MachSwitchFPState)
  * have completed.
  */
 	lw	a0, P_ADDR(a0)			# get pointer to pcb for proc
-	cfc1	t0, MACH_FPC_CSR		# stall til FP done
-	cfc1	t0, MACH_FPC_CSR		# now get status
-	li	t3, ~MACH_SR_COP_1_BIT
+	cfc1	t0, MIPS_FPU_CSR		# stall til FP done
+	cfc1	t0, MIPS_FPU_CSR		# now get status
+	li	t3, ~MIPS_SR_COP_1_BIT
 	lw	t2, U_PCB_REGS+(PS * 4)(a0)	# get CPU status register
 	sw	t0, U_PCB_FPREGS+(32 * 4)(a0)	# save FP status
 	and	t2, t2, t3			# clear COP_1 enable bit
@@ -1366,11 +1366,11 @@ LEAF(MachSwitchFPState)
 	lwc1	$f30, U_PCB_FPREGS+(30 * 4)(a1)
 	lwc1	$f31, U_PCB_FPREGS+(31 * 4)(a1)
 
-	and	t0, t0, ~MACH_FPC_EXCEPTION_BITS
-	ctc1	t0, MACH_FPC_CSR
+	and	t0, t0, ~MIPS_FPU_EXCEPTION_BITS
+	ctc1	t0, MIPS_FPU_CSR
 	nop
 
-	mtc0	t1, MACH_COP_0_STATUS_REG	# Restore the status register.
+	mtc0	t1, MIPS_COP_0_STATUS_REG	# Restore the status register.
 	j	ra
 	nop
 END(MachSwitchFPState)
@@ -1394,19 +1394,19 @@ END(MachSwitchFPState)
  */
 LEAF(MachSaveCurFPState)
 	lw	a0, P_ADDR(a0)			# get pointer to pcb for proc
-	mfc0	t1, MACH_COP_0_STATUS_REG	# Disable interrupts and
-	li	t0, MACH_SR_COP_1_BIT		#  enable the coprocessor
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mfc0	t1, MIPS_COP_0_STATUS_REG	# Disable interrupts and
+	li	t0, MIPS_SR_COP_1_BIT		#  enable the coprocessor
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 	sw	zero, _C_LABEL(machFPCurProcPtr) # indicate state has been saved
 /*
  * First read out the status register to make sure that all FP operations
  * have completed.
  */
 	lw	t2, U_PCB_REGS+(PS * 4)(a0)	# get CPU status register
-	li	t3, ~MACH_SR_COP_1_BIT
+	li	t3, ~MIPS_SR_COP_1_BIT
 	and	t2, t2, t3			# clear COP_1 enable bit
-	cfc1	t0, MACH_FPC_CSR		# stall til FP done
-	cfc1	t0, MACH_FPC_CSR		# now get status
+	cfc1	t0, MIPS_FPU_CSR		# stall til FP done
+	cfc1	t0, MIPS_FPU_CSR		# now get status
 	sw	t2, U_PCB_REGS+(PS * 4)(a0)	# save new status register
 	sw	t0, U_PCB_FPREGS+(32 * 4)(a0)	# save FP status
 /*
@@ -1445,7 +1445,7 @@ LEAF(MachSaveCurFPState)
 	swc1	$f30, U_PCB_FPREGS+(30 * 4)(a0)
 	swc1	$f31, U_PCB_FPREGS+(31 * 4)(a0)
 
-	mtc0	t1, MACH_COP_0_STATUS_REG	# Restore the status register.
+	mtc0	t1, MIPS_COP_0_STATUS_REG	# Restore the status register.
 	j	ra
 	nop
 END(MachSaveCurFPState)
@@ -1481,19 +1481,19 @@ NON_LEAF(MachFPInterrupt, STAND_FRAME_SIZE, ra)
 ALEAF(MachFPTrap)
 
 	subu	sp, sp, STAND_FRAME_SIZE
-	mfc0	t0, MACH_COP_0_STATUS_REG
+	mfc0	t0, MIPS_COP_0_STATUS_REG
 	sw	ra, STAND_RA_OFFSET(sp)
 	.mask	0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE)
 
-	or	t1, t0, MACH_SR_COP_1_BIT
-	mtc0	t1, MACH_COP_0_STATUS_REG
+	or	t1, t0, MIPS_SR_COP_1_BIT
+	mtc0	t1, MIPS_COP_0_STATUS_REG
 	nop
 	nop
 	nop				# 1st extra nop for r4k
 	nop				# 2nd extra nop for r4k
 
-	cfc1	t1, MACH_FPC_CSR	# stall til FP done
-	cfc1	t1, MACH_FPC_CSR	# now get status
+	cfc1	t1, MIPS_FPU_CSR	# stall til FP done
+	cfc1	t1, MIPS_FPU_CSR	# now get status
 	nop
 	sll	t2, t1, (31 - 17)	# unimplemented operation?
 	bgez	t2, 3f			# no, normal trap
@@ -1534,16 +1534,16 @@ ALEAF(MachFPTrap)
  * Check to see if the instruction to be emulated is a floating-point
  * instruction.
  */
-	srl	a3, a0, MACH_OPCODE_SHIFT
-	beq	a3, MACH_OPCODE_C1, 4f		# this should never fail
+	srl	a3, a0, MIPS_OPCODE_SHIFT
+	beq	a3, MIPS_OPCODE_C1, 4f		# this should never fail
 	nop
 /*
  * Send a floating point exception signal to the current process.
  */
 3:
 	lw	a0, _C_LABEL(curproc)		# get current process
-	cfc1	a2, MACH_FPC_CSR		# code = FP execptions
-	ctc1	zero, MACH_FPC_CSR		# Clear exceptions
+	cfc1	a2, MIPS_FPU_CSR		# code = FP execptions
+	ctc1	zero, MIPS_FPU_CSR		# Clear exceptions
 	jal	_C_LABEL(trapsignal)
 	li	a1, SIGFPE
 	b	FPReturn
@@ -1560,10 +1560,10 @@ ALEAF(MachFPTrap)
  * Turn off the floating point coprocessor and return.
  */
 FPReturn:
-	mfc0	t0, MACH_COP_0_STATUS_REG
+	mfc0	t0, MIPS_COP_0_STATUS_REG
 	lw	ra, STAND_RA_OFFSET(sp)
-	and	t0, t0, ~MACH_SR_COP_1_BIT
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	and	t0, t0, ~MIPS_SR_COP_1_BIT
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 	j	ra
 	addu	sp, sp, STAND_FRAME_SIZE
 END(MachFPInterrupt)
@@ -1704,7 +1704,7 @@ L* }
  */
 LEAF(kdbpanic)
 ALEAF(mdbpanic)
-	break	MACH_BREAK_KDB_VAL
+	break	MIPS_BREAK_KDB_VAL
 	j	ra
 	nop
 END(kdbpanic)
diff --git a/sys/arch/pmax/pmax/locore_r2000.S b/sys/arch/pmax/pmax/locore_r2000.S
index aa3b77f342e..cd0a66fc243 100644
--- a/sys/arch/pmax/pmax/locore_r2000.S
+++ b/sys/arch/pmax/pmax/locore_r2000.S
@@ -68,13 +68,13 @@
 	.globl	_C_LABEL(mips1_UTLBMiss)
 _C_LABEL(mips1_UTLBMiss):
 	.set	noat
-	mfc0	k0, MACH_COP_0_BAD_VADDR	# get the virtual address
+	mfc0	k0, MIPS_COP_0_BAD_VADDR	# get the virtual address
 	lw	k1, UADDR+U_PCB_SEGTAB		# get the current segment table
 	bltz	k0, 1f				# R3000 chip bug
 	srl	k0, k0, SEGSHIFT		# compute segment table index
 	sll	k0, k0, 2
 	addu	k1, k1, k0
-	mfc0	k0, MACH_COP_0_BAD_VADDR	# get the virtual address
+	mfc0	k0, MIPS_COP_0_BAD_VADDR	# get the virtual address
 	lw	k1, 0(k1)			# get pointer to segment map
 	srl	k0, k0, PGSHIFT - 2		# compute segment map index
 	andi	k0, k0, (NPTEPG - 1) << 2
@@ -83,13 +83,13 @@ _C_LABEL(mips1_UTLBMiss):
 	lw	k0, 0(k1)			# get page PTE
 	nop
 	beq	k0, zero, 2f			# dont load invalid entries
-	mtc0	k0, MACH_COP_0_TLB_LOW
-	mfc0	k1, MACH_COP_0_EXC_PC		# get return address
+	mtc0	k0, MIPS_COP_0_TLB_LOW
+	mfc0	k1, MIPS_COP_0_EXC_PC		# get return address
 	tlbwr					# update TLB
 	j	k1
 	rfe
 1:
-	mfc0	k1, MACH_COP_0_EXC_PC		# get return address
+	mfc0	k1, MIPS_COP_0_EXC_PC		# get return address
 	nop
 	j	k1
 	rfe
@@ -121,11 +121,11 @@ _C_LABEL(mips1_exception):
  * Find out what mode we came from and jump to the proper handler.
  */
 	.set	noat
-	mfc0	k0, MACH_COP_0_STATUS_REG	# Get the status register
-	mfc0	k1, MACH_COP_0_CAUSE_REG	# Get the cause register value.
-	and	k0, k0, MIPS_3K_SR_KU_PREV	# test for user mode
+	mfc0	k0, MIPS_COP_0_STATUS_REG	# Get the status register
+	mfc0	k1, MIPS_COP_0_CAUSE_REG	# Get the cause register value.
+	and	k0, k0, MIPS1_SR_KU_PREV	# test for user mode
 	sll	k0, k0, 4			# shift user bit for cause index
-	and	k1, k1, MIPS_3K_CR_EXC_CODE	# Mask out the cause bits.
+	and	k1, k1, MIPS1_CR_EXC_CODE	# Mask out the cause bits.
 	or	k1, k1, k0			# change index to user table
 1:
 	la	k0, _C_LABEL(mips1_ExceptionTable) # get base of the jump table
@@ -157,9 +157,9 @@ _C_LABEL(mips1_exceptionEnd):
  */
 mips1_SlowFault:
 	.set	noat
-	mfc0	k0, MACH_COP_0_STATUS_REG
+	mfc0	k0, MIPS_COP_0_STATUS_REG
 	nop
-	and	k0, k0, MACH_SR_KU_PREV
+	and	k0, k0, MIPS_SR_KU_PREV
 	bne	k0, zero, _C_LABEL(mips1_UserGenException)
 	nop
 	.set	at
@@ -227,22 +227,22 @@ NNON_LEAF(mips1_KernGenException, KERN_EXC_FRAME_SIZE, ra)
 	sw	a2, KERN_REG_OFFSET + 20(sp)
 	sw	a3, KERN_REG_OFFSET + 24(sp)
 	sw	t0, KERN_REG_OFFSET + 28(sp)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t1, KERN_REG_OFFSET + 32(sp)
 	sw	t2, KERN_REG_OFFSET + 36(sp)
 	sw	t3, KERN_REG_OFFSET + 40(sp)
 	sw	t4, KERN_REG_OFFSET + 44(sp)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	t5, KERN_REG_OFFSET + 48(sp)
 	sw	t6, KERN_REG_OFFSET + 52(sp)
 	sw	t7, KERN_REG_OFFSET + 56(sp)
 	sw	t8, KERN_REG_OFFSET + 60(sp)
-	mfc0	a2, MACH_COP_0_BAD_VADDR	# Third arg is the fault addr.
+	mfc0	a2, MIPS_COP_0_BAD_VADDR	# Third arg is the fault addr.
 	sw	t9, KERN_REG_OFFSET + 64(sp)
 	sw	ra, KERN_REG_OFFSET + 68(sp)
 	sw	v0, KERN_MULT_LO_OFFSET(sp)
 	sw	v1, KERN_MULT_HI_OFFSET(sp)
-	mfc0	a3, MACH_COP_0_EXC_PC		# Fourth arg is the pc.
+	mfc0	a3, MIPS_COP_0_EXC_PC		# Fourth arg is the pc.
 	sw	a0, KERN_SR_OFFSET(sp)
 /*
  * Call the exception handler.
@@ -256,7 +256,7 @@ NNON_LEAF(mips1_KernGenException, KERN_EXC_FRAME_SIZE, ra)
 	lw	a0, KERN_SR_OFFSET(sp)
 	lw	t0, KERN_MULT_LO_OFFSET(sp)
 	lw	t1, KERN_MULT_HI_OFFSET(sp)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# Restore the SR, disable intrs
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# Restore the SR, disable intrs
 	mtlo	t0
 	mthi	t1
 	move	k0, v0
@@ -306,22 +306,22 @@ NNON_LEAF(mips1_UserGenException, STAND_FRAME_SIZE, ra)
 	sw	t2, UADDR+U_PCB_REGS+(T2 * 4)
 	sw	t3, UADDR+U_PCB_REGS+(T3 * 4)
 	sw	t4, UADDR+U_PCB_REGS+(T4 * 4)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t5, UADDR+U_PCB_REGS+(T5 * 4)
 	sw	t6, UADDR+U_PCB_REGS+(T6 * 4)
 	sw	t7, UADDR+U_PCB_REGS+(T7 * 4)
 	sw	s0, UADDR+U_PCB_REGS+(S0 * 4)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	s1, UADDR+U_PCB_REGS+(S1 * 4)
 	sw	s2, UADDR+U_PCB_REGS+(S2 * 4)
 	sw	s3, UADDR+U_PCB_REGS+(S3 * 4)
 	sw	s4, UADDR+U_PCB_REGS+(S4 * 4)
-	mfc0	a2, MACH_COP_0_BAD_VADDR	# Third arg is the fault addr
+	mfc0	a2, MIPS_COP_0_BAD_VADDR	# Third arg is the fault addr
 	sw	s5, UADDR+U_PCB_REGS+(S5 * 4)
 	sw	s6, UADDR+U_PCB_REGS+(S6 * 4)
 	sw	s7, UADDR+U_PCB_REGS+(S7 * 4)
 	sw	t8, UADDR+U_PCB_REGS+(T8 * 4)
-	mfc0	a3, MACH_COP_0_EXC_PC		# Fourth arg is the pc.
+	mfc0	a3, MIPS_COP_0_EXC_PC		# Fourth arg is the pc.
 	sw	t9, UADDR+U_PCB_REGS+(T9 * 4)
 	sw	gp, UADDR+U_PCB_REGS+(GP * 4)
 	sw	sp, UADDR+U_PCB_REGS+(SP * 4)
@@ -337,20 +337,20 @@ NNON_LEAF(mips1_UserGenException, STAND_FRAME_SIZE, ra)
 	sw	a3, UADDR+U_PCB_REGS+(PC * 4)
 	sw	a3, STAND_RA_OFFSET(sp)		# for debugging
 	.set	at
-	and	t0, a0, ~MACH_SR_COP_1_BIT	# Turn off the FPU.
+	and	t0, a0, ~MIPS_SR_COP_1_BIT	# Turn off the FPU.
 	.set	noat
 /*
  * Call the exception handler.
  */
 	jal	_C_LABEL(trap)
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 /*
  * Restore user registers and return. NOTE: interrupts are enabled.
  */
 	lw	a0, UADDR+U_PCB_REGS+(SR * 4)
 	lw	t0, UADDR+U_PCB_REGS+(MULLO * 4)
 	lw	t1, UADDR+U_PCB_REGS+(MULHI * 4)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# this should disable interrupts
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# this should disable interrupts
 	mtlo	t0
 	mthi	t1
 	lw	k0, UADDR+U_PCB_REGS+(PC * 4)
@@ -406,17 +406,17 @@ NNON_LEAF(mips1_KernIntr, KINTR_FRAME_SIZE, ra)
 	sw	a2, KINTR_REG_OFFSET + 20(sp)
 	sw	a3, KINTR_REG_OFFSET + 24(sp)
 	sw	t0, KINTR_REG_OFFSET + 28(sp)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t1, KINTR_REG_OFFSET + 32(sp)
 	sw	t2, KINTR_REG_OFFSET + 36(sp)
 	sw	t3, KINTR_REG_OFFSET + 40(sp)
 	sw	t4, KINTR_REG_OFFSET + 44(sp)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	t5, KINTR_REG_OFFSET + 48(sp)
 	sw	t6, KINTR_REG_OFFSET + 52(sp)
 	sw	t7, KINTR_REG_OFFSET + 56(sp)
 	sw	t8, KINTR_REG_OFFSET + 60(sp)
-	mfc0	a2, MACH_COP_0_EXC_PC		# Third arg is the pc.
+	mfc0	a2, MIPS_COP_0_EXC_PC		# Third arg is the pc.
 	sw	t9, KINTR_REG_OFFSET + 64(sp)
 	sw	ra, KINTR_REG_OFFSET + 68(sp)
 	sw	v0, KINTR_MULT_LO_OFFSET(sp)
@@ -437,7 +437,7 @@ NNON_LEAF(mips1_KernIntr, KINTR_FRAME_SIZE, ra)
 	lw	a0, KINTR_SR_OFFSET(sp)
 	lw	t0, KINTR_MULT_LO_OFFSET(sp)
 	lw	t1, KINTR_MULT_HI_OFFSET(sp)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# Restore the SR, disable intrs
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# Restore the SR, disable intrs
 	mtlo	t0
 	mthi	t1
 	lw	k0, STAND_RA_OFFSET(sp)
@@ -489,17 +489,17 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
 	sw	a2, UADDR+U_PCB_REGS+(A2 * 4)
 	sw	a3, UADDR+U_PCB_REGS+(A3 * 4)
 	sw	t0, UADDR+U_PCB_REGS+(T0 * 4)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t1, UADDR+U_PCB_REGS+(T1 * 4)
 	sw	t2, UADDR+U_PCB_REGS+(T2 * 4)
 	sw	t3, UADDR+U_PCB_REGS+(T3 * 4)
 	sw	t4, UADDR+U_PCB_REGS+(T4 * 4)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	t5, UADDR+U_PCB_REGS+(T5 * 4)
 	sw	t6, UADDR+U_PCB_REGS+(T6 * 4)
 	sw	t7, UADDR+U_PCB_REGS+(T7 * 4)
 	sw	t8, UADDR+U_PCB_REGS+(T8 * 4)
-	mfc0	a2, MACH_COP_0_EXC_PC		# Third arg is the pc.
+	mfc0	a2, MIPS_COP_0_EXC_PC		# Third arg is the pc.
 	sw	t9, UADDR+U_PCB_REGS+(T9 * 4)
 	sw	gp, UADDR+U_PCB_REGS+(GP * 4)
 	sw	sp, UADDR+U_PCB_REGS+(SP * 4)
@@ -513,9 +513,9 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
 	la	gp, _C_LABEL(_gp)		# switch to kernel GP
 #endif
 	.set	at
-	and	t0, a0, ~MACH_SR_COP_1_BIT	# Turn off the FPU.
+	and	t0, a0, ~MIPS_SR_COP_1_BIT	# Turn off the FPU.
 	.set	noat
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 /*
  * Call the interrupt handler.
  */
@@ -526,7 +526,7 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
  */
 	lw	a0, UADDR+U_PCB_REGS+(SR * 4)
 	lw	v0, _C_LABEL(astpending)	# any pending interrupts?
-	mtc0	a0, MACH_COP_0_STATUS_REG	# Restore the SR, disable intrs
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# Restore the SR, disable intrs
 	bne	v0, zero, 1f			# dont restore, call softintr
 	lw	t0, UADDR+U_PCB_REGS+(MULLO * 4)
 	lw	t1, UADDR+U_PCB_REGS+(MULHI * 4)
@@ -569,19 +569,19 @@ NNON_LEAF(mips1_UserIntr, STAND_FRAME_SIZE, ra)
 	sw	s6, UADDR+U_PCB_REGS+(S6 * 4)
 	sw	s7, UADDR+U_PCB_REGS+(S7 * 4)
 	sw	s8, UADDR+U_PCB_REGS+(S8 * 4)
-	li	t0, MACH_HARD_INT_MASK | MIPS_SR_INT_IE
+	li	t0, MIPS_HARD_INT_MASK | MIPS_SR_INT_IE
 /*
  * Call the software interrupt handler.
  */
 	jal	_C_LABEL(softintr)
-	mtc0	t0, MACH_COP_0_STATUS_REG	# enable interrupts (spl0)
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# enable interrupts (spl0)
 /*
  * Restore user registers and return. NOTE: interrupts are enabled.
  */
 	lw	a0, UADDR+U_PCB_REGS+(SR * 4)
 	lw	t0, UADDR+U_PCB_REGS+(MULLO * 4)
 	lw	t1, UADDR+U_PCB_REGS+(MULHI * 4)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# this should disable interrupts
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# this should disable interrupts
 	mtlo	t0
 	mthi	t1
 	lw	k0, UADDR+U_PCB_REGS+(PC * 4)
@@ -633,21 +633,21 @@ _C_LABEL(mips1_exceptionentry_end):
 NLEAF(mips1_TLBModException)
 	.set	noat
 	tlbp					# find the TLB entry
-	mfc0	k0, MACH_COP_0_TLB_LOW		# get the physical address
-	mfc0	k1, MACH_COP_0_TLB_INDEX	# check to be sure its valid
-	or	k0, k0, VMMACH_TLB_MOD_BIT	# update TLB
+	mfc0	k0, MIPS_COP_0_TLB_LOW		# get the physical address
+	mfc0	k1, MIPS_COP_0_TLB_INDEX	# check to be sure its valid
+	or	k0, k0, MIPS1_TLB_MOD_BIT	# update TLB
 	blt	k1, zero, 4f			# not found!!!
-	mtc0	k0, MACH_COP_0_TLB_LOW
-	li	k1, MACH_CACHED_MEMORY_ADDR
+	mtc0	k0, MIPS_COP_0_TLB_LOW
+	li	k1, MIPS_KSEG0_START
 	subu	k0, k0, k1
-	srl	k0, k0, VMMACH_TLB_PHYS_PAGE_SHIFT
+	srl	k0, k0, MIPS1_TLB_PHYS_PAGE_SHIFT
 	la	k1, pmap_attributes
 	addu	k0, k0, k1
 	lbu	k1, 0(k0)			# fetch old value
 	nop
 	or	k1, k1, 1			# set modified bit
 	sb	k1, 0(k0)			# save new value
-	mfc0	k0, MACH_COP_0_EXC_PC		# get return address
+	mfc0	k0, MIPS_COP_0_EXC_PC		# get return address
 	nop
 	j	k0
 	rfe
@@ -675,7 +675,7 @@ END(mips1_TLBModException)
  */
 NLEAF(mips1_TLBMissException)
 	.set	noat
-	mfc0	k0, MACH_COP_0_BAD_VADDR	# get the fault address
+	mfc0	k0, MIPS_COP_0_BAD_VADDR	# get the fault address
 	li	k1, VM_MIN_KERNEL_ADDRESS	# compute index
 	subu	k0, k0, k1
 	lw	k1, _C_LABEL(Sysmapsize)	# index within range?
@@ -687,8 +687,8 @@ NLEAF(mips1_TLBMissException)
 	sll	k0, k0, 2			# compute offset from index
 	addu	k1, k1, k0
 	lw	k0, 0(k1)			# get PTE entry
-	mfc0	k1, MACH_COP_0_EXC_PC		# get return address
-	mtc0	k0, MACH_COP_0_TLB_LOW		# save PTE entry
+	mfc0	k1, MIPS_COP_0_EXC_PC		# get return address
+	mtc0	k0, MIPS_COP_0_TLB_LOW		# save PTE entry
 	and	k0, k0, PG_V			# check for valid entry
 	beq	k0, zero, _C_LABEL(mips1_KernGenException) # PTE invalid
 	nop
@@ -706,15 +706,15 @@ NLEAF(mips1_TLBMissException)
 	sw	sp, 24(a0)
 	move	sp, a0
 	la	a0, 1f
-	mfc0	a2, MACH_COP_0_STATUS_REG
-	mfc0	a3, MACH_COP_0_CAUSE_REG
-	mfc0	a1, MACH_COP_0_EXC_PC
+	mfc0	a2, MIPS_COP_0_STATUS_REG
+	mfc0	a3, MIPS_COP_0_CAUSE_REG
+	mfc0	a1, MIPS_COP_0_EXC_PC
 	sw	a2, 16(sp)
 	sw	a3, 20(sp)
 	sw	sp, 24(sp)
 	move	a2, ra
 	jal	_C_LABEL(printf)
-	mfc0	a3, MACH_COP_0_BAD_VADDR
+	mfc0	a3, MIPS_COP_0_BAD_VADDR
 	.data
 1:
 	.asciiz	"ktlbmiss: PC %x RA %x ADR %x\nSR %x CR %x SP %x\n"
@@ -746,20 +746,20 @@ END(mips1_TLBMissException)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBWriteIndexed)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t0, MACH_COP_0_TLB_HI		# Save the current PID.
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t0, MIPS_COP_0_TLB_HI		# Save the current PID.
 
-	sll	a0, a0, VMMACH_TLB_INDEX_SHIFT
-	mtc0	a0, MACH_COP_0_TLB_INDEX	# Set the index.
-	mtc0	a1, MACH_COP_0_TLB_HI		# Set up entry high.
-	mtc0	a2, MACH_COP_0_TLB_LOW		# Set up entry low.
+	sll	a0, a0, MIPS1_TLB_INDEX_SHIFT
+	mtc0	a0, MIPS_COP_0_TLB_INDEX	# Set the index.
+	mtc0	a1, MIPS_COP_0_TLB_HI		# Set up entry high.
+	mtc0	a2, MIPS_COP_0_TLB_LOW		# Set up entry low.
 	nop
 	tlbwi					# Write the TLB
 
-	mtc0	t0, MACH_COP_0_TLB_HI		# Restore the PID.
+	mtc0	t0, MIPS_COP_0_TLB_HI		# Restore the PID.
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBWriteIndexed)
 
 #if 0
@@ -782,19 +782,19 @@ END(mips1_TLBWriteIndexed)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBWriteRandom)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	v0, MACH_COP_0_TLB_HI		# Save the current PID.
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	v0, MIPS_COP_0_TLB_HI		# Save the current PID.
 	nop
 
-	mtc0	a0, MACH_COP_0_TLB_HI		# Set up entry high.
-	mtc0	a1, MACH_COP_0_TLB_LOW		# Set up entry low.
+	mtc0	a0, MIPS_COP_0_TLB_HI		# Set up entry high.
+	mtc0	a1, MIPS_COP_0_TLB_LOW		# Set up entry low.
 	nop
 	tlbwr					# Write the TLB
 
-	mtc0	v0, MACH_COP_0_TLB_HI		# Restore the PID.
+	mtc0	v0, MIPS_COP_0_TLB_HI		# Restore the PID.
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBWriteRandom)
 #endif
 
@@ -816,8 +816,8 @@ END(mips1_TLBWriteRandom)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_SetPID)
-	sll	a0, a0, VMMACH_TLB_PID_SHIFT	# put PID in right spot
-	mtc0	a0, MACH_COP_0_TLB_HI		# Write the hi reg value
+	sll	a0, a0, MIPS_TLB_PID_SHIFT	# put PID in right spot
+	mtc0	a0, MIPS_COP_0_TLB_HI		# Write the hi reg value
 	j	ra
 	nop
 END(mips1_SetPID)
@@ -839,26 +839,26 @@ END(mips1_SetPID)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBFlush)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t0, MACH_COP_0_TLB_HI		# Save the PID
-	li	t1, MACH_CACHED_MEMORY_ADDR	# invalid address
-	mtc0	t1, MACH_COP_0_TLB_HI		# Mark entry high as invalid
-	mtc0	zero, MACH_COP_0_TLB_LOW	# Zero out low entry.
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t0, MIPS_COP_0_TLB_HI		# Save the PID
+	li	t1, MIPS_KSEG0_START		# invalid address
+	mtc0	t1, MIPS_COP_0_TLB_HI		# Mark entry high as invalid
+	mtc0	zero, MIPS_COP_0_TLB_LOW	# Zero out low entry.
 /*
  * Align the starting value (t1) and the upper bound (t2).
  */
-	li	t1, VMMACH_FIRST_RAND_ENTRY << VMMACH_TLB_INDEX_SHIFT
-	li	t2, VMMACH_NUM_TLB_ENTRIES << VMMACH_TLB_INDEX_SHIFT
+	li	t1, MIPS1_TLB_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
+	li	t2, MIPS1_TLB_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT
 1:
-	mtc0	t1, MACH_COP_0_TLB_INDEX	# Set the index register.
-	addu	t1, t1, 1 << VMMACH_TLB_INDEX_SHIFT	# Increment index.
+	mtc0	t1, MIPS_COP_0_TLB_INDEX	# Set the index register.
+	addu	t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT	# Increment index.
 	bne	t1, t2, 1b
 	tlbwi					# Write the TLB entry.
 
-	mtc0	t0, MACH_COP_0_TLB_HI		# Restore the PID
+	mtc0	t0, MIPS_COP_0_TLB_HI		# Restore the PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBFlush)
 
 #if 0
@@ -880,35 +880,35 @@ END(mips1_TLBFlush)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBFlushPID)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t0, MACH_COP_0_TLB_HI		# Save the current PID
-	sll	a0, a0, VMMACH_TLB_PID_SHIFT	# Align the pid to flush.
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t0, MIPS_COP_0_TLB_HI		# Save the current PID
+	sll	a0, a0, MIPS_TLB_PID_SHIFT	# Align the pid to flush.
 /*
  * Align the starting value (t1) and the upper bound (t2).
  */
-	li	t1, VMMACH_FIRST_RAND_ENTRY << VMMACH_TLB_INDEX_SHIFT
-	li	t2, VMMACH_NUM_TLB_ENTRIES << VMMACH_TLB_INDEX_SHIFT
-	mtc0	t1, MACH_COP_0_TLB_INDEX	# Set the index register
+	li	t1, MIPS1_FIRST_RAND_ENTRY << MIPS1_TLB_INDEX_SHIFT
+	li	t2, MIPS1_NUM_TLB_ENTRIES << MIPS1_TLB_INDEX_SHIFT
+	mtc0	t1, MIPS_COP_0_TLB_INDEX	# Set the index register
 1:
-	addu	t1, t1, 1 << VMMACH_TLB_INDEX_SHIFT	# Increment index.
+	addu	t1, t1, 1 << MIPS1_TLB_INDEX_SHIFT	# Increment index.
 	tlbr					# Read from the TLB
-	mfc0	t4, MACH_COP_0_TLB_HI		# Fetch the hi register.
+	mfc0	t4, MIPS_COP_0_TLB_HI		# Fetch the hi register.
 	nop
-	and	t4, t4, VMMACH_TLB_PID		# compare PIDs
+	and	t4, t4, MIPS1_TLB_PID		# compare PIDs
 	bne	t4, a0, 2f
-	li	v0, MACH_CACHED_MEMORY_ADDR	# invalid address
-	mtc0	v0, MACH_COP_0_TLB_HI		# Mark entry high as invalid
-	mtc0	zero, MACH_COP_0_TLB_LOW	# Zero out low entry.
+	li	v0, MIPS_KSEG0_START	# invalid address
+	mtc0	v0, MIPS_COP_0_TLB_HI		# Mark entry high as invalid
+	mtc0	zero, MIPS_COP_0_TLB_LOW	# Zero out low entry.
 	nop
 	tlbwi					# Write the entry.
 2:
 	bne	t1, t2, 1b
-	mtc0	t1, MACH_COP_0_TLB_INDEX	# Set the index register
+	mtc0	t1, MIPS_COP_0_TLB_INDEX	# Set the index register
 
-	mtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	mtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBFlushPID)
 #endif
 
@@ -930,25 +930,25 @@ END(mips1_TLBFlushPID)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBFlushAddr)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t0, MACH_COP_0_TLB_HI		# Get current PID
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t0, MIPS_COP_0_TLB_HI		# Get current PID
 	nop
 
-	mtc0	a0, MACH_COP_0_TLB_HI		# look for addr & PID
+	mtc0	a0, MIPS_COP_0_TLB_HI		# look for addr & PID
 	nop
 	tlbp					# Probe for the entry.
-	mfc0	v0, MACH_COP_0_TLB_INDEX	# See what we got
-	li	t1, MACH_CACHED_MEMORY_ADDR	# Load invalid entry.
+	mfc0	v0, MIPS_COP_0_TLB_INDEX	# See what we got
+	li	t1, MIPS_KSEG0_START	# Load invalid entry.
 	bltz	v0, 1f				# index < 0 => !found
-	mtc0	t1, MACH_COP_0_TLB_HI		# Mark entry high as invalid
-	mtc0	zero, MACH_COP_0_TLB_LOW	# Zero out low entry.
+	mtc0	t1, MIPS_COP_0_TLB_HI		# Mark entry high as invalid
+	mtc0	zero, MIPS_COP_0_TLB_LOW	# Zero out low entry.
 	nop
 	tlbwi
 1:
-	mtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	mtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBFlushAddr)
 
 /*--------------------------------------------------------------------------
@@ -969,27 +969,27 @@ END(mips1_TLBFlushAddr)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBUpdate)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t0, MACH_COP_0_TLB_HI		# Save current PID
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t0, MIPS_COP_0_TLB_HI		# Save current PID
 	nop					# 2 cycles before intr disabled
-	mtc0	a0, MACH_COP_0_TLB_HI		# init high reg.
+	mtc0	a0, MIPS_COP_0_TLB_HI		# init high reg.
 	nop
 	tlbp					# Probe for the entry.
-	mfc0	v0, MACH_COP_0_TLB_INDEX	# See what we got
-	mtc0	a1, MACH_COP_0_TLB_LOW		# init low reg.
+	mfc0	v0, MIPS_COP_0_TLB_INDEX	# See what we got
+	mtc0	a1, MIPS_COP_0_TLB_LOW		# init low reg.
 	bltz	v0, 1f				# index < 0 => !found
-	sra	v0, v0, VMMACH_TLB_INDEX_SHIFT	# convert index to regular num
+	sra	v0, v0, MIPS1_TLB_INDEX_SHIFT	# convert index to regular num
 	b	2f
 	tlbwi					# update slot found
 1:
-	mtc0	a0, MACH_COP_0_TLB_HI		# init high reg.
+	mtc0	a0, MIPS_COP_0_TLB_HI		# init high reg.
 	nop
 	tlbwr					# enter into a random slot
 2:
-	mtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	mtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBUpdate)
 
 /*--------------------------------------------------------------------------
@@ -1013,27 +1013,27 @@ END(mips1_TLBUpdate)
 	.comm	tlbhi, 4
 	.comm	tlblo, 4
 LEAF(mips1_TLBFind)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t0, MACH_COP_0_TLB_HI		# Get current PID
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t0, MIPS_COP_0_TLB_HI		# Get current PID
 	nop
-	mtc0	a0, MACH_COP_0_TLB_HI		# Set up entry high.
+	mtc0	a0, MIPS_COP_0_TLB_HI		# Set up entry high.
 	nop
 	tlbp					# Probe for the entry.
-	mfc0	v0, MACH_COP_0_TLB_INDEX	# See what we got
+	mfc0	v0, MIPS_COP_0_TLB_INDEX	# See what we got
 	nop
 	bltz	v0, 1f				# not found
 	nop
 	tlbr					# read TLB
-	mfc0	t1, MACH_COP_0_TLB_HI		# See what we got
-	mfc0	t2, MACH_COP_0_TLB_LOW		# See what we got
+	mfc0	t1, MIPS_COP_0_TLB_HI		# See what we got
+	mfc0	t2, MIPS_COP_0_TLB_LOW		# See what we got
 	sw	t1, tlbhi
 	sw	t2, tlblo
-	srl	v0, v0, VMMACH_TLB_INDEX_SHIFT	# convert index to regular num
+	srl	v0, v0, MIPS1_TLB_INDEX_SHIFT	# convert index to regular num
 1:
-	mtc0	t0, MACH_COP_0_TLB_HI		# Restore current PID
+	mtc0	t0, MIPS_COP_0_TLB_HI		# Restore current PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBFind)
 
 /*--------------------------------------------------------------------------
@@ -1054,22 +1054,22 @@ END(mips1_TLBFind)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBRead)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t0, MACH_COP_0_TLB_HI		# Get current PID
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t0, MIPS_COP_0_TLB_HI		# Get current PID
 
-	sll	a0, a0, VMMACH_TLB_INDEX_SHIFT
-	mtc0	a0, MACH_COP_0_TLB_INDEX	# Set the index register
+	sll	a0, a0, MIPS1_TLB_INDEX_SHIFT
+	mtc0	a0, MIPS_COP_0_TLB_INDEX	# Set the index register
 	nop
 	tlbr					# Read from the TLB
-	mfc0	t3, MACH_COP_0_TLB_HI		# fetch the hi entry
-	mfc0	t4, MACH_COP_0_TLB_LOW		# fetch the low entry
+	mfc0	t3, MIPS_COP_0_TLB_HI		# fetch the hi entry
+	mfc0	t4, MIPS_COP_0_TLB_LOW		# fetch the low entry
 	sw	t3, tlbhi
 	sw	t4, tlblo
 
-	mtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	mtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips1_TLBRead)
 
 /*--------------------------------------------------------------------------
@@ -1087,11 +1087,11 @@ END(mips1_TLBRead)
  *--------------------------------------------------------------------------
  */
 LEAF(mips1_TLBGetPID)
-	mfc0	v0, MACH_COP_0_TLB_HI		# get PID
+	mfc0	v0, MIPS_COP_0_TLB_HI		# get PID
 	nop
-	and	v0, v0, VMMACH_TLB_PID		# mask off PID
+	and	v0, v0, MIPS1_TLB_PID		# mask off PID
 	j	ra
-	srl	v0, v0, VMMACH_TLB_PID_SHIFT	# put PID in right spot
+	srl	v0, v0, MIPS_TLB_PID_SHIFT	# put PID in right spot
 END(mips1_TLBGetPID)
 
 
@@ -1123,9 +1123,9 @@ NON_LEAF(mips1_ConfigCache, STAND_FRAME_SIZE, ra)
 	subu	sp, sp, STAND_FRAME_SIZE
 	sw	ra, STAND_RA_OFFSET(sp)		# Save return address.
 	.mask	0x80000000, (STAND_RA_OFFSET - STAND_FRAME_SIZE)
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts.
 	la	v0, 1f
-	or	v0, MACH_UNCACHED_MEMORY_ADDR	# Run uncached.
+	or	v0, MIPS_KSEG1_START	# Run uncached.
 	j	v0
 	nop
 1:
@@ -1141,15 +1141,15 @@ NON_LEAF(mips1_ConfigCache, STAND_FRAME_SIZE, ra)
 	nop
 	nop
 	nop
-	li	v0, MACH_SR_SWAP_CACHES		# Swap caches
-	mtc0	v0, MACH_COP_0_STATUS_REG
+	li	v0, MIPS_SR_SWAP_CACHES		# Swap caches
+	mtc0	v0, MIPS_COP_0_STATUS_REG
 	nop					# Insure caches stable
 	nop
 	nop
 	nop
 	jal	_C_LABEL(mips1_SizeCache)	# Get the size of the i-cache.
 	nop
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Swap back caches and enable.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Swap back caches and enable.
 	nop
 	nop
 	nop
@@ -1180,20 +1180,20 @@ END(mips1_ConfigCache)
  *----------------------------------------------------------------------------
  */
 LEAF(mips1_SizeCache)
-	mfc0	t0, MACH_COP_0_STATUS_REG	# Save the current status reg.
+	mfc0	t0, MIPS_COP_0_STATUS_REG	# Save the current status reg.
 	nop
-	or	v0, t0, MACH_SR_ISOL_CACHES	# Isolate the caches.
+	or	v0, t0, MIPS_SR_ISOL_CACHES	# Isolate the caches.
 	nop					# Make sure no stores in pipe
-	mtc0	v0, MACH_COP_0_STATUS_REG
+	mtc0	v0, MIPS_COP_0_STATUS_REG
 	nop					# Make sure isolated
 	nop
 	nop
 /*
  * Clear cache size boundaries.
  */
-	li	v0, MACH_MIN_CACHE_SIZE
-	li	v1, MACH_CACHED_MEMORY_ADDR
-	li	t2, MACH_MAX_CACHE_SIZE
+	li	v0, MIPS_MIN_CACHE_SIZE
+	li	v1, MIPS_KSEG0_START
+	li	t2, MIPS_MAX_CACHE_SIZE
 1:
 	addu	t1, v0, v1			# Compute address to clear
 	sw	zero, 0(t1)			# Clear cache memory
@@ -1202,7 +1202,7 @@ LEAF(mips1_SizeCache)
 
 	li	v0, -1
 	sw	v0, 0(v1)			# Store marker in cache
-	li	v0, MACH_MIN_CACHE_SIZE
+	li	v0, MIPS_MIN_CACHE_SIZE
 2:
 	addu	t1, v0, v1			# Compute address
 	lw	t3, 0(t1)			# Look for marker
@@ -1214,7 +1214,7 @@ LEAF(mips1_SizeCache)
 
 	move	v0, zero			# must be no cache
 3:
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 	nop					# Make sure unisolated
 	nop
 	nop
@@ -1240,21 +1240,21 @@ END(mips1_SizeCache)
 LEAF(mips1_FlushCache)
 	lw	t1, _C_LABEL(machInstCacheSize)	# Must load before isolating
 	lw	t2, _C_LABEL(machDataCacheSize)	# Must load before isolating
-	mfc0	t3, MACH_COP_0_STATUS_REG 	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts.
+	mfc0	t3, MIPS_COP_0_STATUS_REG 	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts.
 	la	v0, 1f
-	or	v0, MACH_UNCACHED_MEMORY_ADDR	# Run uncached.
+	or	v0, MIPS_KSEG1_START	# Run uncached.
 	j	v0
 	nop
 /*
  * Flush the instruction cache.
  */
 1:
-	li	v0, MACH_SR_ISOL_CACHES | MACH_SR_SWAP_CACHES
-	mtc0	v0, MACH_COP_0_STATUS_REG	# Isolate and swap caches.
-	li	t0, MACH_UNCACHED_MEMORY_ADDR
+	li	v0, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES
+	mtc0	v0, MIPS_COP_0_STATUS_REG	# Isolate and swap caches.
+	li	t0, MIPS_KSEG1_START
 	subu	t0, t0, t1
-	li	t1, MACH_UNCACHED_MEMORY_ADDR
+	li	t1, MIPS_KSEG1_START
 	la	v0, 1f				# Run cached
 	j	v0
 	nop
@@ -1264,16 +1264,16 @@ LEAF(mips1_FlushCache)
 	sb	zero, -4(t0)
 
 	la	v0, 1f
-	or	v0, MACH_UNCACHED_MEMORY_ADDR
+	or	v0, MIPS_KSEG1_START
 	j	v0				# Run uncached
 	nop
 /*
  * Flush the data cache.
  */
 1:
-	li	v0, MACH_SR_ISOL_CACHES
-	mtc0	v0, MACH_COP_0_STATUS_REG	# Isolate and swap back caches
-	li	t0, MACH_UNCACHED_MEMORY_ADDR
+	li	v0, MIPS_SR_ISOL_CACHES
+	mtc0	v0, MIPS_COP_0_STATUS_REG	# Isolate and swap back caches
+	li	t0, MIPS_KSEG1_START
 	subu	t0, t0, t2
 	la	v0, 1f
 	j	v0				# Back to cached mode
@@ -1287,7 +1287,7 @@ LEAF(mips1_FlushCache)
 	nop					#   out of pipe.
 	nop
 	nop
-	mtc0	t3, MACH_COP_0_STATUS_REG	# Restore status reg.
+	mtc0	t3, MIPS_COP_0_STATUS_REG	# Restore status reg.
 	nop					# Insure cache unisolated.
 	nop
 	nop
@@ -1315,17 +1315,17 @@ END(mips1_FlushCache)
  *----------------------------------------------------------------------------
  */
 LEAF(mips1_FlushICache)
-	mfc0	t0, MACH_COP_0_STATUS_REG	# Save SR
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts.
+	mfc0	t0, MIPS_COP_0_STATUS_REG	# Save SR
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts.
 
 	la	v1, 1f
-	or	v1, MACH_UNCACHED_MEMORY_ADDR	# Run uncached.
+	or	v1, MIPS_KSEG1_START	# Run uncached.
 	j	v1
 	nop
 1:
 	bc0f	1b				# make sure stores are complete
-	li	v1, MACH_SR_ISOL_CACHES | MACH_SR_SWAP_CACHES
-	mtc0	v1, MACH_COP_0_STATUS_REG
+	li	v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES
+	mtc0	v1, MIPS_COP_0_STATUS_REG
 	nop
 	addu	a1, a1, a0			# compute ending address
 1:
@@ -1333,7 +1333,7 @@ LEAF(mips1_FlushICache)
 	bne	a0, a1, 1b
 	sb	zero, -4(a0)
 
-	mtc0	t0, MACH_COP_0_STATUS_REG	# enable interrupts
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# enable interrupts
 	j	ra				# return and run cached
 	nop
 END(mips1_FlushICache)
@@ -1357,16 +1357,16 @@ END(mips1_FlushICache)
  *----------------------------------------------------------------------------
  */
 LEAF(mips1_FlushDCache)
-	mfc0	t0, MACH_COP_0_STATUS_REG	# Save SR
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts.
+	mfc0	t0, MIPS_COP_0_STATUS_REG	# Save SR
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts.
 	nop
 1:
 	bc0f	1b				# make sure stores are complete
 # BUG: should drain write buffer.
 # The insn above does not work on some all DEC machines, or all variants
 # of the mips architecture.
-	li	v1, MACH_SR_ISOL_CACHES
-	mtc0	v1, MACH_COP_0_STATUS_REG
+	li	v1, MIPS_SR_ISOL_CACHES
+	mtc0	v1, MIPS_COP_0_STATUS_REG
 	nop
 	addu	t1, a1, a0			# compute ending address
 1:
@@ -1383,7 +1383,7 @@ LEAF(mips1_FlushDCache)
 
 	nop					# drain pipeline
 	nop
-	mtc0	t0, MACH_COP_0_STATUS_REG	# enable interrupts
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# enable interrupts
 	nop
 	j	ra				# return and run cached
 	nop
diff --git a/sys/arch/pmax/pmax/locore_r4000.S b/sys/arch/pmax/pmax/locore_r4000.S
index 27d82c538d8..22e937b3e3d 100644
--- a/sys/arch/pmax/pmax/locore_r4000.S
+++ b/sys/arch/pmax/pmax/locore_r4000.S
@@ -31,13 +31,13 @@ _C_LABEL(mips3_TLBMiss):
 	.globl	_C_LABEL(MachTLBMiss)
 _C_LABEL(MachTLBMiss):
 	.set	noat
-	dmfc0	k0, MACH_COP_0_BAD_VADDR	# get the virtual address
+	dmfc0	k0, MIPS_COP_0_BAD_VADDR	# get the virtual address
 	lw	k1, UADDR+U_PCB_SEGTAB		# get the current segment table
 	bltz	k0, 1f				# kernel address space ->
 	srl	k0, k0, SEGSHIFT - 2		# compute segment table index
 	andi	k0, k0, 0x7fc			# PMAP_SEGTABSIZ-1
 	addu	k1, k1, k0
-	dmfc0	k0, MACH_COP_0_BAD_VADDR	# get the virtual address
+	dmfc0	k0, MIPS_COP_0_BAD_VADDR	# get the virtual address
 	lw	k1, 0(k1)			# get pointer to segment map
 	srl	k0, k0, PGSHIFT - 2		# compute segment map index
 	andi	k0, k0, ((NPTEPG/2) - 1) << 3
@@ -47,10 +47,10 @@ _C_LABEL(MachTLBMiss):
 	lw	k1, 4(k1)
 	dsll	k0, k0, 34
 	dsrl	k0, k0, 34
-	dmtc0	k0, MACH_COP_0_TLB_LO0
+	dmtc0	k0, MIPS_COP_0_TLB_LO0
 	dsll	k1, k1, 34
 	dsrl	k1, k1, 34
-	dmtc0	k1, MACH_COP_0_TLB_LO1
+	dmtc0	k1, MIPS_COP_0_TLB_LO1
 	nop
 	tlbwr					# update TLB
 	nop
@@ -91,8 +91,8 @@ _C_LABEL(mips3_exception):
  * Find out what mode we came from and jump to the proper handler.
  */
 	.set	noat
-	mfc0	k0, MACH_COP_0_STATUS_REG	# Get the status register
-	mfc0	k1, MACH_COP_0_CAUSE_REG	# Get the cause register value.
+	mfc0	k0, MIPS_COP_0_STATUS_REG	# Get the status register
+	mfc0	k1, MIPS_COP_0_CAUSE_REG	# Get the cause register value.
 	and	k0, k0, MIPS_4K_SR_KSU_USER	# test for user mode
 						# sneaky but the bits are
 						# with us........
@@ -134,9 +134,9 @@ _C_LABEL(mips3_exceptionEnd):
  */
 mips3_SlowFault:
 	.set	noat
-	mfc0	k0, MACH_COP_0_STATUS_REG
+	mfc0	k0, MIPS_COP_0_STATUS_REG
 	nop
-	and	k0, k0, MACH_SR_KSU_USER
+	and	k0, k0, MIPS_SR_KSU_USER
 	bne	k0, zero, mips3_UserGenException
 	nop
 	.set	at
@@ -215,25 +215,25 @@ NNON_LEAF(mips3_KernGenException, KERN_EXC_FRAME_SIZE, ra)
 	sw	a2, KERN_REG_OFFSET + 20(sp)
 	sw	a3, KERN_REG_OFFSET + 24(sp)
 	sw	t0, KERN_REG_OFFSET + 28(sp)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t1, KERN_REG_OFFSET + 32(sp)
 	sw	t2, KERN_REG_OFFSET + 36(sp)
 	sw	t3, KERN_REG_OFFSET + 40(sp)
 	sw	t4, KERN_REG_OFFSET + 44(sp)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	t5, KERN_REG_OFFSET + 48(sp)
 	sw	t6, KERN_REG_OFFSET + 52(sp)
 	sw	t7, KERN_REG_OFFSET + 56(sp)
 	sw	t8, KERN_REG_OFFSET + 60(sp)
-	mfc0	a2, MACH_COP_0_BAD_VADDR	# Third arg is the fault addr.
+	mfc0	a2, MIPS_COP_0_BAD_VADDR	# Third arg is the fault addr.
 	sw	t9, KERN_REG_OFFSET + 64(sp)
 	sw	ra, KERN_REG_OFFSET + 68(sp)
 	sw	v0, KERN_MULT_LO_OFFSET(sp)
 	sw	v1, KERN_MULT_HI_OFFSET(sp)
-	mfc0	a3, MACH_COP_0_EXC_PC		# Fourth arg is the pc.
+	mfc0	a3, MIPS_COP_0_EXC_PC		# Fourth arg is the pc.
 	sw	a0, KERN_SR_OFFSET(sp)
 
-	mtc0	zero,MACH_COP_0_STATUS_REG	# Set kernel no error level
+	mtc0	zero,MIPS_COP_0_STATUS_REG	# Set kernel no error level
 /*
  * Call the exception handler.
  */
@@ -243,14 +243,14 @@ NNON_LEAF(mips3_KernGenException, KERN_EXC_FRAME_SIZE, ra)
  * Restore registers and return from the exception.
  * v0 contains the return address.
  */
-	mtc0	zero,MACH_COP_0_STATUS_REG	# Make shure int disabled
+	mtc0	zero,MIPS_COP_0_STATUS_REG	# Make shure int disabled
 	lw	a0, KERN_SR_OFFSET(sp)
 	lw	t0, KERN_MULT_LO_OFFSET(sp)
 	lw	t1, KERN_MULT_HI_OFFSET(sp)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# Restore the SR, disable intrs
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# Restore the SR, disable intrs
 	mtlo	t0
 	mthi	t1
-	dmtc0	v0, MACH_COP_0_EXC_PC		# set return address
+	dmtc0	v0, MIPS_COP_0_EXC_PC		# set return address
 
 	lw	AT, KERN_REG_OFFSET + 0(sp)
 	lw	v0, KERN_REG_OFFSET + 4(sp)
@@ -296,22 +296,22 @@ NNON_LEAF(mips3_UserGenException, STAND_FRAME_SIZE, ra)
 	sw	t2, UADDR+U_PCB_REGS+(T2 * 4)
 	sw	t3, UADDR+U_PCB_REGS+(T3 * 4)
 	sw	t4, UADDR+U_PCB_REGS+(T4 * 4)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t5, UADDR+U_PCB_REGS+(T5 * 4)
 	sw	t6, UADDR+U_PCB_REGS+(T6 * 4)
 	sw	t7, UADDR+U_PCB_REGS+(T7 * 4)
 	sw	s0, UADDR+U_PCB_REGS+(S0 * 4)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	s1, UADDR+U_PCB_REGS+(S1 * 4)
 	sw	s2, UADDR+U_PCB_REGS+(S2 * 4)
 	sw	s3, UADDR+U_PCB_REGS+(S3 * 4)
 	sw	s4, UADDR+U_PCB_REGS+(S4 * 4)
-	mfc0	a2, MACH_COP_0_BAD_VADDR	# Third arg is the fault addr
+	mfc0	a2, MIPS_COP_0_BAD_VADDR	# Third arg is the fault addr
 	sw	s5, UADDR+U_PCB_REGS+(S5 * 4)
 	sw	s6, UADDR+U_PCB_REGS+(S6 * 4)
 	sw	s7, UADDR+U_PCB_REGS+(S7 * 4)
 	sw	t8, UADDR+U_PCB_REGS+(T8 * 4)
-	mfc0	a3, MACH_COP_0_EXC_PC		# Fourth arg is the pc.
+	mfc0	a3, MIPS_COP_0_EXC_PC		# Fourth arg is the pc.
 	sw	t9, UADDR+U_PCB_REGS+(T9 * 4)
 	sw	gp, UADDR+U_PCB_REGS+(GP * 4)
 	sw	sp, UADDR+U_PCB_REGS+(SP * 4)
@@ -326,34 +326,34 @@ NNON_LEAF(mips3_UserGenException, STAND_FRAME_SIZE, ra)
 	sw	a3, STAND_RA_OFFSET(sp)		# for debugging
 	.set	at
 # Turn off fpu and enter kernel mode
-	and	t0, a0, ~(MACH_SR_COP_1_BIT | MACH_SR_EXL | MACH_SR_KSU_MASK | MIPS_SR_INT_IE)
+	and	t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_KSU_MASK | MIPS_SR_INT_IE)
 	.set	noat
 /*
  * Call the exception handler.
  */
 	jal	trap
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 /*
  * Restore user registers and return.
  * First disable interrupts and set exeption level.
  */
-	mtc0	zero, MACH_COP_0_STATUS_REG	# disable int
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# disable int
 	nop
 	nop
 	nop
-	li	v0, MACH_SR_EXL
-	mtc0	v0, MACH_COP_0_STATUS_REG	# set exeption level
+	li	v0, MIPS_SR_EXL
+	mtc0	v0, MIPS_COP_0_STATUS_REG	# set exeption level
 
 	lw	a0, UADDR+U_PCB_REGS+(SR * 4)
 	lw	t0, UADDR+U_PCB_REGS+(MULLO * 4)
 	lw	t1, UADDR+U_PCB_REGS+(MULHI * 4)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# still exeption level
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# still exeption level
 	mtlo	t0
 	mthi	t1
 	lw	a0, UADDR+U_PCB_REGS+(PC * 4)
 	lw	AT, UADDR+U_PCB_REGS+(AST * 4)
 	lw	v0, UADDR+U_PCB_REGS+(V0 * 4)
-	dmtc0	a0, MACH_COP_0_EXC_PC		# set return address
+	dmtc0	a0, MIPS_COP_0_EXC_PC		# set return address
 
 	RESTORE_USER_REGS(UADDR)	/* XXX FIXME */
 
@@ -396,24 +396,24 @@ NNON_LEAF(mips3_KernIntr, KINTR_FRAME_SIZE, ra)
 	sw	a2, KINTR_REG_OFFSET + 20(sp)
 	sw	a3, KINTR_REG_OFFSET + 24(sp)
 	sw	t0, KINTR_REG_OFFSET + 28(sp)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t1, KINTR_REG_OFFSET + 32(sp)
 	sw	t2, KINTR_REG_OFFSET + 36(sp)
 	sw	t3, KINTR_REG_OFFSET + 40(sp)
 	sw	t4, KINTR_REG_OFFSET + 44(sp)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	t5, KINTR_REG_OFFSET + 48(sp)
 	sw	t6, KINTR_REG_OFFSET + 52(sp)
 	sw	t7, KINTR_REG_OFFSET + 56(sp)
 	sw	t8, KINTR_REG_OFFSET + 60(sp)
-	mfc0	a2, MACH_COP_0_EXC_PC		# Third arg is the pc.
+	mfc0	a2, MIPS_COP_0_EXC_PC		# Third arg is the pc.
 	sw	t9, KINTR_REG_OFFSET + 64(sp)
 	sw	ra, KINTR_REG_OFFSET + 68(sp)
 	sw	v0, KINTR_MULT_LO_OFFSET(sp)
 	sw	v1, KINTR_MULT_HI_OFFSET(sp)
 	sw	a0, KINTR_SR_OFFSET(sp)
 
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Reset exl, trap possible.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Reset exl, trap possible.
 /*
  * Call the interrupt handler.
  */
@@ -422,17 +422,17 @@ NNON_LEAF(mips3_KernIntr, KINTR_FRAME_SIZE, ra)
 /*
  * Restore registers and return from the interrupt.
  */
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupt
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupt
 	lw	a0, KINTR_SR_OFFSET(sp)
 	lw	t0, KINTR_MULT_LO_OFFSET(sp)
 	lw	t1, KINTR_MULT_HI_OFFSET(sp)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# Restore the SR, disable intrs
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# Restore the SR, disable intrs
 	mtlo	t0
 	mthi	t1
 	lw	a0, STAND_RA_OFFSET(sp)
 	lw	AT, KINTR_REG_OFFSET + 0(sp)
 	lw	v0, KINTR_REG_OFFSET + 4(sp)
-	dmtc0	a0, MACH_COP_0_EXC_PC		# set return address
+	dmtc0	a0, MIPS_COP_0_EXC_PC		# set return address
 
 	RESTORE_KERN_REGISTERS(KINTR_REG_OFFSET)
 
@@ -478,17 +478,17 @@ NNON_LEAF(mips3_UserIntr, STAND_FRAME_SIZE, ra)
 	sw	a2, UADDR+U_PCB_REGS+(A2 * 4)
 	sw	a3, UADDR+U_PCB_REGS+(A3 * 4)
 	sw	t0, UADDR+U_PCB_REGS+(T0 * 4)
-	mfc0	a0, MACH_COP_0_STATUS_REG	# First arg is the status reg.
+	mfc0	a0, MIPS_COP_0_STATUS_REG	# First arg is the status reg.
 	sw	t1, UADDR+U_PCB_REGS+(T1 * 4)
 	sw	t2, UADDR+U_PCB_REGS+(T2 * 4)
 	sw	t3, UADDR+U_PCB_REGS+(T3 * 4)
 	sw	t4, UADDR+U_PCB_REGS+(T4 * 4)
-	mfc0	a1, MACH_COP_0_CAUSE_REG	# Second arg is the cause reg.
+	mfc0	a1, MIPS_COP_0_CAUSE_REG	# Second arg is the cause reg.
 	sw	t5, UADDR+U_PCB_REGS+(T5 * 4)
 	sw	t6, UADDR+U_PCB_REGS+(T6 * 4)
 	sw	t7, UADDR+U_PCB_REGS+(T7 * 4)
 	sw	t8, UADDR+U_PCB_REGS+(T8 * 4)
-	mfc0	a2, MACH_COP_0_EXC_PC		# Third arg is the pc.
+	mfc0	a2, MIPS_COP_0_EXC_PC		# Third arg is the pc.
 	sw	t9, UADDR+U_PCB_REGS+(T9 * 4)
 	sw	gp, UADDR+U_PCB_REGS+(GP * 4)
 	sw	sp, UADDR+U_PCB_REGS+(SP * 4)
@@ -501,9 +501,9 @@ NNON_LEAF(mips3_UserIntr, STAND_FRAME_SIZE, ra)
 	la	gp, _gp				# switch to kernel GP
 # Turn off fpu and enter kernel mode
 	.set	at
-	and	t0, a0, ~(MACH_SR_COP_1_BIT | MACH_SR_EXL | MIPS_SR_INT_IE | MACH_SR_KSU_MASK)
+	and	t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_INT_IE | MIPS_SR_KSU_MASK)
 	.set	noat
-	mtc0	t0, MACH_COP_0_STATUS_REG
+	mtc0	t0, MIPS_COP_0_STATUS_REG
 /*
  * Call the interrupt handler.
  */
@@ -512,23 +512,23 @@ NNON_LEAF(mips3_UserIntr, STAND_FRAME_SIZE, ra)
 /*
  * Restore registers and return from the interrupt.
  */
-	mtc0	zero, MACH_COP_0_STATUS_REG
+	mtc0	zero, MIPS_COP_0_STATUS_REG
 	nop
 	nop
 	nop
-	li	v0, MACH_SR_EXL
-	mtc0	v0, MACH_COP_0_STATUS_REG	# set exeption level bit.
+	li	v0, MIPS_SR_EXL
+	mtc0	v0, MIPS_COP_0_STATUS_REG	# set exeption level bit.
 
 	lw	a0, UADDR+U_PCB_REGS+(SR * 4)
 	lw	v0, astpending			# any pending interrupts?
-	mtc0	a0, MACH_COP_0_STATUS_REG	# Restore the SR, disable intrs
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# Restore the SR, disable intrs
 	bne	v0, zero, 1f			# dont restore, call softintr
 	lw	t0, UADDR+U_PCB_REGS+(MULLO * 4)
 	lw	t1, UADDR+U_PCB_REGS+(MULHI * 4)
 	lw	a0, UADDR+U_PCB_REGS+(PC * 4)
 	lw	AT, UADDR+U_PCB_REGS+(AST * 4)
 	lw	v0, UADDR+U_PCB_REGS+(V0 * 4)
-	dmtc0	a0, MACH_COP_0_EXC_PC		# set return address
+	dmtc0	a0, MIPS_COP_0_EXC_PC		# set return address
 	lw	v1, UADDR+U_PCB_REGS+(V1 * 4)
 	lw	a0, UADDR+U_PCB_REGS+(A0 * 4)
 	lw	a1, UADDR+U_PCB_REGS+(A1 * 4)
@@ -564,32 +564,32 @@ NNON_LEAF(mips3_UserIntr, STAND_FRAME_SIZE, ra)
 	sw	s6, UADDR+U_PCB_REGS+(S6 * 4)
 	sw	s7, UADDR+U_PCB_REGS+(S7 * 4)
 	sw	s8, UADDR+U_PCB_REGS+(S8 * 4)
-	li	t0, MACH_HARD_INT_MASK | MIPS_SR_INT_IE
+	li	t0, MIPS_HARD_INT_MASK | MIPS_SR_INT_IE
 /*
  * Call the software interrupt handler.
  */
 	jal	softintr
-	mtc0	t0, MACH_COP_0_STATUS_REG	# enable interrupts (spl0)
+	mtc0	t0, MIPS_COP_0_STATUS_REG	# enable interrupts (spl0)
 /*
  * Restore user registers and return. NOTE: interrupts are enabled.
  */
-	mtc0	zero, MACH_COP_0_STATUS_REG
+	mtc0	zero, MIPS_COP_0_STATUS_REG
 	nop
 	nop
 	nop
-	li	v0, MACH_SR_EXL
-	mtc0	v0, MACH_COP_0_STATUS_REG	# set exeption level bit.
+	li	v0, MIPS_SR_EXL
+	mtc0	v0, MIPS_COP_0_STATUS_REG	# set exeption level bit.
 
 	lw	a0, UADDR+U_PCB_REGS+(SR * 4)
 	lw	t0, UADDR+U_PCB_REGS+(MULLO * 4)
 	lw	t1, UADDR+U_PCB_REGS+(MULHI * 4)
-	mtc0	a0, MACH_COP_0_STATUS_REG	# this should disable interrupts
+	mtc0	a0, MIPS_COP_0_STATUS_REG	# this should disable interrupts
 	mtlo	t0
 	mthi	t1
 	lw	a0, UADDR+U_PCB_REGS+(PC * 4)
 	lw	AT, UADDR+U_PCB_REGS+(AST * 4)
 	lw	v0, UADDR+U_PCB_REGS+(V0 * 4)
-	dmtc0	a0, MACH_COP_0_EXC_PC		# set return address
+	dmtc0	a0, MIPS_COP_0_EXC_PC		# set return address
 
 	/*XXX*/
 	RESTORE_USER_REGS(UADDR)	/* XXX FIXME */
@@ -633,7 +633,7 @@ END(mips3_UserIntr)
  */
 NLEAF(mips3_TLBInvalidException)
 	.set	noat
-	dmfc0	k0, MACH_COP_0_BAD_VADDR	# get the fault address
+	dmfc0	k0, MIPS_COP_0_BAD_VADDR	# get the fault address
 	li	k1, VM_MIN_KERNEL_ADDRESS	# compute index
 	subu	k0, k0, k1
 	lw	k1, Sysmapsize			# index within range?
@@ -649,7 +649,7 @@ NLEAF(mips3_TLBInvalidException)
 	bne	k0, zero, KernTLBIOdd
 	nop
 
-	mfc0	k0, MACH_COP_0_TLB_INDEX
+	mfc0	k0, MIPS_COP_0_TLB_INDEX
 	nop
 	bltz	k0, sys_stk_chk
 	sltiu	k0, k0, 8
@@ -659,13 +659,13 @@ NLEAF(mips3_TLBInvalidException)
 
 	dsll	k0, k0, 34			# get rid of "wired" bit
 	dsrl	k0, k0, 34
-	dmtc0	k0, MACH_COP_0_TLB_LO0		# load PTE entry
+	dmtc0	k0, MIPS_COP_0_TLB_LO0		# load PTE entry
 	and	k0, k0, PG_V			# check for valid entry
 	beq	k0, zero, mips3_KernGenException	# PTE invalid
 	lw	k0, 4(k1)			# get odd PTE entry
 	dsll	k0, k0, 34
 	dsrl	k0, k0, 34
-	dmtc0	k0, MACH_COP_0_TLB_LO1		# load PTE entry
+	dmtc0	k0, MIPS_COP_0_TLB_LO1		# load PTE entry
 	nop
 	tlbwi					# write TLB
 	nop
@@ -676,7 +676,7 @@ NLEAF(mips3_TLBInvalidException)
 	eret
 
 KernTLBIOdd:
-	mfc0	k0, MACH_COP_0_TLB_INDEX
+	mfc0	k0, MIPS_COP_0_TLB_INDEX
 	nop
 	bltz	k0, sys_stk_chk
 	sltiu	k0, k0, 8
@@ -686,13 +686,13 @@ KernTLBIOdd:
 
 	dsll	k0, k0, 34			# get rid of wired bit
 	dsrl	k0, k0, 34
-	dmtc0	k0, MACH_COP_0_TLB_LO1		# save PTE entry
+	dmtc0	k0, MIPS_COP_0_TLB_LO1		# save PTE entry
 	and	k0, k0, PG_V			# check for valid entry
 	beq	k0, zero, mips3_KernGenException	# PTE invalid
 	lw	k0, -4(k1)			# get even PTE entry
 	dsll	k0, k0, 34
 	dsrl	k0, k0, 34
-	dmtc0	k0, MACH_COP_0_TLB_LO0		# save PTE entry
+	dmtc0	k0, MIPS_COP_0_TLB_LO0		# save PTE entry
 	nop
 	tlbwi					# update TLB
 	nop
@@ -721,7 +721,7 @@ END(mips3_TLBInvalidException)
  */
 NLEAF(mips3_TLBMissException)
 	.set	noat
-	dmfc0	k0, MACH_COP_0_BAD_VADDR	# get the fault address
+	dmfc0	k0, MIPS_COP_0_BAD_VADDR	# get the fault address
 	li	k1, VM_MIN_KERNEL_ADDRESS	# compute index
 	subu	k0, k0, k1
 	lw	k1, Sysmapsize			# index within range?
@@ -736,10 +736,10 @@ NLEAF(mips3_TLBMissException)
 	lw	k1, 4(k1)			# get odd PTE entry
 	dsll	k0, k0, 34			# get rid of "wired" bit
 	dsrl	k0, k0, 34
-	dmtc0	k0, MACH_COP_0_TLB_LO0		# load PTE entry
+	dmtc0	k0, MIPS_COP_0_TLB_LO0		# load PTE entry
 	dsll	k1, k1, 34
 	dsrl	k1, k1, 34
-	dmtc0	k1, MACH_COP_0_TLB_LO1		# load PTE entry
+	dmtc0	k1, MIPS_COP_0_TLB_LO1		# load PTE entry
 	nop
 	tlbwr					# write TLB
 	nop
@@ -759,14 +759,14 @@ sys_stk_chk:
 	sw	sp, 24(a0)
 	move	sp, a0
 	la	a0, 1f
-	mfc0	a2, MACH_COP_0_STATUS_REG
-	mfc0	a3, MACH_COP_0_CAUSE_REG
-	dmfc0	a1, MACH_COP_0_EXC_PC
+	mfc0	a2, MIPS_COP_0_STATUS_REG
+	mfc0	a3, MIPS_COP_0_CAUSE_REG
+	dmfc0	a1, MIPS_COP_0_EXC_PC
 	sw	a2, 16(sp)
 	sw	a3, 20(sp)
 	move	a2, ra
 	jal	printf
-	dmfc0	a3, MACH_COP_0_BAD_VADDR
+	dmfc0	a3, MIPS_COP_0_BAD_VADDR
 	.data
 1:
 	.asciiz	"ktlbmiss: PC %x RA %x ADR %x\nSR %x CR %x SP %x\n"
@@ -806,20 +806,20 @@ _C_LABEL(mips3_exceptionentry_end):
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBWriteIndexedVPS)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
 	nop
 	lw	a2, 8(a1)
 	lw	a3, 12(a1)
-	dmfc0	t0, MACH_COP_0_TLB_HI		# Save the current PID.
+	dmfc0	t0, MIPS_COP_0_TLB_HI		# Save the current PID.
 
-	dmtc0	a2, MACH_COP_0_TLB_LO0		# Set up entry low0.
-	dmtc0	a3, MACH_COP_0_TLB_LO1		# Set up entry low1.
+	dmtc0	a2, MIPS_COP_0_TLB_LO0		# Set up entry low0.
+	dmtc0	a3, MIPS_COP_0_TLB_LO1		# Set up entry low1.
 	lw	a2, 0(a1)
 	lw	a3, 4(a1)
-	mtc0	a0, MACH_COP_0_TLB_INDEX	# Set the index.
-	dmtc0	a2, MACH_COP_0_TLB_PG_MASK	# Set up entry mask.
-	dmtc0	a3, MACH_COP_0_TLB_HI		# Set up entry high.
+	mtc0	a0, MIPS_COP_0_TLB_INDEX	# Set the index.
+	dmtc0	a2, MIPS_COP_0_TLB_PG_MASK	# Set up entry mask.
+	dmtc0	a3, MIPS_COP_0_TLB_HI		# Set up entry high.
 	nop
 	tlbwi					# Write the TLB
 	nop
@@ -827,11 +827,11 @@ LEAF(mips3_TLBWriteIndexedVPS)
 	nop					# Delay for effect
 	nop
 
-	dmtc0	t0, MACH_COP_0_TLB_HI		# Restore the PID.
+	dmtc0	t0, MIPS_COP_0_TLB_HI		# Restore the PID.
 	nop
-	dmtc0	zero, MACH_COP_0_TLB_PG_MASK	# Default mask value.
+	dmtc0	zero, MIPS_COP_0_TLB_PG_MASK	# Default mask value.
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips3_TLBWriteIndexedVPS)
 
 /*--------------------------------------------------------------------------
@@ -855,20 +855,20 @@ END(mips3_TLBWriteIndexedVPS)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBWriteIndexed)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
 	nop
 	lw	a2, 8(a1)
 	lw	a3, 12(a1)
-	dmfc0	t0, MACH_COP_0_TLB_HI		# Save the current PID.
+	dmfc0	t0, MIPS_COP_0_TLB_HI		# Save the current PID.
 
-	dmtc0	a2, MACH_COP_0_TLB_LO0		# Set up entry low0.
-	dmtc0	a3, MACH_COP_0_TLB_LO1		# Set up entry low1.
+	dmtc0	a2, MIPS_COP_0_TLB_LO0		# Set up entry low0.
+	dmtc0	a3, MIPS_COP_0_TLB_LO1		# Set up entry low1.
 	lw	a2, 0(a1)
 	lw	a3, 4(a1)
-	mtc0	a0, MACH_COP_0_TLB_INDEX	# Set the index.
-	dmtc0	a2, MACH_COP_0_TLB_PG_MASK	# Set up entry mask.
-	dmtc0	a3, MACH_COP_0_TLB_HI		# Set up entry high.
+	mtc0	a0, MIPS_COP_0_TLB_INDEX	# Set the index.
+	dmtc0	a2, MIPS_COP_0_TLB_PG_MASK	# Set up entry mask.
+	dmtc0	a3, MIPS_COP_0_TLB_HI		# Set up entry high.
 	nop
 	tlbwi					# Write the TLB
 	nop
@@ -876,11 +876,11 @@ LEAF(mips3_TLBWriteIndexed)
 	nop					# Delay for effect
 	nop
 
-	dmtc0	t0, MACH_COP_0_TLB_HI		# Restore the PID.
+	dmtc0	t0, MIPS_COP_0_TLB_HI		# Restore the PID.
 	nop
-	dmtc0	zero, MACH_COP_0_TLB_PG_MASK	# Default mask value.
+	dmtc0	zero, MIPS_COP_0_TLB_PG_MASK	# Default mask value.
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips3_TLBWriteIndexed)
 
 /*--------------------------------------------------------------------------
@@ -901,7 +901,7 @@ END(mips3_TLBWriteIndexed)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_SetPID)
-	dmtc0	a0, MACH_COP_0_TLB_HI		# Write the hi reg value
+	dmtc0	a0, MIPS_COP_0_TLB_HI		# Write the hi reg value
 	j	ra
 	nop
 END(mips3_SetPID)
@@ -924,7 +924,7 @@ END(mips3_SetPID)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_SetWIRED)
-	mtc0	a0, MACH_COP_0_TLB_WIRED
+	mtc0	a0, MIPS_COP_0_TLB_WIRED
 	j	ra
 	nop
 END(mips3_SetWIRED)
@@ -946,7 +946,7 @@ END(mips3_SetWIRED)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_GetWIRED)
-	mfc0	v0, MACH_COP_0_TLB_WIRED
+	mfc0	v0, MIPS_COP_0_TLB_WIRED
 	j	ra
 	nop
 END(mips3_GetWIRED)
@@ -969,22 +969,22 @@ END(mips3_GetWIRED)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBFlush)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
-	mfc0	t1, MACH_COP_0_TLB_WIRED
-	li	t2, VMMACH_NUM_TLB_ENTRIES
-	li	v0, MACH_CACHED_MEMORY_ADDR	# invalid address
-	dmfc0	t0, MACH_COP_0_TLB_HI		# Save the PID
-
-	dmtc0	v0, MACH_COP_0_TLB_HI		# Mark entry high as invalid
-	dmtc0	zero, MACH_COP_0_TLB_LO0	# Zero out low entry0.
-	dmtc0	zero, MACH_COP_0_TLB_LO1	# Zero out low entry1.
-	mtc0	zero, MACH_COP_0_TLB_PG_MASK	# Zero out mask entry.
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	t1, MIPS_COP_0_TLB_WIRED
+	li	t2, MIPS3_TLB_NUM_TLB_ENTRIES
+	li	v0, MIPS_KSEG0_START	# invalid address
+	dmfc0	t0, MIPS_COP_0_TLB_HI		# Save the PID
+
+	dmtc0	v0, MIPS_COP_0_TLB_HI		# Mark entry high as invalid
+	dmtc0	zero, MIPS_COP_0_TLB_LO0	# Zero out low entry0.
+	dmtc0	zero, MIPS_COP_0_TLB_LO1	# Zero out low entry1.
+	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# Zero out mask entry.
 /*
  * Align the starting value (t1) and the upper bound (t2).
  */
 1:
-	mtc0	t1, MACH_COP_0_TLB_INDEX	# Set the index register.
+	mtc0	t1, MIPS_COP_0_TLB_INDEX	# Set the index register.
 	addu	t1, t1, 1			# Increment index.
 	tlbwi					# Write the TLB entry.
 	nop
@@ -992,9 +992,9 @@ LEAF(mips3_TLBFlush)
 	bne	t1, t2, 1b
 	nop
 
-	dmtc0	t0, MACH_COP_0_TLB_HI		# Restore the PID
+	dmtc0	t0, MIPS_COP_0_TLB_HI		# Restore the PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips3_TLBFlush)
 
 
@@ -1016,13 +1016,13 @@ END(mips3_TLBFlush)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBFlushAddr)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
 	nop
 	li	v0, (PG_HVPN | PG_ASID)
 	and	a0, a0, v0			# Make shure valid hi value.
-	dmfc0	t0, MACH_COP_0_TLB_HI		# Get current PID
-	dmtc0	a0, MACH_COP_0_TLB_HI		# look for addr & PID
+	dmfc0	t0, MIPS_COP_0_TLB_HI		# Get current PID
+	dmtc0	a0, MIPS_COP_0_TLB_HI		# look for addr & PID
 	nop
 	nop
 	nop
@@ -1030,14 +1030,14 @@ LEAF(mips3_TLBFlushAddr)
 	nop
 	nop					# Delay for effect
 	nop
-	mfc0	v0, MACH_COP_0_TLB_INDEX	# See what we got
-	li	t1, MACH_CACHED_MEMORY_ADDR	# Load invalid entry.
+	mfc0	v0, MIPS_COP_0_TLB_INDEX	# See what we got
+	li	t1, MIPS_KSEG0_START	# Load invalid entry.
 	bltz	v0, 1f				# index < 0 => !found
 	nop
-	dmtc0	t1, MACH_COP_0_TLB_HI		# Mark entry high as invalid
+	dmtc0	t1, MIPS_COP_0_TLB_HI		# Mark entry high as invalid
 
-	dmtc0	zero, MACH_COP_0_TLB_LO0	# Zero out low entry.
-	dmtc0	zero, MACH_COP_0_TLB_LO1	# Zero out low entry.
+	dmtc0	zero, MIPS_COP_0_TLB_LO0	# Zero out low entry.
+	dmtc0	zero, MIPS_COP_0_TLB_LO1	# Zero out low entry.
 	nop
 	tlbwi
 	nop
@@ -1045,9 +1045,9 @@ LEAF(mips3_TLBFlushAddr)
 	nop
 	nop
 1:
-	dmtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	dmtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips3_TLBFlushAddr)
 
 /*--------------------------------------------------------------------------
@@ -1068,13 +1068,13 @@ END(mips3_TLBFlushAddr)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBUpdate)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
 	and	t1, a0, 0x1000			# t1 = Even/Odd flag
 	li	v0, (PG_HVPN | PG_ASID)
 	and	a0, a0, v0
-	dmfc0	t0, MACH_COP_0_TLB_HI		# Save current PID
-	dmtc0	a0, MACH_COP_0_TLB_HI		# Init high reg
+	dmfc0	t0, MIPS_COP_0_TLB_HI		# Save current PID
+	dmtc0	a0, MIPS_COP_0_TLB_HI		# Init high reg
 	and	a2, a1, PG_G			# Copy global bit
 	nop
 	nop
@@ -1082,7 +1082,7 @@ LEAF(mips3_TLBUpdate)
 	dsll	a1, a1, 34
 	dsrl	a1, a1, 34
 	bne	t1, zero, 2f			# Decide even odd
-	mfc0	v0, MACH_COP_0_TLB_INDEX	# See what we got
+	mfc0	v0, MIPS_COP_0_TLB_INDEX	# See what we got
 # EVEN
 	nop
 	bltz	v0, 1f				# index < 0 => !found
@@ -1092,16 +1092,16 @@ LEAF(mips3_TLBUpdate)
 	nop
 	nop
 	nop
-	dmtc0	a1, MACH_COP_0_TLB_LO0		# init low reg0.
+	dmtc0	a1, MIPS_COP_0_TLB_LO0		# init low reg0.
 	nop
 	tlbwi					# update slot found
 	b	4f
 	nop
 1:
-	mtc0	zero, MACH_COP_0_TLB_PG_MASK	# init mask.
-	dmtc0	a0, MACH_COP_0_TLB_HI		# init high reg.
-	dmtc0	a1, MACH_COP_0_TLB_LO0		# init low reg0.
-	dmtc0	a2, MACH_COP_0_TLB_LO1		# init low reg1.
+	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# init mask.
+	dmtc0	a0, MIPS_COP_0_TLB_HI		# init high reg.
+	dmtc0	a1, MIPS_COP_0_TLB_LO0		# init low reg0.
+	dmtc0	a2, MIPS_COP_0_TLB_LO1		# init low reg1.
 	nop
 	tlbwr					# enter into a random slot
 	b	4f
@@ -1116,16 +1116,16 @@ LEAF(mips3_TLBUpdate)
 	nop
 	nop
 	nop
-	dmtc0	a1, MACH_COP_0_TLB_LO1		# init low reg1.
+	dmtc0	a1, MIPS_COP_0_TLB_LO1		# init low reg1.
 	nop
 	tlbwi					# update slot found
 	b	4f
 	nop
 3:
-	mtc0	zero, MACH_COP_0_TLB_PG_MASK	# init mask.
-	dmtc0	a0, MACH_COP_0_TLB_HI		# init high reg.
-	dmtc0	a2, MACH_COP_0_TLB_LO0		# init low reg0.
-	dmtc0	a1, MACH_COP_0_TLB_LO1		# init low reg1.
+	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# init mask.
+	dmtc0	a0, MIPS_COP_0_TLB_HI		# init high reg.
+	dmtc0	a2, MIPS_COP_0_TLB_LO0		# init low reg0.
+	dmtc0	a1, MIPS_COP_0_TLB_LO1		# init low reg1.
 	nop
 	tlbwr					# enter into a random slot
 
@@ -1134,9 +1134,9 @@ LEAF(mips3_TLBUpdate)
 	nop					# uses the tlb.
 	nop
 	nop
-	dmtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	dmtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	j	ra
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 END(mips3_TLBUpdate)
 
 /*--------------------------------------------------------------------------
@@ -1158,28 +1158,28 @@ END(mips3_TLBUpdate)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBReadVPS)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
 	nop
 	nop
 	nop
-	dmfc0	t0, MACH_COP_0_TLB_HI		# Get current PID
+	dmfc0	t0, MIPS_COP_0_TLB_HI		# Get current PID
 
-	mtc0	a0, MACH_COP_0_TLB_INDEX	# Set the index register
+	mtc0	a0, MIPS_COP_0_TLB_INDEX	# Set the index register
 	nop
 	tlbr					# Read from the TLB
 	nop
 	nop
 	nop
-	mfc0	t2, MACH_COP_0_TLB_PG_MASK	# fetch the hi entry
-	dmfc0	t3, MACH_COP_0_TLB_HI		# fetch the hi entry
-	dmfc0	t4, MACH_COP_0_TLB_LO0		# See what we got
-	dmfc0	t5, MACH_COP_0_TLB_LO1		# See what we got
-	dmtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	mfc0	t2, MIPS_COP_0_TLB_PG_MASK	# fetch the hi entry
+	dmfc0	t3, MIPS_COP_0_TLB_HI		# fetch the hi entry
+	dmfc0	t4, MIPS_COP_0_TLB_LO0		# See what we got
+	dmfc0	t5, MIPS_COP_0_TLB_LO1		# See what we got
+	dmtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	nop
 	nop
 	nop					# wait for PID active
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 	sw	t2, 0(a1)
 	sw	t3, 4(a1)
 	sw	t4, 8(a1)
@@ -1206,28 +1206,28 @@ END(mips3_TLBReadVPS)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBRead)
-	mfc0	v1, MACH_COP_0_STATUS_REG	# Save the status register.
-	mtc0	zero, MACH_COP_0_STATUS_REG	# Disable interrupts
+	mfc0	v1, MIPS_COP_0_STATUS_REG	# Save the status register.
+	mtc0	zero, MIPS_COP_0_STATUS_REG	# Disable interrupts
 	nop
 	nop
 	nop
-	dmfc0	t0, MACH_COP_0_TLB_HI		# Get current PID
+	dmfc0	t0, MIPS_COP_0_TLB_HI		# Get current PID
 
-	mtc0	a0, MACH_COP_0_TLB_INDEX	# Set the index register
+	mtc0	a0, MIPS_COP_0_TLB_INDEX	# Set the index register
 	nop
 	tlbr					# Read from the TLB
 	nop
 	nop
 	nop
-	mfc0	t2, MACH_COP_0_TLB_PG_MASK	# fetch the hi entry
-	dmfc0	t3, MACH_COP_0_TLB_HI		# fetch the hi entry
-	dmfc0	t4, MACH_COP_0_TLB_LO0		# See what we got
-	dmfc0	t5, MACH_COP_0_TLB_LO1		# See what we got
-	dmtc0	t0, MACH_COP_0_TLB_HI		# restore PID
+	mfc0	t2, MIPS_COP_0_TLB_PG_MASK	# fetch the hi entry
+	dmfc0	t3, MIPS_COP_0_TLB_HI		# fetch the hi entry
+	dmfc0	t4, MIPS_COP_0_TLB_LO0		# See what we got
+	dmfc0	t5, MIPS_COP_0_TLB_LO1		# See what we got
+	dmtc0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	nop
 	nop
 	nop					# wait for PID active
-	mtc0	v1, MACH_COP_0_STATUS_REG	# Restore the status register
+	mtc0	v1, MIPS_COP_0_STATUS_REG	# Restore the status register
 	sw	t2, 0(a1)
 	sw	t3, 4(a1)
 	sw	t4, 8(a1)
@@ -1250,9 +1250,9 @@ END(mips3_TLBRead)
  *--------------------------------------------------------------------------
  */
 LEAF(mips3_TLBGetPID)
-	dmfc0	v0, MACH_COP_0_TLB_HI		# get PID
+	dmfc0	v0, MIPS_COP_0_TLB_HI		# get PID
 	j	ra
-	and	v0, v0, VMMACH_TLB_PID		# mask off PID
+	and	v0, v0, MIPS3_TLB_PID		# mask off PID
 END(mips3_TLBGetPID)
 
 
@@ -1283,7 +1283,7 @@ END(mips3_TLBGetPID)
  *----------------------------------------------------------------------------
  */
 LEAF(mips3_ConfigCache)
-	mfc0	v0, MACH_COP_0_CONFIG		# Get configuration register
+	mfc0	v0, MIPS_COP_0_CONFIG		# Get configuration register
 	nop
 	srl	t1, v0, 9			# Get I cache size.
 	and	t1, 3
@@ -1334,7 +1334,7 @@ LEAF(mips3_FlushCache)
 /*
  * Flush the instruction cache.
  */
-	li	t0, MACH_CACHED_MEMORY_ADDR
+	li	t0, MIPS_KSEG0_START
 	addu	t1, t0, t1		# End address
 	subu	t1, t1, 128
 1:
@@ -1352,7 +1352,7 @@ LEAF(mips3_FlushCache)
 /*
  * Flush the data cache.
  */
-	li	t0, MACH_CACHED_MEMORY_ADDR
+	li	t0, MIPS_KSEG0_START
 	addu	t1, t0, t2		# End address
 	subu	t1, t1, 128
 1:
diff --git a/sys/arch/pmax/pmax/machdep.c b/sys/arch/pmax/pmax/machdep.c
index 59b704eb671..a8e03ca072c 100644
--- a/sys/arch/pmax/pmax/machdep.c
+++ b/sys/arch/pmax/pmax/machdep.c
@@ -347,10 +347,10 @@ mach_init(argc, argv, code, cv)
 	start = v;
 	curproc->p_addr = proc0paddr = (struct user *)v;
 	curproc->p_md.md_regs = proc0paddr->u_pcb.pcb_regs;
-	firstaddr = MACH_CACHED_TO_PHYS(v);
+	firstaddr = MIPS_KSEG0_TO_PHYS(v);
 	for (i = 0; i < UPAGES; i++) {
 		MachTLBWriteIndexed(i,
-			(UADDR + (i << PGSHIFT)) | (1 << VMMACH_TLB_PID_SHIFT),
+			(UADDR + (i << PGSHIFT)) | (1 << MIPS_TLB_PID_SHIFT),
 			curproc->p_md.md_upte[i] = firstaddr | PG_V | PG_M);
 		firstaddr += NBPG;
 	}
@@ -398,7 +398,7 @@ mach_init(argc, argv, code, cv)
 	 * Initialize physmem_boardmax; assume no SIMM-bank limits.
 	 * Adjst later in model-specific code if necessary.
 	 */
-	physmem_boardmax = MACH_MAX_MEM_ADDR;
+	physmem_boardmax = MIPS_MAX_MEM_ADDR;
 
 	/* check what model platform we are running on */
 	pmax_boardtype = ((i >> 16) & 0xff);
@@ -419,7 +419,7 @@ mach_init(argc, argv, code, cv)
 		Mach_splclock = Mach_spl3;
 		Mach_splstatclock = Mach_spl3;
 		Mach_clock_addr = (volatile struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(KN01_SYS_CLOCK);
+			MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
 		strcpy(cpu_model, "3100");
 		break;
 #endif /* DS3100 */
@@ -440,7 +440,7 @@ mach_init(argc, argv, code, cv)
 		Mach_splclock = Mach_spl3;
 		Mach_splstatclock = Mach_spl3;
 		Mach_clock_addr = (volatile struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(KN01_SYS_CLOCK);
+			MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK);
 		strcpy(cpu_model, "5100");
 		break;
 #endif /* DS5100 */
@@ -449,10 +449,10 @@ mach_init(argc, argv, code, cv)
 	case DS_3MAX:	/* DS5000/200 3max */
 		{
 		volatile int *csr_addr =
-			(volatile int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
+			(volatile int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
 
 		Mach_reset_addr =
-		    (unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR);
+		    (unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR);
 		/* clear any memory errors from new-config probes */
 		*Mach_reset_addr = 0;
 
@@ -472,7 +472,7 @@ mach_init(argc, argv, code, cv)
 		Mach_splclock = Mach_spl1;
 		Mach_splstatclock = Mach_spl1;
 		Mach_clock_addr = (volatile struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(KN02_SYS_CLOCK);
+			MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK);
 
 		}
 		strcpy(cpu_model, "5000/200");
@@ -486,7 +486,7 @@ mach_init(argc, argv, code, cv)
 		tc_slot_phys_base[0] = KMIN_PHYS_TC_0_START;
 		tc_slot_phys_base[1] = KMIN_PHYS_TC_1_START;
 		tc_slot_phys_base[2] = KMIN_PHYS_TC_2_START;
-		ioasic_base = MACH_PHYS_TO_UNCACHED(KMIN_SYS_ASIC);
+		ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC);
 		mips_hardware_intr = kmin_intr;
 		tc_enable_interrupt = kmin_enable_intr;
 		kmin_tc3_imask = (KMIN_INTR_CLOCK | KMIN_INTR_PSWARN |
@@ -505,7 +505,7 @@ mach_init(argc, argv, code, cv)
 		Mach_splclock = splhigh;
 		Mach_splstatclock = splhigh;
 		Mach_clock_addr = (volatile struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(KMIN_SYS_CLOCK);
+			MIPS_PHYS_TO_KSEG1(KMIN_SYS_CLOCK);
 
 
 		/*
@@ -516,7 +516,7 @@ mach_init(argc, argv, code, cv)
 
 		/* clear any memory errors from probes */
 		Mach_reset_addr =
-		    (u_int*)MACH_PHYS_TO_UNCACHED(KMIN_REG_TIMEOUT);
+		    (u_int*)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT);
 		(*Mach_reset_addr) = 0;
 
 		strcpy(cpu_model, "5000/1xx");
@@ -529,10 +529,10 @@ mach_init(argc, argv, code, cv)
 		 * XXX Do MAXINEs lose the same way?
 		 */
 		physmem_boardmax = KMIN_PHYS_MEMORY_END + 1;
-		if ((*(int*)(MACH_PHYS_TO_UNCACHED(KMIN_REG_MSR)) &
+		if ((*(int*)(MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) &
 		     KMIN_MSR_SIZE_16Mb) == 0)
 			physmem_boardmax = physmem_boardmax >> 2;
-		physmem_boardmax = MACH_PHYS_TO_UNCACHED(physmem_boardmax);
+		physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax);
 
 		break;
 #endif /* ds5000_100 */
@@ -543,7 +543,7 @@ mach_init(argc, argv, code, cv)
 		tc_min_slot = XINE_TC_MIN;
 		tc_slot_phys_base[0] = XINE_PHYS_TC_0_START;
 		tc_slot_phys_base[1] = XINE_PHYS_TC_1_START;
-		ioasic_base = MACH_PHYS_TO_UNCACHED(XINE_SYS_ASIC);
+		ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC);
 		mips_hardware_intr = xine_intr;
 		tc_enable_interrupt = xine_enable_intr;
 		Mach_splbio = Mach_spl3;
@@ -553,7 +553,7 @@ mach_init(argc, argv, code, cv)
 		Mach_splclock = Mach_spl1;
 		Mach_splstatclock = Mach_spl1;
 		Mach_clock_addr = (volatile struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(XINE_SYS_CLOCK);
+			MIPS_PHYS_TO_KSEG1(XINE_SYS_CLOCK);
 
 		/*
 		 * Initialize interrupts.
@@ -562,7 +562,7 @@ mach_init(argc, argv, code, cv)
 		*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
 		/* clear any memory errors from probes */
 		Mach_reset_addr =
-		    (u_int*)MACH_PHYS_TO_UNCACHED(XINE_REG_TIMEOUT);
+		    (u_int*)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT);
 		(*Mach_reset_addr) = 0;
 		strcpy(cpu_model, "5000/25");
 		break;
@@ -575,11 +575,11 @@ mach_init(argc, argv, code, cv)
 		tc_slot_phys_base[0] = KN03_PHYS_TC_0_START;
 		tc_slot_phys_base[1] = KN03_PHYS_TC_1_START;
 		tc_slot_phys_base[2] = KN03_PHYS_TC_2_START;
-		ioasic_base = MACH_PHYS_TO_UNCACHED(KN03_SYS_ASIC);
+		ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC);
 		mips_hardware_intr = kn03_intr;
 		tc_enable_interrupt = kn03_enable_intr;
 		Mach_reset_addr =
-		    (u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR);
+		    (u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
 		*Mach_reset_addr = 0;
 
 		/*
@@ -593,7 +593,7 @@ mach_init(argc, argv, code, cv)
 		Mach_splclock = Mach_spl1;
 		Mach_splstatclock = Mach_spl1;
 		Mach_clock_addr = (volatile struct chiptime *)
-			MACH_PHYS_TO_UNCACHED(KN03_SYS_CLOCK);
+			MIPS_PHYS_TO_KSEG1(KN03_SYS_CLOCK);
 
 		asic_init(0);
 		/*
@@ -623,7 +623,7 @@ mach_init(argc, argv, code, cv)
 	 * Be careful to save and restore the original contents for msgbuf.
 	 */
 	physmem = btoc((vm_offset_t)v - KERNBASE);
-	cp = (char *)MACH_PHYS_TO_UNCACHED(physmem << PGSHIFT);	
+	cp = (char *)MIPS_PHYS_TO_KSEG1(physmem << PGSHIFT);	
 	while (cp < (char *)physmem_boardmax) {
 	  	int j;
 		if (badaddr(cp, 4))
@@ -678,7 +678,7 @@ mach_init(argc, argv, code, cv)
 	 * Initialize error message buffer (at end of core).
 	 */
 	maxmem -= btoc(sizeof (struct msgbuf));
-	msgbufp = (struct msgbuf *)(MACH_PHYS_TO_CACHED(maxmem << PGSHIFT));
+	msgbufp = (struct msgbuf *)(MIPS_PHYS_TO_KSEG0(maxmem << PGSHIFT));
 	msgbufmapped = 1;
 
 	/*
@@ -1462,7 +1462,7 @@ initcpu()
 		*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
 		break;
 	case DS_3MAX:
-		*(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CHKSYN) = 0;
+		*(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
 		wbflush();
 		break;
 	default:
@@ -1589,7 +1589,7 @@ kn02_enable_intr(slotno, handler, sc, on)
 	int on;
 {
 	register volatile int *p_csr =
-		(volatile int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
+		(volatile int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
 	int csr;
 	int s;
 
@@ -1650,11 +1650,11 @@ kmin_enable_intr(slotno, handler, sc, on)
 	switch (slotno) {
 		/* slots 0-2 don't interrupt through the IOASIC. */
 	case 0:
-		mask = MACH_INT_MASK_0;	break;
+		mask = MIPS_INT_MASK_0;	break;
 	case 1:
-		mask = MACH_INT_MASK_1; break;
+		mask = MIPS_INT_MASK_1; break;
 	case 2:
-		mask = MACH_INT_MASK_2; break;
+		mask = MIPS_INT_MASK_2; break;
 
 	case KMIN_SCSI_SLOT:
 		mask = (KMIN_INTR_SCSI | KMIN_INTR_SCSI_PTR_LOAD |
@@ -1804,7 +1804,7 @@ kn03_tc_reset()
 	 * Reset interrupts, clear any errors from newconf probes
 	 */
 	*(u_int *)IOASIC_REG_INTR(ioasic_base) = 0;
-	*(unsigned *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR) = 0;
+	*(unsigned *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
 }
 
 
diff --git a/sys/arch/pmax/pmax/mem.c b/sys/arch/pmax/pmax/mem.c
index 56b21b555ee..b228ee4c8eb 100644
--- a/sys/arch/pmax/pmax/mem.c
+++ b/sys/arch/pmax/pmax/mem.c
@@ -111,7 +111,7 @@ mmrw(dev, uio, flags)
 			c = iov->iov_len;
 			if (v + c > ctob(physmem))
 				return (EFAULT);
-			v += MACH_CACHED_MEMORY_ADDR;
+			v += MIPS_KSEG0_START;
 			error = uiomove((caddr_t)v, c, uio);
 			continue;
 
@@ -119,11 +119,11 @@ mmrw(dev, uio, flags)
 		case 1:
 			v = uio->uio_offset;
 			c = min(iov->iov_len, MAXPHYS);
-			if (v < MACH_CACHED_MEMORY_ADDR)
+			if (v < MIPS_KSEG0_START)
 				return (EFAULT);
-			if (v + c > MACH_PHYS_TO_CACHED(avail_end +
+			if (v + c > MIPS_PHYS_TO_KSEG0(avail_end +
 							sizeof (struct msgbuf)) &&
-			    (v < MACH_KSEG2_ADDR ||
+			    (v < MIPS_KSEG2_START ||
 			    !kernacc((caddr_t)v, c,
 			    uio->uio_rw == UIO_READ ? B_READ : B_WRITE)))
 				return (EFAULT);
diff --git a/sys/arch/pmax/pmax/mips_machdep.c b/sys/arch/pmax/pmax/mips_machdep.c
index 5d6d3823fa3..8cc3efa2692 100644
--- a/sys/arch/pmax/pmax/mips_machdep.c
+++ b/sys/arch/pmax/pmax/mips_machdep.c
@@ -65,9 +65,9 @@ mips1_vector_init()
 	 */
 	if (mips1_UTLBMissEnd - mips1_UTLBMiss > 0x80)
 		panic("startup: UTLB code too large");
-	bcopy(mips1_UTLBMiss, (char *)MACH_UTLB_MISS_EXC_VEC,
+	bcopy(mips1_UTLBMiss, (char *)MIPS_UTLB_MISS_EXC_VEC,
 		mips1_UTLBMissEnd - mips1_UTLBMiss);
-	bcopy(mips1_exception, (char *)MACH_GEN_EXC_VEC,
+	bcopy(mips1_exception, (char *)MIPS1_GEN_EXC_VEC,
 	      mips1_exceptionEnd - mips1_exception);
 
 	/*
@@ -125,10 +125,10 @@ mips3_vector_init()
 	 */
 	if (mips3_TLBMissEnd - mips3_TLBMiss > 0x80)
 		panic("startup: UTLB code too large");
-	bcopy(mips3_TLBMiss, (char *)MACH_UTLB_MISS_EXC_VEC,
+	bcopy(mips3_TLBMiss, (char *)MIPS_UTLB_MISS_EXC_VEC,
 	      mips3_TLBMissEnd - mips3_TLBMiss);
 
-	bcopy(mips3_exception, (char *)MACH_GEN_EXC_VEC,
+	bcopy(mips3_exception, (char *)MIPS_GEN_EXC_VEC,
 	      mips3_exceptionEnd - mips3_exception);
 
 	/*
diff --git a/sys/arch/pmax/pmax/nameglue.h b/sys/arch/pmax/pmax/nameglue.h
index 5ddb31f961b..cbe0d51dcb3 100644
--- a/sys/arch/pmax/pmax/nameglue.h
+++ b/sys/arch/pmax/pmax/nameglue.h
@@ -25,7 +25,7 @@
 /*
  * Map physical addresses to kernel-virtual addresses.
  */
-#define KV(x) ((void *)MACH_PHYS_TO_UNCACHED(x))
+#define KV(x) ((void *)MIPS_PHYS_TO_KSEG1(x))
 
 /*
  * Print debugging messages only if DEBUG defined on a pmax.
diff --git a/sys/arch/pmax/pmax/pmap.c b/sys/arch/pmax/pmax/pmap.c
index 0d2bedaa6e2..efed1719d62 100644
--- a/sys/arch/pmax/pmax/pmap.c
+++ b/sys/arch/pmax/pmax/pmap.c
@@ -205,7 +205,7 @@ pmap_bootstrap(firstaddr)
 	 * phys_start and phys_end but its better to use kseg0 addresses
 	 * rather than kernel virtual addresses mapped through the TLB.
 	 */
-	i = maxmem - mips_btop(MACH_CACHED_TO_PHYS(firstaddr));
+	i = maxmem - mips_btop(MIPS_KSEG0_TO_PHYS(firstaddr));
 	valloc(pv_table, struct pv_entry, i);
 
 	/*
@@ -214,7 +214,7 @@ pmap_bootstrap(firstaddr)
 	firstaddr = mips_round_page(firstaddr);
 	bzero((caddr_t)start, firstaddr - start);
 
-	avail_start = MACH_CACHED_TO_PHYS(firstaddr);
+	avail_start = MIPS_KSEG0_TO_PHYS(firstaddr);
 	avail_end = mips_ptob(maxmem);
 	mem_size = avail_end - avail_start;
 
@@ -248,7 +248,7 @@ pmap_bootstrap_alloc(size)
 	if (vm_page_startup_initialized)
 		panic("pmap_bootstrap_alloc: called after startup initialized");
 
-	val = MACH_PHYS_TO_CACHED(avail_start);
+	val = MIPS_PHYS_TO_KSEG0(avail_start);
 	size = round_page(size);
 	avail_start += size;
 
@@ -343,7 +343,7 @@ pmap_pinit(pmap)
 		mem = vm_page_alloc1();
 		pmap_zero_page(VM_PAGE_TO_PHYS(mem));
 		pmap->pm_segtab = stp = (struct segtab *)
-			MACH_PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem));
+			MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(mem));
 		i = mipspagesperpage * (NBPG / sizeof(struct segtab));
 		s = splimp();
 		while (--i != 0) {
@@ -428,7 +428,7 @@ pmap_release(pmap)
 			if (!pte)
 				continue;
 			vm_page_free1(
-				PHYS_TO_VM_PAGE(MACH_CACHED_TO_PHYS(pte)));
+				PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pte)));
 #ifdef DIAGNOSTIC
 			for (j = 0; j < NPTEPG; j++) {
 				if (pte->pt_entry)
@@ -556,7 +556,7 @@ pmap_remove(pmap, sva, eva)
 			 */
 			if (pmap->pm_tlbgen == tlbpid_gen) {
 				MachTLBFlushAddr(sva | (pmap->pm_tlbpid <<
-					VMMACH_TLB_PID_SHIFT));
+					MIPS_TLB_PID_SHIFT));
 #ifdef DEBUG
 				remove_stats.flushes++;
 #endif
@@ -719,7 +719,7 @@ pmap_protect(pmap, sva, eva, prot)
 			 */
 			if (pmap->pm_tlbgen == tlbpid_gen)
 				MachTLBUpdate(sva | (pmap->pm_tlbpid <<
-					VMMACH_TLB_PID_SHIFT), entry);
+					MIPS_TLB_PID_SHIFT), entry);
 		}
 	}
 }
@@ -786,7 +786,7 @@ pmap_page_cache(pa,mode)
 					pte->pt_entry = entry;
 					if (pv->pv_pmap->pm_tlbgen == tlbpid_gen)
 						MachTLBUpdate(pv->pv_va | (pv->pv_pmap->pm_tlbpid <<
-							VMMACH_TLB_PID_SHIFT), entry);
+							MIPS_TLB_PID_SHIFT), entry);
 				}
 			}
 		}
@@ -978,7 +978,7 @@ pmap_enter(pmap, va, pa, prot, wired)
 	 * NOTE: we only support cache flush for read only text.
 	 */
 	if (prot == (VM_PROT_READ | VM_PROT_EXECUTE))
-		MachFlushICache(MACH_PHYS_TO_CACHED(pa), PAGE_SIZE);
+		MachFlushICache(MIPS_PHYS_TO_KSEG0(pa), PAGE_SIZE);
 
 	if (!pmap->pm_segtab) {
 		/* enter entries into kernel pmap */
@@ -1014,7 +1014,7 @@ pmap_enter(pmap, va, pa, prot, wired)
 		mem = vm_page_alloc1();
 		pmap_zero_page(VM_PAGE_TO_PHYS(mem));
 		pmap_segmap(pmap, va) = pte = (pt_entry_t *)
-			MACH_PHYS_TO_CACHED(VM_PAGE_TO_PHYS(mem));
+			MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(mem));
 	}
 	pte += (va >> PGSHIFT) & (NPTEPG - 1);
 
@@ -1041,7 +1041,7 @@ pmap_enter(pmap, va, pa, prot, wired)
 		pte->pt_entry = npte;
 		if (pmap->pm_tlbgen == tlbpid_gen)
 			MachTLBUpdate(va | (pmap->pm_tlbpid <<
-				VMMACH_TLB_PID_SHIFT), npte);
+				MIPS_TLB_PID_SHIFT), npte);
 		va += NBPG;
 		npte += NBPG;
 		pte++;
@@ -1223,7 +1223,7 @@ pmap_zero_page(phys)
 	if (pmapdebug & PDB_FOLLOW)
 		printf("pmap_zero_page(%lx)\n", phys);
 #endif
-	p = (int *)MACH_PHYS_TO_CACHED(phys);
+	p = (int *)MIPS_PHYS_TO_KSEG0(phys);
 	end = p + PAGE_SIZE / sizeof(int);
 	/* XXX blkclr()? */
 	do {
@@ -1250,8 +1250,8 @@ pmap_copy_page(src, dst)
 	if (pmapdebug & PDB_FOLLOW)
 		printf("pmap_copy_page(%lx, %lx)\n", src, dst);
 #endif
-	s = (int *)MACH_PHYS_TO_CACHED(src);
-	d = (int *)MACH_PHYS_TO_CACHED(dst);
+	s = (int *)MIPS_PHYS_TO_KSEG0(src);
+	d = (int *)MIPS_PHYS_TO_KSEG0(dst);
 	end = s + PAGE_SIZE / sizeof(int);
 	do {
 		tmp0 = s[0];
@@ -1400,7 +1400,7 @@ pmap_alloc_tlbpid(p)
 	pmap = p->p_vmspace->vm_map.pmap;
 	if (pmap->pm_tlbgen != tlbpid_gen) {
 		id = tlbpid_cnt;
-		if (id == VMMACH_NUM_PIDS) {
+		if (id == MIPS_TLB_NUM_PIDS) {
 			MachTLBFlush();
 			/* reserve tlbpid_gen == 0 to alway mean invalid */
 			if (++tlbpid_gen == 0)
diff --git a/sys/arch/pmax/pmax/pmax_trap.c b/sys/arch/pmax/pmax/pmax_trap.c
index 86968c3d611..b33445dfd0c 100644
--- a/sys/arch/pmax/pmax/pmax_trap.c
+++ b/sys/arch/pmax/pmax/pmax_trap.c
@@ -200,7 +200,7 @@ kn01_intr(mask, pc, statusReg, causeReg)
 	extern struct cfdriver dc_cd;
 
 	/* handle clock interrupts ASAP */
-	if (mask & MACH_INT_MASK_3) {
+	if (mask & MIPS_INT_MASK_3) {
 		temp = c->regc;	/* XXX clear interrupt bits */
 		cf.pc = pc;
 		cf.sr = statusReg;
@@ -208,26 +208,26 @@ kn01_intr(mask, pc, statusReg, causeReg)
 		intrcnt[HARDCLOCK]++;
 
 		/* keep clock interrupts enabled when we return */
-		causeReg &= ~MACH_INT_MASK_3;
+		causeReg &= ~MIPS_INT_MASK_3;
 	}
 
 	/* If clock interrupts were enabled, re-enable them ASAP. */
-	splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_3));
+	splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_3));
 
 #if NSII > 0
-	if (mask & MACH_INT_MASK_0) {
+	if (mask & MIPS_INT_MASK_0) {
 		intrcnt[SCSI_INTR]++;
 		siiintr(sii_cd.cd_devs[0]);
 	}
 #endif /* NSII */
 
 #if NLE_PMAX > 0
-	if (mask & MACH_INT_MASK_1) {
+	if (mask & MIPS_INT_MASK_1) {
 		/* 
 		 * tty interrupts were disabled by the splx() call
 		 * that re-enables clock interrupts.  A slip or ppp driver
 		 * manipulating if queues should have called splimp(),
-		 * which would mask out MACH_INT_MASK_1.
+		 * which would mask out MIPS_INT_MASK_1.
 		 */
 		am7990_intr(tc_slot_info[1].sc);
 		intrcnt[LANCE_INTR]++;
@@ -235,18 +235,18 @@ kn01_intr(mask, pc, statusReg, causeReg)
 #endif /* NLE_PMAX */
 
 #if NDC_DS > 0
-	if (mask & MACH_INT_MASK_2) {
+	if (mask & MIPS_INT_MASK_2) {
 		dcintr(dc_cd.cd_devs[0]);
 		intrcnt[SERIAL0_INTR]++;
 	}
 #endif /* NDC_DS */
 
-	if (mask & MACH_INT_MASK_4) {
+	if (mask & MIPS_INT_MASK_4) {
 		pmax_errintr();
 		intrcnt[ERROR_INTR]++;
 	}
-	return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
-		MACH_SR_INT_ENA_CUR);
+	return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
+		MIPS_SR_INT_ENA_CUR);
 }
 #endif	/* DS3100 */
 
@@ -270,8 +270,8 @@ kn02_intr(mask, pc, statusReg, causeReg)
 	static int warned = 0;
 
 	/* handle clock interrupts ASAP */
-	if (mask & MACH_INT_MASK_1) {
-		csr = *(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
+	if (mask & MIPS_INT_MASK_1) {
+		csr = *(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
 		if ((csr & KN02_CSR_PSWARN) && !warned) {
 			warned = 1;
 			printf("WARNING: power supply is overheating!\n");
@@ -287,23 +287,23 @@ kn02_intr(mask, pc, statusReg, causeReg)
 		intrcnt[HARDCLOCK]++;
 
 		/* keep clock interrupts enabled when we return */
-		causeReg &= ~MACH_INT_MASK_1;
+		causeReg &= ~MIPS_INT_MASK_1;
 	}
 
 	/* If clock interrups were enabled, re-enable them ASAP. */
-	splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_1));
+	splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
 
-	if (mask & MACH_INT_MASK_0) {
+	if (mask & MIPS_INT_MASK_0) {
 		static int intr_map[8] = { SLOT0_INTR, SLOT1_INTR, SLOT2_INTR,
 					   /* these two bits reserved */
 					   STRAY_INTR,  STRAY_INTR,
 					   SCSI_INTR, LANCE_INTR,
 					   SERIAL0_INTR };
 
-		csr = *(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR);
+		csr = *(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
 		m = csr & (csr >> KN02_CSR_IOINTEN_SHIFT) & KN02_CSR_IOINT;
 #if 0
-		*(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR) =
+		*(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) =
 			(csr & ~(KN02_CSR_WRESERVED | 0xFF)) |
 			(m << KN02_CSR_IOINTEN_SHIFT);
 #endif
@@ -317,17 +317,17 @@ kn02_intr(mask, pc, statusReg, causeReg)
 				printf("spurious interrupt %d\n", i);
 		}
 #if 0
-		*(unsigned *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CSR) =
+		*(unsigned *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) =
 			csr & ~(KN02_CSR_WRESERVED | 0xFF);
 #endif
 	}
-	if (mask & MACH_INT_MASK_3) {
+	if (mask & MIPS_INT_MASK_3) {
 		intrcnt[ERROR_INTR]++;
 		kn02_errintr();
 	}
 
-	return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
-		MACH_SR_INT_ENA_CUR);
+	return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
+		MIPS_SR_INT_ENA_CUR);
 }
 
 /*
@@ -343,9 +343,9 @@ kmin_intr(mask, pc, statusReg, causeReg)
 	register u_int intr;
 	register volatile struct chiptime *c = Mach_clock_addr;
 	volatile u_int *imaskp =
-		(volatile u_int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_IMSK);
+		(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK);
 	volatile u_int *intrp =
-		(volatile u_int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_INTR);
+		(volatile u_int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_INTR);
 	unsigned int old_mask;
 	struct clockframe cf;
 	int temp;
@@ -355,9 +355,9 @@ kmin_intr(mask, pc, statusReg, causeReg)
 	*imaskp = kmin_tc3_imask |
 		 (KMIN_IM0 & ~(KN03_INTR_TC_0|KN03_INTR_TC_1|KN03_INTR_TC_2));
 
-	if (mask & MACH_INT_MASK_4)
+	if (mask & MIPS_INT_MASK_4)
 		(*callv->_halt)((int *)0, 0);
-	if (mask & MACH_INT_MASK_3) {
+	if (mask & MIPS_INT_MASK_3) {
 		intr = *intrp;
 
 		/* masked interrupts are still observable */
@@ -424,29 +424,29 @@ kmin_intr(mask, pc, statusReg, causeReg)
 			printf("%s\n", "Power supply overheating");
 		}
 	}
-	if ((mask & MACH_INT_MASK_0) && tc_slot_info[0].intr) {
+	if ((mask & MIPS_INT_MASK_0) && tc_slot_info[0].intr) {
 		(*tc_slot_info[0].intr)(tc_slot_info[0].sc);
 		intrcnt[SLOT0_INTR]++;
  	}
 	
-	if ((mask & MACH_INT_MASK_1) && tc_slot_info[1].intr) {
+	if ((mask & MIPS_INT_MASK_1) && tc_slot_info[1].intr) {
 		(*tc_slot_info[1].intr)(tc_slot_info[1].sc);
 		intrcnt[SLOT1_INTR]++;
 	}
-	if ((mask & MACH_INT_MASK_2) && tc_slot_info[2].intr) {
+	if ((mask & MIPS_INT_MASK_2) && tc_slot_info[2].intr) {
 		(*tc_slot_info[2].intr)(tc_slot_info[2].sc);
 		intrcnt[SLOT2_INTR]++;
 	}
 
 #if 0 /*XXX*/
-	if (mask & (MACH_INT_MASK_2|MACH_INT_MASK_1|MACH_INT_MASK_0))
+	if (mask & (MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0))
 		printf("kmin: slot intr, mask 0x%x\n",
 			mask &
-			(MACH_INT_MASK_2|MACH_INT_MASK_1|MACH_INT_MASK_0));
+			(MIPS_INT_MASK_2|MIPS_INT_MASK_1|MIPS_INT_MASK_0));
 #endif
 	
-	return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
-		MACH_SR_INT_ENA_CUR);
+	return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
+		MIPS_SR_INT_ENA_CUR);
 }
 
 /*
@@ -462,9 +462,9 @@ xine_intr(mask, pc, statusReg, causeReg)
 	register u_int intr;
 	register volatile struct chiptime *c = Mach_clock_addr;
 	volatile u_int *imaskp = (volatile u_int *)
-		MACH_PHYS_TO_UNCACHED(XINE_REG_IMSK);
+		MIPS_PHYS_TO_KSEG1(XINE_REG_IMSK);
 	volatile u_int *intrp = (volatile u_int *)
-		MACH_PHYS_TO_UNCACHED(XINE_REG_INTR);
+		MIPS_PHYS_TO_KSEG1(XINE_REG_INTR);
 	u_int old_mask;
 	struct clockframe cf;
 	int temp;
@@ -472,24 +472,24 @@ xine_intr(mask, pc, statusReg, causeReg)
 	old_mask = *imaskp & xine_tc3_imask;
 	*imaskp = xine_tc3_imask;
 
-	if (mask & MACH_INT_MASK_4)
+	if (mask & MIPS_INT_MASK_4)
 		(*callv->_halt)((int *)0, 0);
 
 	/* handle clock interrupts ASAP */
-	if (mask & MACH_INT_MASK_1) {
+	if (mask & MIPS_INT_MASK_1) {
 		temp = c->regc;	/* XXX clear interrupt bits */
 		cf.pc = pc;
 		cf.sr = statusReg;
 		hardclock(&cf);
 		intrcnt[HARDCLOCK]++;
 		/* keep clock interrupts enabled when we return */
-		causeReg &= ~MACH_INT_MASK_1;
+		causeReg &= ~MIPS_INT_MASK_1;
 	}
 
 	/* If clock interrups were enabled, re-enable them ASAP. */
-	splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_1));
+	splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
 
-	if (mask & MACH_INT_MASK_3) {
+	if (mask & MIPS_INT_MASK_3) {
 		intr = *intrp;
 		/* masked interrupts are still observable */
 		intr &= old_mask;
@@ -580,10 +580,10 @@ xine_intr(mask, pc, statusReg, causeReg)
 			intrcnt[LANCE_INTR]++;
 		}
 	}
-	if (mask & MACH_INT_MASK_2)
+	if (mask & MIPS_INT_MASK_2)
 		kn02ba_errintr();
-	return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
-		MACH_SR_INT_ENA_CUR);
+	return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
+		MIPS_SR_INT_ENA_CUR);
 }
 
 #ifdef DS5000_240
@@ -600,9 +600,9 @@ kn03_intr(mask, pc, statusReg, causeReg)
 	register u_int intr;
 	register volatile struct chiptime *c = Mach_clock_addr;
 	volatile u_int *imaskp = (volatile u_int *)
-		MACH_PHYS_TO_UNCACHED(KN03_REG_IMSK);
+		MIPS_PHYS_TO_KSEG1(KN03_REG_IMSK);
 	volatile u_int *intrp = (volatile u_int *)
-		MACH_PHYS_TO_UNCACHED(KN03_REG_INTR);
+		MIPS_PHYS_TO_KSEG1(KN03_REG_INTR);
 	u_int old_mask;
 	struct clockframe cf;
 	int temp;
@@ -612,11 +612,11 @@ kn03_intr(mask, pc, statusReg, causeReg)
 	old_mask = *imaskp & kn03_tc3_imask;
 	*imaskp = kn03_tc3_imask;
 
-	if (mask & MACH_INT_MASK_4)
+	if (mask & MIPS_INT_MASK_4)
 		(*callv->_halt)((int *)0, 0);
 
 	/* handle clock interrupts ASAP */
-	if (mask & MACH_INT_MASK_1) {
+	if (mask & MIPS_INT_MASK_1) {
 		temp = c->regc;	/* XXX clear interrupt bits */
 		cf.pc = pc;
 		cf.sr = statusReg;
@@ -625,11 +625,11 @@ kn03_intr(mask, pc, statusReg, causeReg)
 		intrcnt[HARDCLOCK]++;
 		old_buscycle = latched_cycle_cnt - old_buscycle;
 		/* keep clock interrupts enabled when we return */
-		causeReg &= ~MACH_INT_MASK_1;
+		causeReg &= ~MIPS_INT_MASK_1;
 	}
 
 	/* If clock interrups were enabled, re-enable them ASAP. */
-	splx(MACH_SR_INT_ENA_CUR | (statusReg & MACH_INT_MASK_1));
+	splx(MIPS_SR_INT_ENA_CUR | (statusReg & MIPS_INT_MASK_1));
 
 	/*
 	 * Check for late clock interrupts (allow 10% slop). Be careful
@@ -638,7 +638,7 @@ kn03_intr(mask, pc, statusReg, causeReg)
 	 * ticks to be missed.
 	 */
 #ifdef notdef
-	if ((mask & MACH_INT_MASK_1) && old_buscycle > (tick+49) * 25) {
+	if ((mask & MIPS_INT_MASK_1) && old_buscycle > (tick+49) * 25) {
 		extern int msgbufmapped;
   		if(msgbufmapped && 0)
 			 addlog("kn03: clock intr %d usec late\n",
@@ -650,7 +650,7 @@ kn03_intr(mask, pc, statusReg, causeReg)
 	 * and DMA pointers serviced as soon as possible.
 	 */
 
-	if (mask & MACH_INT_MASK_0) {
+	if (mask & MIPS_INT_MASK_0) {
 		intr = *intrp;
 		/* masked interrupts are still observable */
 		intr &= old_mask;
@@ -750,10 +750,10 @@ kn03_intr(mask, pc, statusReg, causeReg)
 			printf("%s\n", "Power supply overheating");
 		}
 	}
-	if (mask & MACH_INT_MASK_3)
+	if (mask & MIPS_INT_MASK_3)
 		kn03_errintr();
-	return ((statusReg & ~causeReg & MACH_HARD_INT_MASK) |
-		MACH_SR_INT_ENA_CUR);
+	return ((statusReg & ~causeReg & MIPS_HARD_INT_MASK) |
+		MIPS_SR_INT_ENA_CUR);
 }
 #endif /* DS5000_240 */
 
@@ -781,14 +781,14 @@ static void
 pmax_errintr()
 {
 	volatile u_short *sysCSRPtr =
-		(u_short *)MACH_PHYS_TO_UNCACHED(KN01_SYS_CSR);
+		(u_short *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
 	u_short csr;
 
 	csr = *sysCSRPtr;
 
 	if (csr & KN01_CSR_MERR) {
 		printf("Memory error at 0x%x\n",
-			*(unsigned *)MACH_PHYS_TO_UNCACHED(KN01_SYS_ERRADR));
+			*(unsigned *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR));
 		panic("Mem error interrupt");
 	}
 	*sysCSRPtr = (csr & ~KN01_CSR_MBZ) | 0xff;
@@ -800,9 +800,9 @@ kn02_errintr()
 {
 	u_int erradr, chksyn, physadr;
 
-	erradr = *(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR);
-	chksyn = *(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CHKSYN);
-	*(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_ERRADR) = 0;
+	erradr = *(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR);
+	chksyn = *(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN);
+	*(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
 	wbflush();
 
 	if (!(erradr & KN02_ERR_VALID))
@@ -818,7 +818,7 @@ kn02_errintr()
 		(erradr & KN02_ERR_ECCERR) ? "ECC" : "timeout",
 		physadr);
 	if (erradr & KN02_ERR_ECCERR) {
-		*(u_int *)MACH_PHYS_TO_UNCACHED(KN02_SYS_CHKSYN) = 0;
+		*(u_int *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
 		wbflush();
 		printf("ECC 0x%08x\n", chksyn);
 
@@ -844,9 +844,9 @@ kn03_errintr()
 {
 	u_int erradr, errsyn, physadr;
 
-	erradr = *(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR);
-	errsyn = *(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRSYN);
-	*(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRADR) = 0;
+	erradr = *(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR);
+	errsyn = *(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN);
+	*(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0;
 	wbflush();
 
 	if (!(erradr & KN03_ERR_VALID))
@@ -862,7 +862,7 @@ kn03_errintr()
 		(erradr & KN03_ERR_ECCERR) ? "ECC" : "timeout",
 		physadr);
 	if (erradr & KN03_ERR_ECCERR) {
-		*(u_int *)MACH_PHYS_TO_UNCACHED(KN03_SYS_ERRSYN) = 0;
+		*(u_int *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN) = 0;
 		wbflush();
 		printf("   ECC 0x%08x\n", errsyn);
 
@@ -892,12 +892,12 @@ kn02ba_errintr()
 	register int mer, adr, siz;
 	static int errintr_cnt = 0;
 
-	siz = *(volatile int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_MSR);
-	mer = *(volatile int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_MER);
-	adr = *(volatile int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_AER);
+	siz = *(volatile int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR);
+	mer = *(volatile int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MER);
+	adr = *(volatile int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_AER);
 
 	/* clear interrupt bit */
-	*(unsigned int *)MACH_PHYS_TO_UNCACHED(KMIN_REG_TIMEOUT) = 0;
+	*(unsigned int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
 
 	errintr_cnt++;
 	printf("(%d)%s%x [%x %x %x]\n", errintr_cnt,
diff --git a/sys/arch/pmax/pmax/trap.c b/sys/arch/pmax/pmax/trap.c
index 5f22bc4af0b..803b7107945 100644
--- a/sys/arch/pmax/pmax/trap.c
+++ b/sys/arch/pmax/pmax/trap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: trap.c,v 1.13 1998/05/09 21:29:58 millert Exp $	*/
+/*	$OpenBSD: trap.c,v 1.14 1998/05/18 00:28:31 millert Exp $	*/
 /*	$NetBSD: trap.c,v 1.50 1996/10/13 21:37:49 jonathan Exp $	*/
 
 /*
@@ -429,7 +429,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 #endif
 
 	cnt.v_trap++;
-	type = (causeReg & MIPS_3K_CR_EXC_CODE) >> MACH_CR_EXC_CODE_SHIFT;
+	type = (causeReg & MIPS1_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
 	if (USERMODE(statusReg)) {
 		type |= T_USER;
 		sticks = p->p_sticks;
@@ -439,8 +439,8 @@ trap(statusReg, causeReg, vadr, pc, args)
 	 * Enable hardware interrupts if they were on before.
 	 * We only respond to software interrupts when returning to user mode.
 	 */
-	if (statusReg & MIPS_3K_SR_INT_ENA_PREV)
-		splx((statusReg & MACH_HARD_INT_MASK) | MIPS_SR_INT_IE);
+	if (statusReg & MIPS_SR_INT_ENA_PREV)
+		splx((statusReg & MIPS_HARD_INT_MASK) | MIPS_SR_INT_IE);
 
 	switch (type) {
 	case T_TLB_MOD:
@@ -501,7 +501,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		entry |= PG_M;
 		pte->pt_entry = entry;
 		vadr = (vadr & ~PGOFSET) |
-			(pmap->pm_tlbpid << VMMACH_TLB_PID_SHIFT);
+			(pmap->pm_tlbpid << MIPS_TLB_PID_SHIFT);
 		MachTLBUpdate(vadr, entry);
 		pa = PTE_TO_PADDR(entry);
 #ifdef ATTR
@@ -829,10 +829,10 @@ trap(statusReg, causeReg, vadr, pc, args)
 			p->p_md.md_ss_addr, p->p_md.md_ss_instr); /* XXX */
 #endif
 #ifdef KADB
-		if (instr == MACH_BREAK_BRKPT || instr == MACH_BREAK_SSTEP)
+		if (instr == MIPS_BREAK_BRKPT || instr == MIPS_BREAK_SSTEP)
 			goto err;
 #endif
-		if (p->p_md.md_ss_addr != va || instr != MACH_BREAK_SSTEP) {
+		if (p->p_md.md_ss_addr != va || instr != MIPS_BREAK_SSTEP) {
 			i = SIGTRAP;
 			typ = TRAP_TRACE;
 			break;
@@ -870,7 +870,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		break;
 
 	case T_COP_UNUSABLE+T_USER:
-		if ((causeReg & MACH_CR_COP_ERR) != 0x10000000) {
+		if ((causeReg & MIPS_CR_COP_ERR) != 0x10000000) {
 			i = SIGILL;	/* only FPU instructions allowed */
 			typ = ILL_ILLOPC;
 			break;
@@ -878,7 +878,7 @@ trap(statusReg, causeReg, vadr, pc, args)
 		MachSwitchFPState(machFPCurProcPtr,
 				  (struct user*)p->p_md.md_regs);
 		machFPCurProcPtr = p;
-		p->p_md.md_regs[PS] |= MACH_SR_COP_1_BIT;
+		p->p_md.md_regs[PS] |= MIPS_SR_COP_1_BIT;
 		p->p_md.md_flags |= MDP_FPUSED;
 		goto out;
 
@@ -1031,7 +1031,7 @@ interrupt(statusReg, causeReg, pc /* XXX what, args */ )
 	mask = causeReg & statusReg;	/* pending interrupts & enable mask */
 	if (mips_hardware_intr)
 		splx((*mips_hardware_intr)(mask, pc, statusReg, causeReg));
-	if (mask & MACH_INT_MASK_5) {
+	if (mask & MIPS_INT_MASK_5) {
 		intrcnt[FPU_INTR]++;
 		if (!USERMODE(statusReg)) {
 #ifdef DEBUG
@@ -1046,8 +1046,8 @@ interrupt(statusReg, causeReg, pc /* XXX what, args */ )
 
 	/* process network interrupt if we trapped or will very soon */
 	/* XXX fixme: operator precedence botch? */
-	if ((mask & MACH_SOFT_INT_MASK_1) ||
-	    netisr && (statusReg & MACH_SOFT_INT_MASK_1)) {
+	if ((mask & MIPS_SOFT_INT_MASK_1) ||
+	    netisr && (statusReg & MIPS_SOFT_INT_MASK_1)) {
 		clearsoftnet();
 		cnt.v_soft++;
 		intrcnt[SOFTNET_INTR]++;
@@ -1087,7 +1087,7 @@ interrupt(statusReg, causeReg, pc /* XXX what, args */ )
 #endif
 	}
 
-	if (mask & MACH_SOFT_INT_MASK_0) {
+	if (mask & MIPS_SOFT_INT_MASK_0) {
 		clearsoftclock();
 		intrcnt[SOFTCLOCK_INTR]++;
 		cnt.v_soft++;
@@ -1158,8 +1158,8 @@ trapDump(msg)
 		if (trp->cause == 0)
 			break;
 		printf("%s: ADR %x PC %x CR %x SR %x\n",
-			trap_type[(trp->cause & MIPS_3K_CR_EXC_CODE) >>
-				MACH_CR_EXC_CODE_SHIFT],
+			trap_type[(trp->cause & MIPS1_CR_EXC_CODE) >>
+				MIPS_CR_EXC_CODE_SHIFT],
 			trp->vadr, trp->pc, trp->cause, trp->status);
 		printf("   RA %x SP %x code %d\n", trp->ra, trp->sp, trp->code);
 	}
@@ -1201,7 +1201,7 @@ MachEmulateBranch(regsPtr, instPC, fpcCSR, allowNonBranch)
 	unsigned retAddr;
 	int condition;
 
-	inst.word = (instPC < MACH_CACHED_MEMORY_ADDR) ?
+	inst.word = (instPC < MIPS_KSEG0_START) ?
 		fuiword((caddr_t)instPC) : *(unsigned*)instPC;
 
 #if 0
@@ -1300,9 +1300,9 @@ MachEmulateBranch(regsPtr, instPC, fpcCSR, allowNonBranch)
 		case OP_BCx:
 		case OP_BCy:
 			if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
-				condition = fpcCSR & MACH_FPC_COND_BIT;
+				condition = fpcCSR & MIPS_FPU_COND_BIT;
 			else
-				condition = !(fpcCSR & MACH_FPC_COND_BIT);
+				condition = !(fpcCSR & MIPS_FPU_COND_BIT);
 			if (condition)
 				retAddr = GetBranchDest((InstFmt *)instPC);
 			else
@@ -1352,7 +1352,7 @@ cpu_singlestep(p)
 	}
 	p->p_md.md_ss_addr = va;
 	p->p_md.md_ss_instr = fuiword((caddr_t)va);
-	i = suiword((caddr_t)va, MACH_BREAK_SSTEP);
+	i = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
 	if (i < 0) {
 		vm_offset_t sa, ea;
 		int rv;
@@ -1362,13 +1362,13 @@ cpu_singlestep(p)
 		rv = vm_map_protect(&p->p_vmspace->vm_map, sa, ea,
 			VM_PROT_DEFAULT, FALSE);
 		if (rv == KERN_SUCCESS) {
-			i = suiword((caddr_t)va, MACH_BREAK_SSTEP);
+			i = suiword((caddr_t)va, MIPS_BREAK_SSTEP);
 			(void) vm_map_protect(&p->p_vmspace->vm_map,
 				sa, ea, VM_PROT_READ|VM_PROT_EXECUTE, FALSE);
 		}
 	}
 #endif
-	int bpinstr = MACH_BREAK_SSTEP;
+	int bpinstr = MIPS_BREAK_SSTEP;
 	int curinstr;
 	struct uio uio;
 	struct iovec iov;
diff --git a/sys/arch/pmax/pmax/vm_machdep.c b/sys/arch/pmax/pmax/vm_machdep.c
index 2e95d9fd75f..ac4779e6869 100644
--- a/sys/arch/pmax/pmax/vm_machdep.c
+++ b/sys/arch/pmax/pmax/vm_machdep.c
@@ -357,12 +357,12 @@ kvtophys(vm_offset_t kva)
 	pt_entry_t *pte;
 	vm_offset_t phys;
 
-        if (kva >= MACH_CACHED_MEMORY_ADDR && kva < MACH_UNCACHED_MEMORY_ADDR)
+        if (kva >= MIPS_KSEG0_START && kva < MIPS_KSEG1_START)
 	{
-		return (MACH_CACHED_TO_PHYS(kva));
+		return (MIPS_KSEG0_TO_PHYS(kva));
 	}
-	else if (kva >= MACH_UNCACHED_MEMORY_ADDR && kva < MACH_KSEG2_ADDR) {
-		return (MACH_UNCACHED_TO_PHYS(kva));
+	else if (kva >= MIPS_KSEG1_START && kva < MIPS_KSEG2_START) {
+		return (MIPS_KSEG1_TO_PHYS(kva));
 	}
 	else if (kva >= UADDR && kva < KERNELSTACK) {
 		int upage = (kva - UADDR) >> PGSHIFT;
@@ -371,7 +371,7 @@ kvtophys(vm_offset_t kva)
 		phys = (pte->pt_entry & PG_FRAME) |
 			(kva & PGOFSET);
 	}
-	else if (kva >= MACH_KSEG2_ADDR /*&& kva < VM_MAX_KERNEL_ADDRESS*/) {
+	else if (kva >= MIPS_KSEG2_START /*&& kva < VM_MAX_KERNEL_ADDRESS*/) {
 		pte = kvtopte(kva);
 
 		if ((pte - Sysmap) > Sysmapsize)  {
diff --git a/sys/arch/pmax/stand/dec_prom.h b/sys/arch/pmax/stand/dec_prom.h
index 6eecc47c5a7..739772de03b 100644
--- a/sys/arch/pmax/stand/dec_prom.h
+++ b/sys/arch/pmax/stand/dec_prom.h
@@ -311,7 +311,7 @@ typedef struct {
 /*
  * The nonvolatile ram has a flag to indicate it is usable.
  */
-#define MACH_USE_NON_VOLATILE 	((char *)0xbd0000c0)
-#define MACH_NON_VOLATILE_FLAG	0x02
+#define MIPS_USE_NON_VOLATILE 	((char *)0xbd0000c0)
+#define MIPS_NON_VOLATILE_FLAG	0x02
 
 #endif /* _DEC_PROM */
diff --git a/sys/arch/pmax/tc/scc.c b/sys/arch/pmax/tc/scc.c
index 4fe4c7c38a4..306774ed2d0 100644
--- a/sys/arch/pmax/tc/scc.c
+++ b/sys/arch/pmax/tc/scc.c
@@ -496,7 +496,7 @@ sccattach(parent, self, aux)
 		printf("\nattaching scc%d, currently PROM console\n", unit);
 #endif /* defined(DEBUG) && defined(HAVE_RCONS)*/
 
-	sccaddr = (void*)MACH_PHYS_TO_UNCACHED(d->iada_addr);
+	sccaddr = (void*)MIPS_PHYS_TO_KSEG1(d->iada_addr);
 #ifdef SPARSE
 	sccaddr = (void *)TC_DENSE_TO_SPARSE((tc_addr_t)sccaddr);
 #endif
diff --git a/sys/arch/pmax/tc/tc.c b/sys/arch/pmax/tc/tc.c
index 487bc8d854c..8a0654b7995 100644
--- a/sys/arch/pmax/tc/tc.c
+++ b/sys/arch/pmax/tc/tc.c
@@ -98,7 +98,7 @@ int consprobeslot __P((int slot));
 #include <pmax/pmax/turbochannel.h>
 
 /*#include <pmax/pmax/nameglue.h>*/
-#define KV(x) ((tc_addr_t)MACH_PHYS_TO_UNCACHED(x))
+#define KV(x) ((tc_addr_t)MIPS_PHYS_TO_KSEG1(x))
 
 
 
diff --git a/sys/arch/pmax/tc/tc_subr.c b/sys/arch/pmax/tc/tc_subr.c
index 8cb7487cae0..6e01cb20a21 100644
--- a/sys/arch/pmax/tc/tc_subr.c
+++ b/sys/arch/pmax/tc/tc_subr.c
@@ -74,7 +74,7 @@ static int tc_consprobeslot __P((tc_addr_t slotaddr));
 
 
 /*#include <pmax/pmax/nameglue.h>*/
-#define KV(x) ((tc_addr_t)MACH_PHYS_TO_UNCACHED(x))
+#define KV(x) ((tc_addr_t)MIPS_PHYS_TO_KSEG1(x))