Switch off CPU-PCI write posting for the Saturn chipset; it is known

to cause problems with PCI busmasters; fvdl

1 files changed, 20 insertions, 0 deletions

diff --git a/sys/arch/i386/pci/pchb.c b/sys/arch/i386/pci/pchb.c
index 88b5cb6aea1..c0422cc87cd 100644
--- a/sys/arch/i386/pci/pchb.c
+++ b/sys/arch/i386/pci/pchb.c
@@ -56,6 +56,15 @@
 #define PCISET_BRIDGE_NUMBER(reg)	(((reg) >> 8) & 0xff)
 #define PCISET_PCI_BUS_NUMBER(reg)	(((reg) >> 16) & 0xff)
 
+/* XXX should be in dev/ic/i82424{reg.var}.h */
+#define I82424_CPU_BCTL_REG		0x53
+#define I82424_PCI_BCTL_REG		0x54
+
+#define I82424_BCTL_CPUMEM_POSTEN	0x01
+#define I82424_BCTL_CPUPCI_POSTEN	0x02
+#define I82424_BCTL_PCIMEM_BURSTEN	0x01
+#define I82424_BCTL_PCI_BURSTEN		0x02
+
 int	pchbmatch __P((struct device *, void *, void *));
 void	pchbattach __P((struct device *, struct device *, void *));
 
@@ -69,6 +78,7 @@ struct cfdriver pchb_cd = {
 	NULL, "pchb", DV_DULL
 };
 
+
 int
 pchbmatch(parent, match, aux)
 	struct device *parent;
@@ -129,6 +139,16 @@ pchbattach(parent, self, aux)
 				break;
 			}
 			break;
+		case PCI_PRODUCT_INTEL_CDC:
+			bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
+			    I82424_CPU_BCTL_REG);
+			if (bcreg & I82424_BCTL_CPUPCI_POSTEN) {
+				bcreg &= ~I82424_BCTL_CPUPCI_POSTEN;
+				pci_conf_write(pa->pa_pc, pa->pa_tag,
+				    I82424_CPU_BCTL_REG, bcreg);
+				printf(": disabled CPU-PCI write posting\n");
+			}
+			break;
 		default:
 			printf("\n");
 			break;