unifdef CPU_XSCALE_PXA2X0, ARM_MMU_XSCALE, ARM_MMU_GENERIC (armv3)

and remove some xscale definitions.

ok kettenis@

5 files changed, 10 insertions, 288 deletions

diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h
index b317892ef36..6c88e85b47c 100644
--- a/sys/arch/arm/include/armreg.h
+++ b/sys/arch/arm/include/armreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: armreg.h,v 1.38 2017/01/01 09:54:44 jsg Exp $	*/
+/*	$OpenBSD: armreg.h,v 1.39 2017/01/04 00:40:49 jsg Exp $	*/
 /*	$NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $	*/
 
 /*
@@ -109,11 +109,8 @@
 /* The high-order byte is always the implementor */
 #define CPU_ID_IMPLEMENTOR_MASK	0xff000000
 #define CPU_ID_ARM_LTD		0x41000000 /* 'A' */
-#define CPU_ID_INTEL		0x69000000 /* 'i' */
 
 #define CPU_ID_ARCH_MASK	0x000f0000
-#define CPU_ID_ARCH_V5TE	0x00050000
-#define CPU_ID_ARCH_V5TEJ	0x00060000
 #define CPU_ID_ARCH_V6		0x00070000
 #define CPU_ID_ARCH_CPUID	0x000f0000
 #define CPU_ID_VARIANT_MASK	0x00f00000
@@ -121,25 +118,11 @@
 /* Next three nybbles are part number */
 #define CPU_ID_PARTNO_MASK	0x0000fff0
 
-/* Intel XScale has sub fields in part number */
-#define CPU_ID_XSCALE_COREGEN_MASK	0x0000e000 /* core generation */
-#define CPU_ID_XSCALE_COREREV_MASK	0x00001c00 /* core revision */
-#define CPU_ID_XSCALE_PRODUCT_MASK	0x000003f0 /* product number */
-
 /* And finally, the revision number. */
 #define CPU_ID_REVISION_MASK	0x0000000f
 
 /* Individual CPUs are probably best IDed by everything but the revision. */
 #define CPU_ID_CPU_MASK		0xfffffff0
-#define CPU_ID_PXA250		0x69052100 /* sans core revision */
-#define CPU_ID_PXA210		0x69052120
-#define CPU_ID_PXA250A		0x69052100 /* 1st version Core */
-#define CPU_ID_PXA210A		0x69052120 /* 1st version Core */
-#define CPU_ID_PXA250B		0x69052900 /* 3rd version Core */
-#define CPU_ID_PXA210B		0x69052920 /* 3rd version Core */
-#define CPU_ID_PXA250C		0x69052d00 /* 4th version Core */
-#define CPU_ID_PXA210C		0x69052d20 /* 4th version Core */
-#define CPU_ID_PXA27X		0x69054110
 #define CPU_ID_CORTEX_MASK	0xff0ffff0
 #define CPU_ID_CORTEX_A5	0x410fc050
 #define CPU_ID_CORTEX_A5_MASK	0xff0ffff0
@@ -259,14 +242,6 @@
 
 #define CPU_CONTROL_IDC_ENABLE	CPU_CONTROL_DC_ENABLE
 
-/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
-#define XSCALE_AUXCTL_K		0x00000001 /* dis. write buffer coalescing */
-#define XSCALE_AUXCTL_P		0x00000002 /* ECC protect page table access */
-#define XSCALE_AUXCTL_MD_WB_RA	0x00000000 /* mini-D$ wb, read-allocate */
-#define XSCALE_AUXCTL_MD_WB_RWA	0x00000010 /* mini-D$ wb, read/write-allocate */
-#define XSCALE_AUXCTL_MD_WT	0x00000020 /* mini-D$ wt, read-allocate */
-#define XSCALE_AUXCTL_MD_MASK	0x00000030
-
 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
 #define CORTEXA9_AUXCTL_FW	(1 << 0) /* Cache and TLB updates broadcast */
 #define CORTEXA9_AUXCTL_L2PE	(1 << 1) /* Prefetch hint enable */
diff --git a/sys/arch/arm/include/cpuconf.h b/sys/arch/arm/include/cpuconf.h
index 5af430eaaae..469585c4a69 100644
--- a/sys/arch/arm/include/cpuconf.h
+++ b/sys/arch/arm/include/cpuconf.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpuconf.h,v 1.17 2016/08/14 11:30:54 jsg Exp $	*/
+/*	$OpenBSD: cpuconf.h,v 1.18 2017/01/04 00:40:49 jsg Exp $	*/
 /*	$NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $	*/
 
 /*
@@ -48,12 +48,6 @@
 /*
  * Determine which ARM architecture versions are configured.
  */
-#if defined(CPU_XSCALE_PXA2X0)
-#define	ARM_ARCH_5	1
-#else
-#define	ARM_ARCH_5	0
-#endif
-
 #if defined(CPU_ARMv7)
 #define ARM_ARCH_7     1
 #else 
@@ -63,34 +57,16 @@
 /*
  * Define which MMU classes are configured:
  *
- *	ARM_MMU_GENERIC		Generic ARM MMU, compatible with ARM6.
- *
- *	ARM_MMU_XSCALE		XScale MMU.  Compatible with generic ARM
- *				MMU, but also has several extensions which
- *				require different PTE layout to use.
  *      ARM_MMU_V7		v6/v7 MMU with XP bit enabled subpage
  *				protection is not used, TEX/AP is used instead.
  */
 
 #if defined(CPU_ARMv7)
-#define	ARM_MMU_GENERIC		1
-#else
-#define	ARM_MMU_GENERIC		0
-#endif
-
-#if defined(CPU_XSCALE_PXA2X0)
-#define	ARM_MMU_XSCALE		1
-#else
-#define	ARM_MMU_XSCALE		0
-#endif
-
-#if defined(CPU_ARMv7)
 #define ARM_MMU_V7		1
 #else
 #define ARM_MMU_V7		0
 #endif
 
-#define	ARM_NMMUS		(ARM_MMU_GENERIC +	\
-				 ARM_MMU_XSCALE + ARM_MMU_V7)
+#define	ARM_NMMUS		(ARM_MMU_V7)
 
 #endif /* _ARM_CPUCONF_H_ */
diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h
index c8910187b78..7a824565a01 100644
--- a/sys/arch/arm/include/cpufunc.h
+++ b/sys/arch/arm/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.27 2016/08/22 01:42:00 jsg Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.28 2017/01/04 00:40:49 jsg Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
 
 /*
@@ -254,56 +254,6 @@ extern unsigned armv7_dcache_index_max;
 extern unsigned armv7_dcache_index_inc;
 #endif
 
-
-#if defined(CPU_XSCALE_PXA2X0)
-void	armv4_tlb_flushID	(void);
-void	armv4_tlb_flushI	(void);
-void	armv4_tlb_flushD	(void);
-void	armv4_tlb_flushD_SE	(u_int va);
-
-void	armv4_drain_writebuf	(void);
-#endif
-
-#if defined(CPU_XSCALE_PXA2X0) || (ARM_MMU_XSCALE == 1)
-void	xscale_cpwait		(void);
-
-void	xscale_cpu_sleep	(int mode);
-
-u_int	xscale_control		(u_int clear, u_int bic);
-
-void	xscale_setttb		(u_int ttb);
-
-void	xscale_tlb_flushID_SE	(u_int va);
-
-void	xscale_cache_flushID	(void);
-void	xscale_cache_flushI	(void);
-void	xscale_cache_flushD	(void);
-void	xscale_cache_flushD_SE	(u_int entry);
-
-void	xscale_cache_cleanID	(void);
-void	xscale_cache_cleanD	(void);
-void	xscale_cache_cleanD_E	(u_int entry);
-
-void	xscale_cache_clean_minidata (void);
-
-void	xscale_cache_purgeID	(void);
-void	xscale_cache_purgeID_E	(u_int entry);
-void	xscale_cache_purgeD	(void);
-void	xscale_cache_purgeD_E	(u_int entry);
-
-void	xscale_cache_syncI	(void);
-void	xscale_cache_cleanID_rng (vaddr_t start, vsize_t end);
-void	xscale_cache_cleanD_rng	(vaddr_t start, vsize_t end);
-void	xscale_cache_purgeID_rng (vaddr_t start, vsize_t end);
-void	xscale_cache_purgeD_rng	(vaddr_t start, vsize_t end);
-void	xscale_cache_syncI_rng	(vaddr_t start, vsize_t end);
-void	xscale_cache_flushD_rng	(vaddr_t start, vsize_t end);
-
-void	xscale_context_switch	(u_int);
-
-void	xscale_setup		(void);
-#endif	/* CPU_XSCALE_PXA2X0 */
-
 #define tlb_flush	cpu_tlb_flushID
 #define setttb		cpu_setttb
 #define drain_writebuf	cpu_drain_writebuf
diff --git a/sys/arch/arm/include/pmap.h b/sys/arch/arm/include/pmap.h
index 62465c6cd28..b7dbf94b640 100644
--- a/sys/arch/arm/include/pmap.h
+++ b/sys/arch/arm/include/pmap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.h,v 1.46 2016/08/26 11:59:04 kettenis Exp $	*/
+/*	$OpenBSD: pmap.h,v 1.47 2017/01/04 00:40:49 jsg Exp $	*/
 /*	$NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $	*/
 
 /*
@@ -361,9 +361,6 @@ do {									\
 #define l2pte_index(v)		(((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
 #define	l2pte_valid(pte)	(((pte) & L2_TYPE_MASK) != L2_TYPE_INV)
 #define	l2pte_pa(pte)		((pte) & L2_S_FRAME)
-#define l2pte_minidata(pte)	(((pte) & \
-				 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
-				 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
 
 /* L1 and L2 page table macros */
 #define pmap_pde_v(pde)		l1pte_valid(*(pde))
@@ -373,7 +370,7 @@ do {									\
 
 /************************* ARM MMU configuration *****************************/
 
-#if (ARM_MMU_GENERIC + ARM_MMU_V7) != 0
+#if (ARM_MMU_V7) != 0
 void	pmap_copy_page_generic(struct vm_page *, struct vm_page *);
 void	pmap_zero_page_generic(struct vm_page *);
 
@@ -381,24 +378,12 @@ void	pmap_pte_init_generic(void);
 #if defined(CPU_ARMv7)
 void	pmap_pte_init_armv7(void);
 #endif /* CPU_ARMv7 */
-#endif /* (ARM_MMU_GENERIC + ARM_MMU_V7) != 0 */
+#endif /* (ARM_MMU_V7) != 0 */
 
 #if ARM_MMU_V7 == 1
 void	pmap_pte_init_v7(void);
 #endif /* ARM_MMU_V7 == 1 */
 
-#if ARM_MMU_XSCALE == 1
-void	pmap_copy_page_xscale(struct vm_page *, struct vm_page *);
-void	pmap_zero_page_xscale(struct vm_page *);
-
-void	pmap_pte_init_xscale(void);
-
-void	xscale_setup_minidata(vaddr_t, vaddr_t, paddr_t);
-
-#define	PMAP_UAREA(va)		pmap_uarea(va)
-void	pmap_uarea(vaddr_t);
-#endif /* ARM_MMU_XSCALE == 1 */
-
 extern pt_entry_t		pte_l1_s_cache_mode;
 extern pt_entry_t		pte_l1_s_cache_mask;
 
@@ -457,96 +442,42 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
  * We use these macros since we use different bits on different processor
  * models.
  */
-#define	L1_S_PROT_UR_generic	(L1_S_AP(AP_U))
-#define	L1_S_PROT_UW_generic	(L1_S_AP(AP_U|AP_W))
-#define	L1_S_PROT_KR_generic	(L1_S_AP(0))
-#define	L1_S_PROT_KW_generic	(L1_S_AP(AP_W))
-#define	L1_S_PROT_MASK_generic	(L1_S_AP(0x03))
-
-#define	L1_S_PROT_UR_xscale	(L1_S_AP(AP_U))
-#define	L1_S_PROT_UW_xscale	(L1_S_AP(AP_U|AP_W))
-#define	L1_S_PROT_KR_xscale	(L1_S_AP(0))
-#define	L1_S_PROT_KW_xscale	(L1_S_AP(AP_W))
-#define	L1_S_PROT_MASK_xscale	(L1_S_AP(0x03))
-
 #define	L1_S_PROT_UR_v7		(L1_S_V7_AP(AP_V7_KRUR))
 #define	L1_S_PROT_UW_v7		(L1_S_V7_AP(AP_KRWURW))
 #define	L1_S_PROT_KR_v7		(L1_S_V7_AP(AP_V7_KR))
 #define	L1_S_PROT_KW_v7		(L1_S_V7_AP(AP_KRW))
 #define	L1_S_PROT_MASK_v7	(L1_S_V7_AP(0x07))
 
-#define	L1_S_CACHE_MASK_generic	(L1_S_B|L1_S_C)
-#define	L1_S_CACHE_MASK_xscale	(L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X))
 #define	L1_S_CACHE_MASK_v7	(L1_S_B|L1_S_C|L1_S_V7_TEX_MASK)
 
-#define	L1_S_COHERENT_generic	(L1_S_B|L1_S_C)
-#define	L1_S_COHERENT_xscale	(L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X))
 #define	L1_S_COHERENT_v7	(L1_S_C)
 
-#define	L2_L_PROT_KR_generic	(L2_AP(0))
-#define	L2_L_PROT_UR_generic	(L2_AP(AP_U))
-#define	L2_L_PROT_KW_generic	(L2_AP(AP_W))
-#define	L2_L_PROT_UW_generic	(L2_AP(AP_U|AP_W))
-#define	L2_L_PROT_MASK_generic	(L2_AP(AP_U|AP_W))
-
-#define	L2_L_PROT_KR_xscale	(L2_AP(0))
-#define	L2_L_PROT_UR_xscale	(L2_AP(AP_U))
-#define	L2_L_PROT_KW_xscale	(L2_AP(AP_W))
-#define	L2_L_PROT_UW_xscale	(L2_AP(AP_U|AP_W))
-#define	L2_L_PROT_MASK_xscale	(L2_AP(AP_U|AP_W))
-
 #define	L2_L_PROT_UR_v7		(L2_V7_AP(AP_V7_KRUR))
 #define	L2_L_PROT_UW_v7		(L2_V7_AP(AP_KRWURW))
 #define	L2_L_PROT_KR_v7		(L2_V7_AP(AP_V7_KR))
 #define	L2_L_PROT_KW_v7		(L2_V7_AP(AP_KRW))
 #define	L2_L_PROT_MASK_v7	(L2_V7_AP(0x07) | L2_V7_L_XN)
 
-#define	L2_L_CACHE_MASK_generic	(L2_B|L2_C)
-#define	L2_L_CACHE_MASK_xscale	(L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X))
 #define	L2_L_CACHE_MASK_v7	(L2_B|L2_C|L2_V7_L_TEX_MASK)
 
-#define	L2_L_COHERENT_generic	(L2_B|L2_C)
-#define	L2_L_COHERENT_xscale	(L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X))
 #define	L2_L_COHERENT_v7	(L2_C)
 
-#define	L2_S_PROT_UR_generic	(L2_AP(AP_U))
-#define	L2_S_PROT_UW_generic	(L2_AP(AP_U|AP_W))
-#define	L2_S_PROT_KR_generic	(L2_AP(0))
-#define	L2_S_PROT_KW_generic	(L2_AP(AP_W))
-#define	L2_S_PROT_MASK_generic	(L2_AP(AP_U|AP_W))
-
-#define	L2_S_PROT_UR_xscale	(L2_AP0(AP_U))
-#define	L2_S_PROT_UW_xscale	(L2_AP0(AP_U|AP_W))
-#define	L2_S_PROT_KR_xscale	(L2_AP0(0))
-#define	L2_S_PROT_KW_xscale	(L2_AP0(AP_W))
-#define	L2_S_PROT_MASK_xscale	(L2_AP0(AP_U|AP_W))
-
 #define	L2_S_PROT_UR_v7		(L2_V7_AP(AP_V7_KRUR))
 #define	L2_S_PROT_UW_v7		(L2_V7_AP(AP_KRWURW))
 #define	L2_S_PROT_KR_v7		(L2_V7_AP(AP_V7_KR))
 #define	L2_S_PROT_KW_v7		(L2_V7_AP(AP_KRW))
 #define	L2_S_PROT_MASK_v7	(L2_V7_AP(0x07) | L2_V7_S_XN)
 
-#define	L2_S_CACHE_MASK_generic	(L2_B|L2_C)
-#define	L2_S_CACHE_MASK_xscale	(L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X))
 #define	L2_S_CACHE_MASK_v7	(L2_B|L2_C|L2_V7_S_TEX_MASK)
 
-#define	L2_S_COHERENT_generic	(L2_B|L2_C)
-#define	L2_S_COHERENT_xscale	(L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X))
 #define	L2_S_COHERENT_v7	(L2_C)
 
-#define	L1_S_PROTO_generic	(L1_TYPE_S | L1_S_IMP)
-#define	L1_S_PROTO_xscale	(L1_TYPE_S)
 #define	L1_S_PROTO_v7		(L1_TYPE_S)
 
-#define	L1_C_PROTO_generic	(L1_TYPE_C | L1_C_IMP2)
-#define	L1_C_PROTO_xscale	(L1_TYPE_C)
 #define	L1_C_PROTO_v7		(L1_TYPE_C)
 
 #define	L2_L_PROTO		(L2_TYPE_L)
 
-#define	L2_S_PROTO_generic	(L2_TYPE_S)
-#define	L2_S_PROTO_xscale	(L2_TYPE_XSCALE_XS)
 #define	L2_S_PROTO_v7		(L2_TYPE_S)
 
 /*
@@ -587,72 +518,6 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
 
 #define	pmap_copy_page(s, d)	(*pmap_copy_page_func)((s), (d))
 #define	pmap_zero_page(d)	(*pmap_zero_page_func)((d))
-#elif ARM_MMU_GENERIC == 1
-#define	L1_S_PROT_UR		L1_S_PROT_UR_generic
-#define	L1_S_PROT_UW		L1_S_PROT_UW_generic
-#define	L1_S_PROT_KR		L1_S_PROT_KR_generic
-#define	L1_S_PROT_KW		L1_S_PROT_KW_generic
-#define	L1_S_PROT_MASK		L1_S_PROT_MASK_generic
-
-#define	L2_L_PROT_UR		L2_L_PROT_UR_generic
-#define	L2_L_PROT_UW		L2_L_PROT_UW_generic
-#define	L2_L_PROT_KR		L2_L_PROT_KR_generic
-#define	L2_L_PROT_KW		L2_L_PROT_KW_generic
-#define	L2_L_PROT_MASK		L2_L_PROT_MASK_generic
-
-#define	L2_S_PROT_UR		L2_S_PROT_UR_generic
-#define	L2_S_PROT_UW		L2_S_PROT_UW_generic
-#define	L2_S_PROT_KR		L2_S_PROT_KR_generic
-#define	L2_S_PROT_KW		L2_S_PROT_KW_generic
-#define	L2_S_PROT_MASK		L2_S_PROT_MASK_generic
-
-#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_generic
-#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_generic
-#define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_generic
-
-#define	L1_S_COHERENT		L1_S_COHERENT_generic
-#define	L2_L_COHERENT		L2_L_COHERENT_generic
-#define	L2_S_COHERENT		L2_S_COHERENT_generic
-
-#define	L1_S_PROTO		L1_S_PROTO_generic
-#define	L1_C_PROTO		L1_C_PROTO_generic
-#define	L2_S_PROTO		L2_S_PROTO_generic
-
-#define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
-#define	pmap_zero_page(d)	pmap_zero_page_generic((d))
-#elif ARM_MMU_XSCALE == 1
-#define	L1_S_PROT_UR		L1_S_PROT_UR_xscale
-#define	L1_S_PROT_UW		L1_S_PROT_UW_xscale
-#define	L1_S_PROT_KR		L1_S_PROT_KR_xscale
-#define	L1_S_PROT_KW		L1_S_PROT_KW_xscale
-#define	L1_S_PROT_MASK		L1_S_PROT_MASK_xscale
-
-#define	L2_L_PROT_UR		L2_L_PROT_UR_xscale
-#define	L2_L_PROT_UW		L2_L_PROT_UW_xscale
-#define	L2_L_PROT_KR		L2_L_PROT_KR_xscale
-#define	L2_L_PROT_KW		L2_L_PROT_KW_xscale
-#define	L2_L_PROT_MASK		L2_L_PROT_MASK_xscale
-
-#define	L2_S_PROT_UR		L2_S_PROT_UR_xscale
-#define	L2_S_PROT_UW		L2_S_PROT_UW_xscale
-#define	L2_S_PROT_KR		L2_S_PROT_KR_xscale
-#define	L2_S_PROT_KW		L2_S_PROT_KW_xscale
-#define	L2_S_PROT_MASK		L2_S_PROT_MASK_xscale
-
-#define	L1_S_CACHE_MASK		L1_S_CACHE_MASK_xscale
-#define	L2_L_CACHE_MASK		L2_L_CACHE_MASK_xscale
-#define	L2_S_CACHE_MASK		L2_S_CACHE_MASK_xscale
-
-#define	L1_S_COHERENT		L1_S_COHERENT_xscale
-#define	L2_L_COHERENT		L2_L_COHERENT_xscale
-#define	L2_S_COHERENT		L2_S_COHERENT_xscale
-
-#define	L1_S_PROTO		L1_S_PROTO_xscale
-#define	L1_C_PROTO		L1_C_PROTO_xscale
-#define	L2_S_PROTO		L2_S_PROTO_xscale
-
-#define	pmap_copy_page(s, d)	pmap_copy_page_xscale((s), (d))
-#define	pmap_zero_page(d)	pmap_zero_page_xscale((d))
 #elif ARM_MMU_V7 == 1
 #define	L1_S_PROT_UR		L1_S_PROT_UR_v7
 #define	L1_S_PROT_UW		L1_S_PROT_UW_v7
@@ -684,8 +549,8 @@ extern void (*pmap_zero_page_func)(struct vm_page *);
 #define	L1_C_PROTO		L1_C_PROTO_v7
 #define	L2_S_PROTO		L2_S_PROTO_v7
 
-#define	pmap_copy_page(s, d)	pmap_copy_page_v7((s), (d))
-#define	pmap_zero_page(d)	pmap_zero_page_v7((d))
+#define	pmap_copy_page(s, d)	pmap_copy_page_generic((s), (d))
+#define	pmap_zero_page(d)	pmap_zero_page_generic((d))
 #endif /* ARM_NMMUS > 1 */
 
 /*
diff --git a/sys/arch/arm/include/pte.h b/sys/arch/arm/include/pte.h
index 4dc2638fa2b..53b6cc8831f 100644
--- a/sys/arch/arm/include/pte.h
+++ b/sys/arch/arm/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.8 2016/08/27 14:22:35 kettenis Exp $	*/
+/*	$OpenBSD: pte.h,v 1.9 2017/01/04 00:40:49 jsg Exp $	*/
 /*	$NetBSD: pte.h,v 1.6 2003/04/18 11:08:28 scw Exp $	*/
 
 /*
@@ -146,9 +146,6 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L1_S_AP(x)	((x) << 10)	/* access permissions */
 #define	L1_S_ADDR_MASK	0xfff00000	/* phys address of section */
 
-#define	L1_S_XSCALE_P	0x00000200	/* ECC enable for this section */
-#define	L1_S_XSCALE_TEX(x) ((x) << 12)	/* Type Extension */
-
 #define	L1_S_V7_TEX(x)	(((x) & 0x7) << 12)	/* Type Extension */
 #define	L1_S_V7_TEX_MASK	(0x7 << 12)	/* Type Extension */
 #define	L1_S_V7_NS	0x00080000	/* Non-secure */
@@ -169,8 +166,6 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L1_C_DOM_MASK	L1_C_DOM(0xf)
 #define	L1_C_ADDR_MASK	0xfffffc00	/* phys address of L2 Table */
 
-#define	L1_C_XSCALE_P	0x00000200	/* ECC enable for this section */
-
 #define	L1_C_V7_IMP	0x00000200	/* implementation defined */
 #define	L1_C_V7_NS	0x00000008	/* Non-secure */
 #define	L1_C_V7_PXN	0x00000004	/* Privileged eXecute Never */
@@ -183,8 +178,6 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L1_F_DOM_MASK	L1_F_DOM(0xf)
 #define	L1_F_ADDR_MASK	0xfffff000	/* phys address of L2 Table */
 
-#define	L1_F_XSCALE_P	0x00000200	/* ECC enable for this section */
-
 /*
  * ARM L2 Descriptors
  */
@@ -195,14 +188,6 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L2_TYPE_T	0x03		/* Tiny Page (pre-V7) */
 #define	L2_TYPE_MASK	0x03		/* mask of type bits */
 
-	/*
-	 * This L2 Descriptor type is available on XScale processors
-	 * when using a Coarse L1 Descriptor.  The Extended Small
-	 * Descriptor has the same format as the XScale Tiny Descriptor,
-	 * but describes a 4K page, rather than a 1K page.
-	 */
-#define	L2_TYPE_XSCALE_XS 0x03		/* XScale Extended Small Page */
-
 #define	L2_B		0x00000004	/* Bufferable page */
 #define	L2_C		0x00000008	/* Cacheable page */
 #define	L2_AP0(x)	((x) << 4)	/* access permissions (sp 0) */
@@ -211,9 +196,6 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L2_AP3(x)	((x) << 10)	/* access permissions (sp 3) */
 #define	L2_AP(x)	(L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
 
-#define	L2_XSCALE_L_TEX(x) ((x) << 12)	/* Type Extension */
-#define	L2_XSCALE_T_TEX(x) ((x) << 6)	/* Type Extension */
-
 #define	L2_V7_L_TEX(x)	(((x) & 0x7) << 12)	/* Type Extension */
 #define	L2_V7_L_TEX_MASK	(0x7 << 12)	/* Type Extension */
 #define	L2_V7_L_XN	0x00008000	/* eXecute Never */
@@ -227,12 +209,6 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	L2_V7_nG	0x00000800	/* not Global */
 
 /*
- * Access Permissions for L1 and L2 Descriptors. (except for V7)
- */
-#define	AP_W		0x01		/* writable */
-#define	AP_U		0x02		/* user */
-
-/*
  * Short-hand for common AP_* constants.
  *
  * Note: These values assume the S (System) bit is set and
@@ -253,24 +229,4 @@ typedef uint32_t	pt_entry_t;	/* L2 table entry */
 #define	DOMAIN_RESERVED	0x02		/* reserved */
 #define	DOMAIN_MANAGER	0x03		/* manager */
 
-/*
- * Type Extension bits for XScale processors.
- *
- * Behavior of C and B when X == 0:
- *
- * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
- * 0 0      N          N            -                 -
- * 0 1      N          Y            -                 -
- * 1 0      Y          Y       Write-through    Read Allocate
- * 1 1      Y          Y        Write-back      Read Allocate
- *
- * Behavior of C and B when X == 1:
- * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
- * 0 0      -          -            -                 -           DO NOT USE
- * 0 1      N          Y            -                 -
- * 1 0  Mini-Data      -            -                 -
- * 1 1      Y          Y        Write-back       R/W Allocate
- */
-#define	TEX_XSCALE_X	0x01		/* X modifies C and B */
-
 #endif /* _ARM_PTE_H_ */