start to sync some changes and fixes from various "openhal" ports of

this driver. thanks for contribution (even if i didn't get much
feedback from these projects...).

tested by many during c2k6, like aanriot@ and ian@

5 files changed, 210 insertions, 42 deletions

diff --git a/sys/dev/ic/ar5212.c b/sys/dev/ic/ar5212.c
index 395a5554172..bac94483d70 100644
--- a/sys/dev/ic/ar5212.c
+++ b/sys/dev/ic/ar5212.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212.c,v 1.28 2005/12/18 17:59:58 reyk Exp $	*/
+/*	$OpenBSD: ar5212.c,v 1.29 2006/06/05 15:21:43 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
@@ -544,7 +544,7 @@ ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
 		    rt->rt_info[i].r_control_rate, AH_FALSE));
 	}
 
-	if (!(channel->c_channel_flags & IEEE80211_CHAN_TURBO)) {
+	if ((channel->c_channel_flags & IEEE80211_CHAN_TURBO) == 0) {
 		rt = ar5k_ar5212_get_rate_table(hal, HAL_MODE_11B);
 		for (i = 0; i < rt->rt_rate_count; i++) {
 			data = AR5K_AR5212_RATE_DUR(rt->rt_info[i].r_rate_code);
@@ -560,6 +560,18 @@ ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
 		}
 	}
 
+	/* Fix for first revision of the AR5112 RF chipset */
+	if (hal->ah_radio >= AR5K_AR5112 &&
+	    hal->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
+		AR5K_REG_WRITE(AR5K_AR5212_PHY_CCKTXCTL,
+		    AR5K_AR5212_PHY_CCKTXCTL_WORLD);
+		if (channel->c_channel_flags & IEEE80211_CHAN_OFDM)
+			data = 0xffb81020;
+		else
+			data = 0xffb80d20;
+		AR5K_REG_WRITE(AR5K_AR5212_PHY_FC, data);
+	}
+
 	/*
 	 * Set TX power (XXX use txpower from net80211)
 	 */
@@ -721,9 +733,8 @@ ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
 	    AR5K_AR5212_PHY_AGCCTL_NF |
 	    AR5K_AR5212_PHY_AGCCTL_CAL);
 
-	if (channel->c_channel_flags & IEEE80211_CHAN_B) {
-		hal->ah_calibration = AH_FALSE;
-	} else {
+	hal->ah_calibration = AH_FALSE;
+	if ((channel->c_channel_flags & IEEE80211_CHAN_B) == 0) {
 		hal->ah_calibration = AH_TRUE;
 		AR5K_REG_WRITE_BITS(AR5K_AR5212_PHY_IQ,
 		    AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX, 15);
@@ -993,18 +1004,17 @@ ar5k_ar5212_reset_tx_queue(struct ath_hal *hal, u_int queue)
 	/*
 	 * Set registers by channel mode
 	 */
+	cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN;
+	cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX;
+	hal->ah_aifs = AR5K_TUNE_AIFS;
 	if (IEEE80211_IS_CHAN_XR(channel)) {
-		hal->ah_cw_min = AR5K_TUNE_CWMIN_XR;
+		cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_XR;
 		cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_XR;
 		hal->ah_aifs = AR5K_TUNE_AIFS_XR;
 	} else if (IEEE80211_IS_CHAN_B(channel)) {
-		hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
+		cw_min = hal->ah_cw_min = AR5K_TUNE_CWMIN_11B;
 		cw_max = hal->ah_cw_max = AR5K_TUNE_CWMAX_11B;
 		hal->ah_aifs = AR5K_TUNE_AIFS_11B;
-	} else {
-		hal->ah_cw_min = AR5K_TUNE_CWMIN;
-		hal->ah_cw_max = AR5K_TUNE_CWMAX;
-		hal->ah_aifs = AR5K_TUNE_AIFS;
 	}
 
 	/*
diff --git a/sys/dev/ic/ar5212reg.h b/sys/dev/ic/ar5212reg.h
index 43af0889100..a2b3cbc665e 100644
--- a/sys/dev/ic/ar5212reg.h
+++ b/sys/dev/ic/ar5212reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212reg.h,v 1.7 2005/12/18 17:59:58 reyk Exp $	*/
+/*	$OpenBSD: ar5212reg.h,v 1.8 2006/06/05 15:21:43 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
@@ -1217,6 +1217,13 @@ typedef enum {
 #define AR5K_AR5212_PHY_MODE_XR		0x00000010
 
 /*
+ * PHY CCK transmit control register
+ */
+#define AR5K_AR5212_PHY_CCKTXCTL	0xa204
+#define AR5K_AR5212_PHY_CCKTXCTL_WORLD	0x00000000
+#define AR5K_AR5212_PHY_CCKTXCTL_JAPAN	0x00000010
+
+/*
  * PHY 2GHz gain register
  */
 #define	AR5K_AR5212_PHY_GAIN_2GHZ		0xa20c
diff --git a/sys/dev/ic/ar5212var.h b/sys/dev/ic/ar5212var.h
index beac93239f9..3906a02a123 100644
--- a/sys/dev/ic/ar5212var.h
+++ b/sys/dev/ic/ar5212var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5212var.h,v 1.10 2005/12/18 17:59:58 reyk Exp $	*/
+/*	$OpenBSD: ar5212var.h,v 1.11 2006/06/05 15:21:43 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
@@ -429,7 +429,7 @@ struct ar5k_ar5212_ini {
 	{ AR5K_INI_FLAG_BOTH, 0x9908, 0x00000000 },			\
 	{ AR5K_INI_FLAG_BOTH, 0x990c, 0x00800000 },			\
 	{ AR5K_INI_FLAG_BOTH, 0x9910, 0x00000001 },			\
-	{ AR5K_INI_FLAG_BOTH, 0x991c, 0x00000c80 },			\
+	{ AR5K_INI_FLAG_BOTH, 0x991c, 0x0000092a },			\
 	{ AR5K_INI_FLAG_BOTH, 0x9920, 0x05100000 },			\
 	{ AR5K_INI_FLAG_BOTH, 0x9928, 0x00000001 },			\
 	{ AR5K_INI_FLAG_BOTH, 0x992c, 0x00000004 },			\
@@ -477,11 +477,11 @@ struct ar5k_ar5212_ini {
 	{ AR5K_INI_FLAG_BOTH, 0xa1f4, 0x10ff10ff },			\
 	{ AR5K_INI_FLAG_BOTH, 0xa1f8, 0x10ff10ff },			\
 	{ AR5K_INI_FLAG_BOTH, 0xa1fc, 0x10ff10ff },			\
-	{ AR5K_INI_FLAG_BOTH, 0xa210, 0x00806333 },			\
-	{ AR5K_INI_FLAG_BOTH, 0xa214, 0x00106c10 },			\
+	{ AR5K_INI_FLAG_BOTH, 0xa210, 0x0080a333 },			\
+	{ AR5K_INI_FLAG_BOTH, 0xa214, 0x00206c10 },			\
 	{ AR5K_INI_FLAG_BOTH, 0xa218, 0x009c4060 },			\
-	{ AR5K_INI_FLAG_BOTH, 0xa21c, 0x1883800a },			\
-	{ AR5K_INI_FLAG_BOTH, 0xa220, 0x018830c6 },			\
+	{ AR5K_INI_FLAG_BOTH, 0xa21c, 0x1483800a },			\
+	{ AR5K_INI_FLAG_BOTH, 0xa220, 0x01831061 },			\
 	{ AR5K_INI_FLAG_BOTH, 0xa224, 0x00000400 },			\
 	{ AR5K_INI_FLAG_BOTH, 0xa228, 0x000001b5 },			\
 	{ AR5K_INI_FLAG_BOTH, 0xa22c, 0x00000000 },			\
@@ -501,6 +501,7 @@ struct ar5k_ar5212_ini {
 	{ AR5K_INI_FLAG_5111, 0x9930, 0x00004883 },			\
 	{ AR5K_INI_FLAG_5111, 0xa204, 0x00000000 },			\
 	{ AR5K_INI_FLAG_5111, 0xa208, 0xd03e6788 },			\
+	{ AR5K_INI_FLAG_5111, 0xa20c, 0x6448416a },			\
 	{ AR5K_INI_FLAG_5111, 0x9b04, 0x00000020 },			\
 	{ AR5K_INI_FLAG_5111, 0x9b08, 0x00000010 },			\
 	{ AR5K_INI_FLAG_5111, 0x9b0c, 0x00000030 },			\
@@ -716,9 +717,13 @@ struct ar5k_ar5212_ini_mode {
 		{ 0, },								\
 		{ 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 }	\
 	} },									\
+	{ 0x9858, AR5K_INI_FLAG_511X, {						\
+		{ 0, },								\
+		{ 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e }	\
+	} },									\
 	{ 0x9860, AR5K_INI_FLAG_511X, {						\
 		{ 0, },								\
-		{ 0x00009d10, 0x00009d10, 0x00009d10, 0x00009d10, 0x00009d10 }	\
+		{ 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d10, 0x00009d10 }	\
 	} },									\
 	{ 0x9864, AR5K_INI_FLAG_511X, {						\
 		{ 0, },								\
@@ -760,10 +765,6 @@ struct ar5k_ar5212_ini_mode {
 		{ 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 },	\
 		{ 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 }	\
 	} },									\
-	{ 0x9858, AR5K_INI_FLAG_BOTH, {						\
-		{ 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e },	\
-		{ 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e }	\
-	} },									\
 	{ 0x985c, AR5K_INI_FLAG_BOTH, {						\
 		{ 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e },	\
 		{ 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e }	\
@@ -777,8 +778,8 @@ struct ar5k_ar5212_ini_mode {
 		{ 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 }	\
 	} },									\
 	{ 0x9944, AR5K_INI_FLAG_BOTH, {						\
-		{ 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 },	\
-		{ 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 }	\
+		{ 0xffb81020, 0xffb81020, 0xffb80d20, 0xffb81020, 0xffb81020 },	\
+		{ 0xffb81020, 0xffb81020, 0xffb80d10, 0xffb81010, 0xffb81010 }	\
 	} },									\
 	{ 0xa204, AR5K_INI_FLAG_5112, {						\
 		{ 0, },								\
@@ -788,8 +789,8 @@ struct ar5k_ar5212_ini_mode {
 		{ 0, },								\
 		{ 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 }	\
 	} },									\
-	{ 0xa20c, AR5K_INI_FLAG_BOTH, {						\
-		{ 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a },	\
+	{ 0xa20c, AR5K_INI_FLAG_5112, {						\
+		{ 0, },								\
 		{ 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 }	\
 	} },									\
 }
diff --git a/sys/dev/ic/ar5xxx.c b/sys/dev/ic/ar5xxx.c
index 32cce815c19..d15dc1a6514 100644
--- a/sys/dev/ic/ar5xxx.c
+++ b/sys/dev/ic/ar5xxx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5xxx.c,v 1.32 2005/12/18 17:59:58 reyk Exp $	*/
+/*	$OpenBSD: ar5xxx.c,v 1.33 2006/06/05 15:21:43 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
@@ -108,6 +108,7 @@ static const struct ar5k_gain_opt ar5112_gain_opt = AR5K_AR5112_GAIN_OPT;
  */
 static const struct ar5k_ini_rf ar5111_rf[] = AR5K_AR5111_INI_RF;
 static const struct ar5k_ini_rf ar5112_rf[] = AR5K_AR5112_INI_RF;
+static const struct ar5k_ini_rf ar5112a_rf[] = AR5K_AR5112A_INI_RF;
 static const struct ar5k_ini_rfgain ar5k_rfg[] = AR5K_INI_RFGAIN;
 
 /*
@@ -833,6 +834,21 @@ ar5k_eeprom_init(struct ath_hal *hal)
 	if (hal->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
 		return (0);
 
+#ifdef notyet
+	/*
+	 * Validate the checksum of the EEPROM date. There are some
+	 * devices with invalid EEPROMs.
+	 */
+	for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
+		AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
+		cksum ^= val;
+	}
+	if (cksum != AR5K_EEPROM_INFO_CKSUM) {
+		AR5K_PRINTF("Invalid EEPROM checksum 0x%04x\n", cksum);
+		return (EINVAL);
+	}
+#endif
+
 	AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(hal->ah_ee_version),
 	    ee_ant_gain);
 
@@ -1426,7 +1442,10 @@ ar5k_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
 		hal->ah_rf_banks_size = sizeof(ar5111_rf);
 		func = ar5k_ar5111_rfregs;
 	} else if (hal->ah_radio == AR5K_AR5112) {
-		hal->ah_rf_banks_size = sizeof(ar5112_rf);
+		if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
+			hal->ah_rf_banks_size = sizeof(ar5112a_rf);
+		else
+			hal->ah_rf_banks_size = sizeof(ar5112_rf);
 		func = ar5k_ar5112_rfregs;
 	} else
 		return (AH_FALSE);
@@ -1547,29 +1566,38 @@ HAL_BOOL
 ar5k_ar5112_rfregs(struct ath_hal *hal, HAL_CHANNEL *channel, u_int mode)
 {
 	struct ar5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
-	const u_int rf_size = AR5K_ELEMENTS(ar5112_rf);
+	u_int rf_size;
 	u_int32_t *rf;
 	int i, obdb = -1, bank = -1;
 	u_int32_t ee_mode;
+	const struct ar5k_ini_rf *rf_ini;
 
 	AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
 
 	rf = hal->ah_rf_banks;
 
+	if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
+		rf_ini = ar5112a_rf;
+		rf_size = AR5K_ELEMENTS(ar5112a_rf);
+	} else {
+		rf_ini = ar5112_rf;
+		rf_size = AR5K_ELEMENTS(ar5112_rf);
+	}
+
 	/* Copy values to modify them */
 	for (i = 0; i < rf_size; i++) {
-		if (ar5112_rf[i].rf_bank >=
+		if (rf_ini[i].rf_bank >=
 		    AR5K_AR5112_INI_RF_MAX_BANKS) {
 			AR5K_PRINT("invalid bank\n");
 			return (AH_FALSE);
 		}
 
-		if (bank != ar5112_rf[i].rf_bank) {
-			bank = ar5112_rf[i].rf_bank;
+		if (bank != rf_ini[i].rf_bank) {
+			bank = rf_ini[i].rf_bank;
 			hal->ah_offset[bank] = i;
 		}
 
-		rf[i] = ar5112_rf[i].rf_value[mode];
+		rf[i] = rf_ini[i].rf_value[mode];
 	}
 
 	if (channel->c_channel_flags & IEEE80211_CHAN_2GHZ) {
@@ -1662,7 +1690,7 @@ void
 ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power)
 {
 	u_int16_t txpower, *rates;
-	int i;
+	int i, min, max, n;
 
 	rates = hal->ah_txpower.txp_rates;
 
@@ -1681,6 +1709,15 @@ ar5k_txpower_table(struct ath_hal *hal, HAL_CHANNEL *channel, int16_t max_power)
 	hal->ah_txpower.txp_max = rates[0];
 	hal->ah_txpower.txp_ofdm = rates[0];
 
-	for (i = 0; i < AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac); i++)
-		hal->ah_txpower.txp_pcdac[i] = AR5K_EEPROM_PCDAC_START;
+	/* Calculate the power table */
+	n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac);
+	min = AR5K_EEPROM_PCDAC_START;
+	max = AR5K_EEPROM_PCDAC_STOP;
+	for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
+		hal->ah_txpower.txp_pcdac[i] =
+#ifdef notyet
+		    min + ((i * (max - min)) / n);
+#else
+		    min;
+#endif
 }
diff --git a/sys/dev/ic/ar5xxx.h b/sys/dev/ic/ar5xxx.h
index b61d4f150b6..65fff657792 100644
--- a/sys/dev/ic/ar5xxx.h
+++ b/sys/dev/ic/ar5xxx.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ar5xxx.h,v 1.30 2005/12/18 17:59:58 reyk Exp $	*/
+/*	$OpenBSD: ar5xxx.h,v 1.31 2006/06/05 15:21:43 reyk Exp $	*/
 
 /*
  * Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
@@ -635,6 +635,7 @@ struct ar5k_gain {
 #define AR5K_EEPROM_INFO_BASE		0x00c0
 #define AR5K_EEPROM_INFO_MAX						\
 	(0x400 - AR5K_EEPROM_INFO_BASE)
+#define AR5K_EEPROM_INFO_CKSUM		0xffff
 #define AR5K_EEPROM_INFO(_n)		(AR5K_EEPROM_INFO_BASE + (_n))
 
 #define AR5K_EEPROM_VERSION		AR5K_EEPROM_INFO(1)
@@ -1197,6 +1198,7 @@ struct ar5k_srev_name {
 	{ "5111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5111 },	\
 	{ "2111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2111 },	\
 	{ "5112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112 },	\
+	{ "5112a",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112A },	\
 	{ "2112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112 },	\
 	{ "2112a",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112A },	\
 	{ "xxxx",	AR5K_VERSION_RAD,	AR5K_SREV_UNKNOWN }	\
@@ -1282,7 +1284,7 @@ typedef HAL_BOOL (ar5k_rfgain_t)
  */
 
 #define AR5K_INIT_MODE				(			\
-	IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM			\
+	IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN			\
 )
 #define AR5K_INIT_TX_LATENCY			502
 #define AR5K_INIT_USEC				39
@@ -1544,6 +1546,117 @@ struct ar5k_ini_rf {
 	{ 3, 0x98dc,								\
 	    { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },	\
 	{ 6, 0x989c,								\
+	    { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },	\
+	{ 6, 0x989c,								\
+	    { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },	\
+	{ 6, 0x989c,								\
+	    { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },	\
+	{ 6, 0x989c,								\
+	    { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },	\
+	{ 6, 0x989c,								\
+	    { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },	\
+	{ 6, 0x989c,								\
+	    { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },	\
+	{ 6, 0x989c,								\
+	    { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },	\
+	{ 6, 0x98d0,								\
+	    { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },	\
+	{ 7, 0x989c,								\
+	    { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },	\
+	{ 7, 0x989c,								\
+	    { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },	\
+	{ 7, 0x989c,								\
+	    { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },	\
+	{ 7, 0x989c,								\
+	    { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },	\
+	{ 7, 0x989c,								\
+	    { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },	\
+	{ 7, 0x989c,								\
+	    { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },	\
+	{ 7, 0x989c,								\
+	    { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },	\
+	{ 7, 0x989c,								\
+	    { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },	\
+	{ 7, 0x989c,								\
+	    { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },	\
+	{ 7, 0x989c,								\
+	    { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },	\
+	{ 7, 0x989c,								\
+	    { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },	\
+	{ 7, 0x989c,								\
+	    { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },	\
+	{ 7, 0x98c4,								\
+	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },	\
+}
+
+#define AR5K_AR5112A_INI_RF	{						\
+	{ 1, 0x98d4,								\
+	    { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },	\
+	{ 2, 0x98d0,								\
+	    { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },	\
+	{ 3, 0x98dc,								\
+	    { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },	\
+	{ 6, 0x989c,								\
 	    { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },	\
 	{ 6, 0x989c,								\
 	    { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },	\
@@ -1580,7 +1693,7 @@ struct ar5k_ini_rf {
 	{ 6, 0x989c,								\
 	    { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },	\
 	{ 6, 0x989c,								\
-	    { 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 } },	\
+	    { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },	\
 	{ 6, 0x989c,								\
 	    { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },	\
 	{ 6, 0x989c,								\
@@ -1604,9 +1717,9 @@ struct ar5k_ini_rf {
 	{ 6, 0x989c,								\
 	    { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },	\
 	{ 6, 0x989c,								\
-	    { 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 } },	\
+	    { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },	\
 	{ 6, 0x989c,								\
-	    { 0x00070019, 0x00070019, 0x00070019, 0x00070019, 0x00070019 } },	\
+	    { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },	\
 	{ 6, 0x989c,								\
 	    { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },	\
 	{ 6, 0x989c,								\