big clean up of commit operation (and register defns)

2 files changed, 278 insertions, 317 deletions

diff --git a/sys/dev/sbus/cs4231.c b/sys/dev/sbus/cs4231.c
index a4d7ef7af44..9b9a3ebbf2a 100644
--- a/sys/dev/sbus/cs4231.c
+++ b/sys/dev/sbus/cs4231.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cs4231.c,v 1.1 2001/09/30 00:45:17 jason Exp $	*/
+/*	$OpenBSD: cs4231.c,v 1.2 2001/09/30 20:58:16 jason Exp $	*/
 
 /*
  * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
@@ -264,7 +264,7 @@ cs4231_attach(parent, self, aux)
 }
 
 /*
- * Write to one of the indirect registers of cs4231.
+ * Write to one of the indexed registers of cs4231.
  */
 void
 cs4231_write(sc, r, v)
@@ -276,7 +276,7 @@ cs4231_write(sc, r, v)
 }
 
 /*
- * Read from one of the indirect registers of cs4231.
+ * Read from one of the indexed registers of cs4231.
  */
 u_int8_t
 cs4231_read(sc, r)
@@ -377,44 +377,6 @@ cs4231_set_speed(sc, argp)
 	return (0);
 }
 
-void
-cs4231_wait(sc)
-	struct cs4231_softc *sc;
-{
-	int tries;
-	u_int8_t ir;
-
-	DELAY(100);
-
-	CS_WRITE(sc, CS4231_IAR, ~(CS_IAR_MCE));
-	tries = CS_TIMEOUT;
-	while (1) {
-		ir = CS_READ(sc, CS4231_IAR);
-		if (ir != CS_IAR_INIT)
-			break;
-		if (--tries == 0)
-			break;
-		DELAY(100);
-	}
-	if (!tries)
-		printf("%s: waited too long to reset iar\n",
-		    sc->sc_dev.dv_xname);
-
-	CS_WRITE(sc, CS4231_IAR, CS_IAR_ERRINIT);
-	tries = CS_TIMEOUT;
-	while (1) {
-		ir = CS_READ(sc, CS4231_IDR);
-		if (ir != CS_ERRINIT_ACI)
-			break;
-		if (--tries == 0)
-			break;
-		DELAY(100);
-	}
-	if (!tries)
-		printf("%s: waited too long to reset errinit\n",
-		    sc->sc_dev.dv_xname);
-}
-
 /*
  * Audio interface functions
  */
@@ -424,6 +386,7 @@ cs4231_open(addr, flags)
 	int flags;
 {
 	struct cs4231_softc *sc = addr;
+	int tries;
 	u_int8_t reg;
 
 	if (sc->sc_open)
@@ -444,11 +407,16 @@ cs4231_open(addr, flags)
 	DELAY(20);
 
 	APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) & (~APC_CSR_CODEC_RESET));
-	CS_WRITE(sc, CS4231_IAR, CS_READ(sc, CS4231_IAR) | CS_IAR_MCE);
 
-	cs4231_wait(sc);
+	for (tries = CS_TIMEOUT;
+	     tries && CS_READ(sc, CS4231_IAR) == CS_IAR_INIT; tries--)
+		DELAY(10);
+	if (tries == 0)
+		printf("%s: timeout waiting for reset\n", sc->sc_dev.dv_xname);
 
-	cs4231_write(sc, CS_IAR_MCE | CS_IAR_MODEID, CS_MODEID_MODE2);
+	/* Turn on cs4231 mode */
+	cs4231_write(sc, CS_IAR_MODEID,
+	    cs4231_read(sc, CS_IAR_MODEID) | CS_MODEID_MODE2);
 
 	reg = cs4231_read(sc, CS_IAR_VID);
 	if ((reg & CS_VID_CHIP_MASK) == CS_VID_CHIP_CS4231) {
@@ -468,16 +436,6 @@ cs4231_open(addr, flags)
 		    reg & CS_VID_VER_MASK);
 	}
 
-	/* XXX TODO: setup some defaults */
-	CS_WRITE(sc, CS4231_IAR, ~(CS_IAR_MCE));
-	cs4231_wait(sc);
-
-	reg = cs4231_read(sc, CS_IAR_MCE | CS_IAR_IC);
-	reg &= ~(CS_IC_CAL_CONV);
-	cs4231_write(sc, CS_IAR_MCE | CS_IAR_IC, reg);
-	CS_WRITE(sc, CS4231_IAR, ~(CS_IAR_MCE));
-	cs4231_wait(sc);
-
 	cs4231_setup_output(sc);
 	return (0);
 }
@@ -709,7 +667,7 @@ cs4231_commit_settings(addr)
 {
 	struct cs4231_softc *sc = (struct cs4231_softc *)addr;
 	int s, tries;
-	u_int8_t fs;
+	u_int8_t r;
 
 	if (sc->sc_need_commit == 0)
 		return (0);
@@ -718,45 +676,52 @@ cs4231_commit_settings(addr)
 
 	cs4231_mute_monitor(sc, 1);
 
-	fs = sc->sc_speed_bits | (sc->sc_format_bits << 5);
+	r = cs4231_read(sc, CS_IAR_IC) | CS_IC_ACAL;
+	CS_WRITE(sc, CS4231_IAR, CS_IAR_MCE);
+	CS_WRITE(sc, CS4231_IAR, CS_IAR_MCE | CS_IAR_IC);
+	CS_WRITE(sc, CS4231_IDR, r);
+
+	r = sc->sc_speed_bits | (sc->sc_format_bits << 5);
 	if (sc->sc_channels == 2)
-		fs |= CS_FSPB_SM_STEREO;
+		r |= CS_FSPB_SM_STEREO;
+
+	printf("commit: %02x\n", r);
 
-	cs4231_write(sc, CS_IAR_MCE | CS_IAR_FSPB, fs);
+	CS_WRITE(sc, CS4231_IAR, CS_IAR_MCE | CS_IAR_FSPB);
+	CS_WRITE(sc, CS4231_IDR, r);
 	CS_READ(sc, CS4231_IDR);
 	CS_READ(sc, CS4231_IDR);
-	tries = 100000;
-	while (1) {
-		if (CS_READ(sc, CS4231_IAR) != CS_IAR_INIT)
-			break;
-		if (--tries == 0)
-			break;
+	tries = CS_TIMEOUT;
+	for (tries = CS_TIMEOUT;
+	     tries && CS_READ(sc, CS4231_IAR) == CS_IAR_INIT; tries--)
 		DELAY(10);
-	}
-	if (tries == 0) {
+	if (tries == 0)
 		printf("%s: timeout committing fspb\n", sc->sc_dev.dv_xname);
-		splx(s);
-		return (0);
-	}
 
-	cs4231_write(sc, CS_IAR_MCE | CS_IAR_CDF, fs);
+	CS_WRITE(sc, CS4231_IAR, CS_IAR_MCE | CS_IAR_CDF);
+	CS_WRITE(sc, CS4231_IDR, r);
 	CS_READ(sc, CS4231_IDR);
 	CS_READ(sc, CS4231_IDR);
-	tries = 100000;
-	while (1) {
-		if (CS_READ(sc, CS4231_IAR) != CS_IAR_INIT)
-			break;
-		if (--tries == 0)
-			break;
+	for (tries = CS_TIMEOUT;
+	     tries && CS_READ(sc, CS4231_IAR) == CS_IAR_INIT; tries--)
 		DELAY(10);
-	}
-	if (tries == 0) {
+	if (tries == 0)
 		printf("%s: timeout committing cdf\n", sc->sc_dev.dv_xname);
-		splx(s);
-		return (0);
-	}
 
-	cs4231_wait(sc);
+	CS_WRITE(sc, CS4231_IAR, 0);
+	for (tries = CS_TIMEOUT;
+	     tries && CS_READ(sc, CS4231_IAR) == CS_IAR_INIT; tries--)
+		DELAY(10);
+	if (tries == 0)
+		printf("%s: timeout waiting for !mce\n", sc->sc_dev.dv_xname);
+
+	CS_WRITE(sc, CS4231_IAR, CS_IAR_ERRINIT);
+	for (tries = CS_TIMEOUT;
+	     tries && CS_READ(sc, CS4231_IDR) & CS_ERRINIT_ACI; tries--)
+		DELAY(10);
+	if (tries == 0)
+		printf("%s: timeout waiting for autocalibration\n",
+		    sc->sc_dev.dv_xname);
 
 	cs4231_mute_monitor(sc, 0);
 
diff --git a/sys/dev/sbus/cs4231reg.h b/sys/dev/sbus/cs4231reg.h
index 44c870234a6..6beb88cb037 100644
--- a/sys/dev/sbus/cs4231reg.h
+++ b/sys/dev/sbus/cs4231reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cs4231reg.h,v 1.1 2001/09/30 00:45:17 jason Exp $	*/
+/*	$OpenBSD: cs4231reg.h,v 1.2 2001/09/30 20:58:16 jason Exp $	*/
 
 /*
  * Copyright (c) 1999 Jason L. Wright (jason@thought.net)
@@ -35,7 +35,7 @@
  * Driver for CS4231 SBUS audio.
  */
 
-#define CS_TIMEOUT	90000
+#define	CS_TIMEOUT	90000
 
 /* CS4231 registers */
 #define	CS4231_IAR	0x0000		/* index address */
@@ -66,60 +66,60 @@
  */
 
 /* cs4231_reg.iar: index address register */
-#define CS_IAR_IR_MASK		0x1f		/* indirect register mask */
-#define CS_IAR_TRD		0x20		/* transfer request disable */
-#define CS_IAR_MCE		0x40		/* mode change enable */
-#define CS_IAR_INIT		0x80		/* initialization */
+#define	CS_IAR_IR_MASK		0x1f		/* indirect register mask */
+#define	CS_IAR_TRD		0x20		/* transfer request disable */
+#define	CS_IAR_MCE		0x40		/* mode change enable */
+#define	CS_IAR_INIT		0x80		/* initialization */
 
 /* indirect register numbers (mode1/mode2) */
-#define CS_IAR_LADCIN		0x00		/* left adc input control */
-#define CS_IAR_RADCIN		0x01		/* right adc input control */
-#define CS_IAR_LACIN1		0x02		/* left aux #1 input control */
-#define CS_IAR_RACIN1		0x03		/* right aux #1 input control */
-#define CS_IAR_LACIN2		0x04		/* left aux #2 input control */
-#define CS_IAR_RACIN2		0x05		/* right aux #2 input control */
-#define CS_IAR_LDACOUT		0x06		/* left dac output control */
-#define CS_IAR_RDACOUT		0x07		/* right dac output control */
-#define CS_IAR_FSPB		0x08		/* fs and playback format */
-#define CS_IAR_IC		0x09		/* interface configuration */
-#define CS_IAR_PC		0x0a		/* pin control */
-#define CS_IAR_ERRINIT		0x0b		/* error status & init */
-#define CS_IAR_MODEID		0x0c		/* mode and id */
-#define CS_IAR_LOOP		0x0d		/* loopback control */
-#define CS_IAR_PBUB		0x0e		/* playback upper base */
-#define CS_IAR_PBLB		0x0f		/* playback lower base */
+#define	CS_IAR_LADCIN		0x00		/* left adc input control */
+#define	CS_IAR_RADCIN		0x01		/* right adc input control */
+#define	CS_IAR_LACIN1		0x02		/* left aux #1 input control */
+#define	CS_IAR_RACIN1		0x03		/* right aux #1 input control */
+#define	CS_IAR_LACIN2		0x04		/* left aux #2 input control */
+#define	CS_IAR_RACIN2		0x05		/* right aux #2 input control */
+#define	CS_IAR_LDACOUT		0x06		/* left dac output control */
+#define	CS_IAR_RDACOUT		0x07		/* right dac output control */
+#define	CS_IAR_FSPB		0x08		/* fs and playback format */
+#define	CS_IAR_IC		0x09		/* interface configuration */
+#define	CS_IAR_PC		0x0a		/* pin control */
+#define	CS_IAR_ERRINIT		0x0b		/* error status & init */
+#define	CS_IAR_MODEID		0x0c		/* mode and id */
+#define	CS_IAR_LOOP		0x0d		/* loopback control */
+#define	CS_IAR_PBUB		0x0e		/* playback upper base */
+#define	CS_IAR_PBLB		0x0f		/* playback lower base */
 
 /* indirect register numbers (mode2 only) */
 
-#define CS_IAR_AFE1		0x10		/* alt feature enable I */
-#define CS_IAR_AFE2		0x11		/* alt feature enable II */
-#define CS_IAR_LLI		0x12		/* left line input control */
-#define CS_IAR_RLI		0x13		/* right line input control */
-#define CS_IAR_TLB		0x14		/* timer lower base */
-#define CS_IAR_TUB		0x15		/* timer upper base */
-#define CS_IAR_reserved1	0x16		/* reserved */
-#define CS_IAR_AFE3		0x17		/* alt feature enable III */
-#define CS_IAR_AFS		0x18		/* alt feature status */
-#define CS_IAR_VID		0x19		/* version id */
-#define CS_IAR_MONO		0x1a		/* mono input/output control */
-#define CS_IAR_reserved2	0x1b		/* reserved */
-#define CS_IAR_CDF		0x1c		/* capture data format */
-#define CS_IAR_reserved3	0x1d		/* reserved */
-#define CS_IAR_CUB		0x1e		/* capture upper base */
-#define CS_IAR_CLB		0x1f		/* capture lower base */
+#define	CS_IAR_AFE1		0x10		/* alt feature enable I */
+#define	CS_IAR_AFE2		0x11		/* alt feature enable II */
+#define	CS_IAR_LLI		0x12		/* left line input control */
+#define	CS_IAR_RLI		0x13		/* right line input control */
+#define	CS_IAR_TLB		0x14		/* timer lower base */
+#define	CS_IAR_TUB		0x15		/* timer upper base */
+#define	CS_IAR_reserved1	0x16		/* reserved */
+#define	CS_IAR_AFE3		0x17		/* alt feature enable III */
+#define	CS_IAR_AFS		0x18		/* alt feature status */
+#define	CS_IAR_VID		0x19		/* version id */
+#define	CS_IAR_MONO		0x1a		/* mono input/output control */
+#define	CS_IAR_reserved2	0x1b		/* reserved */
+#define	CS_IAR_CDF		0x1c		/* capture data format */
+#define	CS_IAR_reserved3	0x1d		/* reserved */
+#define	CS_IAR_CUB		0x1e		/* capture upper base */
+#define	CS_IAR_CLB		0x1f		/* capture lower base */
 
 /* cs4231_reg.idr: index data register */
 /* Contains the data of the indirect register indexed by the iar */
 
 /* cs4231_reg.status: status register */
-#define CS_STATUS_INT		0x01		/* interrupt status(1=active) */
-#define CS_STATUS_PRDY		0x02		/* playback data ready */
-#define CS_STATUS_PL		0x04		/* playback l/r sample */
-#define CS_STATUS_PU		0x08		/* playback up/lw byte needed */
-#define CS_STATUS_SER		0x10		/* sample error */
-#define CS_STATUS_CRDY		0x20		/* capture data ready */
-#define CS_STATUS_CL		0x40		/* capture l/r sample */
-#define CS_STATUS_CU		0x80		/* capture up/lw byte needed */
+#define	CS_STATUS_INT		0x01		/* interrupt status(1=active) */
+#define	CS_STATUS_PRDY		0x02		/* playback data ready */
+#define	CS_STATUS_PL		0x04		/* playback l/r sample */
+#define	CS_STATUS_PU		0x08		/* playback up/lw byte needed */
+#define	CS_STATUS_SER		0x10		/* sample error */
+#define	CS_STATUS_CRDY		0x20		/* capture data ready */
+#define	CS_STATUS_CL		0x40		/* capture l/r sample */
+#define	CS_STATUS_CU		0x80		/* capture up/lw byte needed */
 
 /* cs4231_reg.pior: programmed i/o register */
 /* On write, this is the playback data byte */
@@ -130,175 +130,171 @@
  */
 
 /* Left ADC Input Control: I0 */
-#define CS_LADCIN_GAIN_MASK	0x0f		/* left adc gain */
-#define CS_LADCIN_reserved	0x10		/* reserved */
-#define CS_LADCIN_LMGE		0x20		/* left mic gain enable */
-#define CS_LADCIN_SRC_MASK	0xc0		/* left adc source select */
+#define	CS_LADCIN_GAIN_MASK	0x0f		/* left adc gain */
+#define	CS_LADCIN_reserved	0x10		/* reserved */
+#define	CS_LADCIN_LMGE		0x20		/* left mic gain enable */
+#define	CS_LADCIN_SRC_MASK	0xc0		/* left adc source select */
 
-#define CS_LADCIN_SRC_LINE	0x00		/* left input src: line */
-#define CS_LADCIN_SRC_AUX	0x40		/* left input src: aux */
-#define CS_LADCIN_SRC_MIC	0x80		/* left input src: mic */
-#define CS_LADCIN_SRC_LOOP	0xc0		/* left input src: loopback */
+#define	CS_LADCIN_SRC_LINE	0x00		/* left input src: line */
+#define	CS_LADCIN_SRC_AUX	0x40		/* left input src: aux */
+#define	CS_LADCIN_SRC_MIC	0x80		/* left input src: mic */
+#define	CS_LADCIN_SRC_LOOP	0xc0		/* left input src: loopback */
 
 /* Right ADC Input Control: I1 */
-#define CS_RADCIN_GAIN_MASK	0x0f		/* right adc gain */
-#define CS_RADCIN_reserved	0x10		/* reserved */
-#define CS_RADCIN_LMGE		0x20		/* right mic gain enable */
-#define CS_RADCIN_SRC_MASK	0xc0		/* right adc source select */
+#define	CS_RADCIN_GAIN_MASK	0x0f		/* right adc gain */
+#define	CS_RADCIN_reserved	0x10		/* reserved */
+#define	CS_RADCIN_LMGE		0x20		/* right mic gain enable */
+#define	CS_RADCIN_SRC_MASK	0xc0		/* right adc source select */
 
-#define CS_RADCIN_SRC_LINE	0x00		/* right input src: line */
-#define CS_RADCIN_SRC_AUX	0x40		/* right input src: aux */
-#define CS_RADCIN_SRC_MIC	0x80		/* right input src: mic */
-#define CS_RADCIN_SRC_LOOP	0xc0		/* right input src: loopback */
+#define	CS_RADCIN_SRC_LINE	0x00		/* right input src: line */
+#define	CS_RADCIN_SRC_AUX	0x40		/* right input src: aux */
+#define	CS_RADCIN_SRC_MIC	0x80		/* right input src: mic */
+#define	CS_RADCIN_SRC_LOOP	0xc0		/* right input src: loopback */
 
 /* Left Auxiliary #1 Input Control: I2 */
-#define CS_LACIN1_GAIN_MASK	0x1f		/* left aux #1 mix gain */
-#define CS_LACIN1_reserved1	0x20		/* reserved */
-#define CS_LACIN1_reserved2	0x40		/* reserved */
-#define CS_LACIN1_LX1M		0x80		/* left aux #1 mute */
+#define	CS_LACIN1_GAIN_MASK	0x1f		/* left aux #1 mix gain */
+#define	CS_LACIN1_reserved1	0x20		/* reserved */
+#define	CS_LACIN1_reserved2	0x40		/* reserved */
+#define	CS_LACIN1_LX1M		0x80		/* left aux #1 mute */
 
 /* Right Auxiliary #1 Input Control: I3 */
-#define CS_RACIN1_GAIN_MASK	0x1f		/* right aux #1 mix gain */
-#define CS_RACIN1_reserved1	0x20		/* reserved */
-#define CS_RACIN1_reserved2	0x40		/* reserved */
-#define CS_RACIN1_RX1M		0x80		/* right aux #1 mute */
+#define	CS_RACIN1_GAIN_MASK	0x1f		/* right aux #1 mix gain */
+#define	CS_RACIN1_reserved1	0x20		/* reserved */
+#define	CS_RACIN1_reserved2	0x40		/* reserved */
+#define	CS_RACIN1_RX1M		0x80		/* right aux #1 mute */
 
 /* Left Auxiliary #2 Input Control: I4 */
-#define CS_LACIN2_GAIN_MASK	0x1f		/* left aux #2 mix gain */
-#define CS_LACIN2_reserved1	0x20		/* reserved */
-#define CS_LACIN2_reserved2	0x40		/* reserved */
-#define CS_LACIN2_LX2M		0x80		/* left aux #2 mute */
+#define	CS_LACIN2_GAIN_MASK	0x1f		/* left aux #2 mix gain */
+#define	CS_LACIN2_reserved1	0x20		/* reserved */
+#define	CS_LACIN2_reserved2	0x40		/* reserved */
+#define	CS_LACIN2_LX2M		0x80		/* left aux #2 mute */
 
 /* Right Auxiliary #2 Input Control: I5 */
-#define CS_RACIN2_GAIN_MASK	0x1f		/* right aux #2 mix gain */
-#define CS_RACIN2_reserved1	0x20		/* reserved */
-#define CS_RACIN2_reserved2	0x40		/* reserved */
-#define CS_RACIN2_RX2M		0x80		/* right aux #2 mute */
+#define	CS_RACIN2_GAIN_MASK	0x1f		/* right aux #2 mix gain */
+#define	CS_RACIN2_reserved1	0x20		/* reserved */
+#define	CS_RACIN2_reserved2	0x40		/* reserved */
+#define	CS_RACIN2_RX2M		0x80		/* right aux #2 mute */
 
 /* Left DAC Output Control: I6 */
-#define CS_LDACOUT_LDA_MASK	0x3f		/* left dac attenuator */
-#define CS_LDACOUT_reserved	0x40		/* reserved */
-#define CS_LDACOUT_LDM		0x80		/* left dac mute */
+#define	CS_LDACOUT_LDA_MASK	0x3f		/* left dac attenuator */
+#define	CS_LDACOUT_reserved	0x40		/* reserved */
+#define	CS_LDACOUT_LDM		0x80		/* left dac mute */
 
 /* Right DAC Output Control: I7 */
-#define CS_RDACOUT_RDA_MASK	0x3f		/* right dac attenuator */
-#define CS_RDACOUT_reserved	0x40		/* reserved */
-#define CS_RDACOUT_RDM		0x80		/* right dac mute */
+#define	CS_RDACOUT_RDA_MASK	0x3f		/* right dac attenuator */
+#define	CS_RDACOUT_reserved	0x40		/* reserved */
+#define	CS_RDACOUT_RDM		0x80		/* right dac mute */
 
 /* Fs and Playback Data Format: I8 */
-#define CS_FSPB_C2SL		0x01		/* clock 2 source select */
-#define CS_FSPB_CFS_MASK	0x0e		/* clock frequency div select */
-#define CS_FSPB_SM		0x10		/* stereo/mono select */
-#define CS_FSPB_FMT_MASK	0xe0		/* playback format select */
-
-#define CS_FSPB_C2SL_XTAL1	0x00		/* use 24.576 Mhz crystal */
-#define CS_FSPB_C2SL_XTAL2	0x01		/* use 16.9344 Mhz crystal */
-#define CS_FSPB_SM_MONO		0x00		/* use mono output */
-#define CS_FSPB_SM_STEREO	0x10		/* use stereo output */
-#define CS_FSPB_FMT_ULINEAR	0x00		/* fmt: linear 8bit unsigned */
-#define CS_FSPB_FMT_ULAW	0x20		/* fmt: ulaw, 8bit companded */
-#define CS_FSPB_FMT_LINEAR_LE	0x40		/* fmt: linear 16bit little */
-#define CS_FSPB_FMT_ALAW	0x60		/* fmt: alaw, 8bit companded */
-#define CS_FSPB_FMT_reserved1	0x80		/* fmt: reserved */
-#define CS_FSPB_FMT_ADPCM	0xa0		/* fmt: adpcm 4bit */
-#define CS_FSPB_FMT_LINEAR_BE	0xc0		/* fmt: linear 16bit big */
-#define CS_FSPB_FMT_reserved2	0xe0		/* fmt: reserved */
+#define	CS_FSPB_C2SL		0x01		/* clock 2 source select */
+#define	CS_FSPB_CFS_MASK	0x0e		/* clock frequency div select */
+#define	CS_FSPB_SM		0x10		/* stereo/mono select */
+#define	CS_FSPB_FMT_MASK	0xe0		/* playback format select */
+
+#define	CS_FSPB_C2SL_XTAL1	0x00		/* use 24.576 Mhz crystal */
+#define	CS_FSPB_C2SL_XTAL2	0x01		/* use 16.9344 Mhz crystal */
+#define	CS_FSPB_SM_MONO		0x00		/* use mono output */
+#define	CS_FSPB_SM_STEREO	0x10		/* use stereo output */
+#define	CS_FSPB_FMT_ULINEAR	0x00		/* fmt: linear 8bit unsigned */
+#define	CS_FSPB_FMT_ULAW	0x20		/* fmt: ulaw, 8bit companded */
+#define	CS_FSPB_FMT_LINEAR_LE	0x40		/* fmt: linear 16bit little */
+#define	CS_FSPB_FMT_ALAW	0x60		/* fmt: alaw, 8bit companded */
+#define	CS_FSPB_FMT_reserved1	0x80		/* fmt: reserved */
+#define	CS_FSPB_FMT_ADPCM	0xa0		/* fmt: adpcm 4bit */
+#define	CS_FSPB_FMT_LINEAR_BE	0xc0		/* fmt: linear 16bit big */
+#define	CS_FSPB_FMT_reserved2	0xe0		/* fmt: reserved */
 
 /* Interface Configuration: I9 */
-#define CS_IC_PEN		0x01		/* playback enable */
-#define CS_IC_CEN		0x02		/* capture enable */
-#define CS_IC_SDC		0x04		/* single dma channel */
-#define CS_IC_CAL_MASK		0x18		/* calibration type mask */
-#define CS_IC_reserved		0x20		/* reserved */
-#define CS_IC_PPIO		0x40		/* playback pio enable */
-#define CS_IC_CPIO		0x80		/* capture pio enable */
-
-#define CS_IC_CAL_NONE		0x00		/* no calibration */
-#define CS_IC_CAL_CONV		0x08		/* converter calibration */
-#define CS_IC_CAL_DAC		0x10		/* dac calibration */
-#define CS_IC_CAL_FULL		0x18		/* full calibration */
+#define	CS_IC_PEN		0x01		/* playback enable */
+#define	CS_IC_CEN		0x02		/* capture enable */
+#define	CS_IC_SDC		0x04		/* single dma channel */
+#define	CS_IC_ACAL		0x08		/* auto calibration */
+#define	CS_IC_CAL_MASK		0x18		/* calibration type mask */
+#define	CS_IC_reserved		0x20		/* reserved */
+#define	CS_IC_PPIO		0x40		/* playback pio enable */
+#define	CS_IC_CPIO		0x80		/* capture pio enable */
 
 /* Pin Control: I10 */
-#define CS_PC_reserved1		0x01		/* reserved */
-#define CS_PC_IEN		0x02		/* interrupt enable */
-#define CS_PC_reserved2		0x04		/* reserved */
-#define CS_PC_DEN		0x08		/* dither enable */
-#define CS_PC_reserved3		0x10		/* reserved */
-#define CS_PC_reserved4		0x20		/* reserved */
-#define CS_PC_XCTL_MASK		0xc0		/* xctl control */
+#define	CS_PC_reserved1		0x01		/* reserved */
+#define	CS_PC_IEN		0x02		/* interrupt enable */
+#define	CS_PC_reserved2		0x04		/* reserved */
+#define	CS_PC_DEN		0x08		/* dither enable */
+#define	CS_PC_reserved3		0x10		/* reserved */
+#define	CS_PC_reserved4		0x20		/* reserved */
+#define	CS_PC_XCTL_MASK		0xc0		/* xctl control */
 #define	CS_PC_LINEMUTE		0x40		/* mute line */
 #define	CS_PC_HDPHMUTE		0x80		/* mute headphone */
-#define CS_PC_XCTL0		0x40		/* set xtcl0 to 1 */
-#define CS_PC_XCTL1		0x80		/* set xctl1 to 1 */
+#define	CS_PC_XCTL0		0x40		/* set xtcl0 to 1 */
+#define	CS_PC_XCTL1		0x80		/* set xctl1 to 1 */
 
 /* Error Status and Initialization: I11 */
-#define CS_ERRINIT_ORL_MASK	0x03		/* overrange left detect */
-#define CS_ERRINIT_ORR_MASK	0x0c		/* overrange right detect */
-#define CS_ERRINIT_DRQ		0x10		/* drq status */
-#define CS_ERRINIT_ACI		0x20		/* auto-calibrate in progress */
-#define CS_ERRINIT_PUR		0x40		/* playback underrun */
-#define CS_ERRINIT_COR		0x80		/* capture overrun */
-
-#define CS_ERRINIT_ORL_VLOW	0x00		/* < -1.5 dB from full scale */
-#define CS_ERRINIT_ORL_LOW	0x01		/* -1.5dB < x < 0dB */
-#define CS_ERRINIT_ORL_HIGH	0x02		/* 0dB < x < 1.5dB */
-#define CS_ERRINIT_ORL_VHIGH	0x03		/* > 1.5dB overrange */
-#define CS_ERRINIT_ORR_VLOW	0x00		/* < -1.5 dB from full scale */
-#define CS_ERRINIT_ORR_LOW	0x04		/* -1.5dB < x < 0dB */
-#define CS_ERRINIT_ORR_HIGH	0x08		/* 0dB < x < 1.5dB */
-#define CS_ERRINIT_ORR_VHIGH	0x0c		/* > 1.5dB overrange */
+#define	CS_ERRINIT_ORL_MASK	0x03		/* overrange left detect */
+#define	CS_ERRINIT_ORR_MASK	0x0c		/* overrange right detect */
+#define	CS_ERRINIT_DRQ		0x10		/* drq status */
+#define	CS_ERRINIT_ACI		0x20		/* auto-calibrate in progress */
+#define	CS_ERRINIT_PUR		0x40		/* playback underrun */
+#define	CS_ERRINIT_COR		0x80		/* capture overrun */
+
+#define	CS_ERRINIT_ORL_VLOW	0x00		/* < -1.5 dB from full scale */
+#define	CS_ERRINIT_ORL_LOW	0x01		/* -1.5dB < x < 0dB */
+#define	CS_ERRINIT_ORL_HIGH	0x02		/* 0dB < x < 1.5dB */
+#define	CS_ERRINIT_ORL_VHIGH	0x03		/* > 1.5dB overrange */
+#define	CS_ERRINIT_ORR_VLOW	0x00		/* < -1.5 dB from full scale */
+#define	CS_ERRINIT_ORR_LOW	0x04		/* -1.5dB < x < 0dB */
+#define	CS_ERRINIT_ORR_HIGH	0x08		/* 0dB < x < 1.5dB */
+#define	CS_ERRINIT_ORR_VHIGH	0x0c		/* > 1.5dB overrange */
 
 /* Mode and ID: I12 */
-#define CS_MODEID_ID_MASK	0x0f		/* Codec ID */
-#define CS_MODEID_reserved1	0x10		/* reserved */
-#define CS_MODEID_reserved2	0x20		/* reserved */
-#define CS_MODEID_MODE2		0x40		/* enable mode2 operation */
+#define	CS_MODEID_ID_MASK	0x0f		/* Codec ID */
+#define	CS_MODEID_reserved1	0x10		/* reserved */
+#define	CS_MODEID_reserved2	0x20		/* reserved */
+#define	CS_MODEID_MODE2		0x40		/* enable mode2 operation */
 
-#define CS_MODEID_CS4231	0x0a		/* 1010 == cs4231 */
+#define	CS_MODEID_CS4231	0x0a		/* 1010 == cs4231 */
 
 /* Loopback Control: I13 */
-#define CS_LOOP_LBE		0x01		/* loopback enable */
-#define CS_LOOP_reserved	0x02		/* reserved */
-#define CS_LOOP_LBA_MASK	0xfc		/* loopback attenuation */
+#define	CS_LOOP_LBE		0x01		/* loopback enable */
+#define	CS_LOOP_reserved	0x02		/* reserved */
+#define	CS_LOOP_LBA_MASK	0xfc		/* loopback attenuation */
 
 /* Playback Upper Base: I14 */
 
 /* Playback Lower Base: I15 */
 
 /* Alternate Feature Enable I: I16 */
-#define CS_AFE1_DACZ		0x01		/* dac zero */
-#define CS_AFE1_SPE		0x02		/* serial port enable */
-#define CS_AFE1_SF_MASK		0x0c		/* serial format mask */
-#define CS_AFE1_PMCE		0x10		/* playback mode change enbl */
-#define CS_AFE1_CMCE		0x20		/* capture mode change enable */
-#define CS_AFE1_TE		0x40		/* timer enable */
-#define CS_AFE1_OLB		0x80		/* output level bit */
-
-#define CS_AFE1_SF_64E		0x00		/* 64 bit enhanced */
-#define CS_AFE1_SF_64		0x04		/* 64 bit */
-#define CS_AFE1_SF_32		0x08		/* 32 bit */
-#define CS_AFE1_SF_reserved	0x0c		/* reserved */
-#define CS_AFE1_OLB_2		0x00		/* full scale 2Vpp (-3dB) */
-#define CS_AFE1_OLB_28		0x80		/* full scale 2.8Vpp (0dB) */
+#define	CS_AFE1_DACZ		0x01		/* dac zero */
+#define	CS_AFE1_SPE		0x02		/* serial port enable */
+#define	CS_AFE1_SF_MASK		0x0c		/* serial format mask */
+#define	CS_AFE1_PMCE		0x10		/* playback mode change enbl */
+#define	CS_AFE1_CMCE		0x20		/* capture mode change enable */
+#define	CS_AFE1_TE		0x40		/* timer enable */
+#define	CS_AFE1_OLB		0x80		/* output level bit */
+
+#define	CS_AFE1_SF_64E		0x00		/* 64 bit enhanced */
+#define	CS_AFE1_SF_64		0x04		/* 64 bit */
+#define	CS_AFE1_SF_32		0x08		/* 32 bit */
+#define	CS_AFE1_SF_reserved	0x0c		/* reserved */
+#define	CS_AFE1_OLB_2		0x00		/* full scale 2Vpp (-3dB) */
+#define	CS_AFE1_OLB_28		0x80		/* full scale 2.8Vpp (0dB) */
 
 /* Alternate Feature Enable II: I17 */
-#define CS_AFE2_HPF		0x01		/* high pass filter enable */
-#define CS_AFE2_XTALE		0x02		/* crystal enable */
-#define CS_AFE2_APAR		0x04		/* ADPCM pb accumulator reset */
-#define CS_AFE2_reserved	0x08		/* reserved */
-#define CS_AFE2_TEST_MASK	0xf0		/* factory test bits */
+#define	CS_AFE2_HPF		0x01		/* high pass filter enable */
+#define	CS_AFE2_XTALE		0x02		/* crystal enable */
+#define	CS_AFE2_APAR		0x04		/* ADPCM pb accumulator reset */
+#define	CS_AFE2_reserved	0x08		/* reserved */
+#define	CS_AFE2_TEST_MASK	0xf0		/* factory test bits */
 
 /* Left Line Input Control: I18 */
-#define CS_LLI_GAIN_MASK	0x1f		/* left line mix gain mask */
-#define CS_LLI_reserved1	0x20		/* reserved */
-#define CS_LLI_reserved2	0x40		/* reserved */
-#define CS_LLI_MUTE		0x80		/* left line mute */
+#define	CS_LLI_GAIN_MASK	0x1f		/* left line mix gain mask */
+#define	CS_LLI_reserved1	0x20		/* reserved */
+#define	CS_LLI_reserved2	0x40		/* reserved */
+#define	CS_LLI_MUTE		0x80		/* left line mute */
 
 /* Right Line Input Control: I19 */
-#define CS_RLI_GAIN_MASK	0x1f		/* right line mix gain mask */
-#define CS_RLI_reserved1	0x20		/* reserved */
-#define CS_RLI_reserved2	0x40		/* reserved */
-#define CS_RLI_MUTE		0x80		/* right line mute */
+#define	CS_RLI_GAIN_MASK	0x1f		/* right line mix gain mask */
+#define	CS_RLI_reserved1	0x20		/* reserved */
+#define	CS_RLI_reserved2	0x40		/* reserved */
+#define	CS_RLI_MUTE		0x80		/* right line mute */
 
 /* Timer Lower Base: I20 */
 
@@ -307,52 +303,52 @@
 /* Reserved: I22 */
 
 /* Alternate Feature Enable III: I23 */
-#define CS_AFE3_ACF		0x01		/* ADPCM capture freeze */
-#define CS_AFE3_reserved	0xfe		/* reserved bits */
+#define	CS_AFE3_ACF		0x01		/* ADPCM capture freeze */
+#define	CS_AFE3_reserved	0xfe		/* reserved bits */
 
 /* Alternate Feature Status: I24 */
-#define CS_AFS_PU		0x01		/* playback underrun */
-#define CS_AFS_PO		0x02		/* playback overrun */
-#define CS_AFS_CO		0x04		/* capture underrun */
-#define CS_AFS_CU		0x08		/* capture overrun */
-#define CS_AFS_PI		0x10		/* playback interrupt */
-#define CS_AFS_CI		0x20		/* capture interrupt */
-#define CS_AFS_TI		0x40		/* timer interrupt */
-#define CS_AFS_reserved		0x80		/* reserved */
+#define	CS_AFS_PU		0x01		/* playback underrun */
+#define	CS_AFS_PO		0x02		/* playback overrun */
+#define	CS_AFS_CO		0x04		/* capture underrun */
+#define	CS_AFS_CU		0x08		/* capture overrun */
+#define	CS_AFS_PI		0x10		/* playback interrupt */
+#define	CS_AFS_CI		0x20		/* capture interrupt */
+#define	CS_AFS_TI		0x40		/* timer interrupt */
+#define	CS_AFS_reserved		0x80		/* reserved */
 
 /* Version ID: I25 */
-#define CS_VID_CHIP_MASK	0x07		/* chip id mask */
-#define CS_VID_VER_MASK		0xe0		/* version number mask */
+#define	CS_VID_CHIP_MASK	0x07		/* chip id mask */
+#define	CS_VID_VER_MASK		0xe0		/* version number mask */
 
-#define CS_VID_CHIP_CS4231	0x00		/* CS4231 and CS4231A */
-#define CS_VID_VER_CS4231	0x80		/* CS4231 */
-#define CS_VID_VER_CS4232	0x82		/* CS4232 */
-#define CS_VID_VER_CS4231A	0xa0		/* CS4231A */
+#define	CS_VID_CHIP_CS4231	0x00		/* CS4231 and CS4231A */
+#define	CS_VID_VER_CS4231	0x80		/* CS4231 */
+#define	CS_VID_VER_CS4232	0x82		/* CS4232 */
+#define	CS_VID_VER_CS4231A	0xa0		/* CS4231A */
 
 /* Mono Input & Output Control: I26 */
-#define CS_MONO_MIA_MASK	0x0f		/* mono attenuation mask */
-#define CS_MONO_reserved	0x10		/* reserved */
-#define CS_MONO_MBY		0x20		/* mono bypass */
-#define CS_MONO_MOM		0x40		/* mono output mute */
-#define CS_MONO_MIM		0x80		/* mono input mute */
+#define	CS_MONO_MIA_MASK	0x0f		/* mono attenuation mask */
+#define	CS_MONO_reserved	0x10		/* reserved */
+#define	CS_MONO_MBY		0x20		/* mono bypass */
+#define	CS_MONO_MOM		0x40		/* mono output mute */
+#define	CS_MONO_MIM		0x80		/* mono input mute */
 
 /* Reserved: I27 */
 
 /* Capture Data Format: I28 */
-#define CS_CDF_reserved		0x0f		/* reserved bits */
-#define CS_CDF_SM		0x10		/* Stereo/mono select */
-#define CS_CDF_FMT_MASK		0xe0		/* capture format mask */
-
-#define CS_CDF_SM_MONO		0x00		/* select mono capture */
-#define CS_CDF_SM_STEREO	0x10		/* select stereo capture */
-#define CS_CDF_FMT_ULINEAR	0x00		/* fmt: linear 8bit unsigned */
-#define CS_CDF_FMT_ULAW		0x20		/* fmt: ulaw, 8bit companded */
-#define CS_CDF_FMT_LINEAR_LE	0x40		/* fmt: linear 16bit little */
-#define CS_CDF_FMT_ALAW		0x60		/* fmt: alaw, 8bit companded */
-#define CS_CDF_FMT_reserved1	0x80		/* fmt: reserved */
-#define CS_CDF_FMT_ADPCM	0xa0		/* fmt: adpcm 4bit */
-#define CS_CDF_FMT_LINEAR_BE	0xc0		/* fmt: linear 16bit big */
-#define CS_CDF_FMT_reserved2	0xe0		/* fmt: reserved */
+#define	CS_CDF_reserved		0x0f		/* reserved bits */
+#define	CS_CDF_SM		0x10		/* Stereo/mono select */
+#define	CS_CDF_FMT_MASK		0xe0		/* capture format mask */
+
+#define	CS_CDF_SM_MONO		0x00		/* select mono capture */
+#define	CS_CDF_SM_STEREO	0x10		/* select stereo capture */
+#define	CS_CDF_FMT_ULINEAR	0x00		/* fmt: linear 8bit unsigned */
+#define	CS_CDF_FMT_ULAW		0x20		/* fmt: ulaw, 8bit companded */
+#define	CS_CDF_FMT_LINEAR_LE	0x40		/* fmt: linear 16bit little */
+#define	CS_CDF_FMT_ALAW		0x60		/* fmt: alaw, 8bit companded */
+#define	CS_CDF_FMT_reserved1	0x80		/* fmt: reserved */
+#define	CS_CDF_FMT_ADPCM	0xa0		/* fmt: adpcm 4bit */
+#define	CS_CDF_FMT_LINEAR_BE	0xc0		/* fmt: linear 16bit big */
+#define	CS_CDF_FMT_reserved2	0xe0		/* fmt: reserved */
 
 /* Reserved: I29 */
 
@@ -363,30 +359,30 @@
 /*
  * APC DMA Register definitions
  */
-#define APC_CSR_RESET		0x00000001	/* reset */
-#define APC_CSR_CDMA_GO		0x00000004	/* capture dma go */
-#define APC_CSR_PDMA_GO		0x00000008	/* playback dma go */
-#define APC_CSR_CODEC_RESET	0x00000020	/* codec reset */
-#define APC_CSR_CPAUSE		0x00000040	/* capture dma pause */
-#define APC_CSR_PPAUSE		0x00000080	/* playback dma pause */
-#define APC_CSR_CMIE		0x00000100	/* capture pipe empty enb */
-#define APC_CSR_CMI		0x00000200	/* capture pipe empty intr */
-#define APC_CSR_CD		0x00000400	/* capture nva dirty */
-#define APC_CSR_CM		0x00000800	/* capture data lost */
-#define APC_CSR_PMIE		0x00001000	/* pb pipe empty intr enable */
-#define APC_CSR_PD		0x00002000	/* pb nva dirty */
-#define APC_CSR_PM		0x00004000	/* pb pipe empty */
-#define APC_CSR_PMI		0x00008000	/* pb pipe empty interrupt */
-#define APC_CSR_EIE		0x00010000	/* error interrupt enable */
-#define APC_CSR_CIE		0x00020000	/* capture intr enable */
-#define APC_CSR_PIE		0x00040000	/* playback intr enable */
-#define APC_CSR_GIE		0x00080000	/* general intr enable */
-#define APC_CSR_EI		0x00100000	/* error interrupt */
-#define APC_CSR_CI		0x00200000	/* capture interrupt */
-#define APC_CSR_PI		0x00400000	/* playback interrupt */
-#define APC_CSR_GI		0x00800000	/* general interrupt */
-
-#define APC_CSR_PLAY			( \
+#define	APC_CSR_RESET		0x00000001	/* reset */
+#define	APC_CSR_CDMA_GO		0x00000004	/* capture dma go */
+#define	APC_CSR_PDMA_GO		0x00000008	/* playback dma go */
+#define	APC_CSR_CODEC_RESET	0x00000020	/* codec reset */
+#define	APC_CSR_CPAUSE		0x00000040	/* capture dma pause */
+#define	APC_CSR_PPAUSE		0x00000080	/* playback dma pause */
+#define	APC_CSR_CMIE		0x00000100	/* capture pipe empty enb */
+#define	APC_CSR_CMI		0x00000200	/* capture pipe empty intr */
+#define	APC_CSR_CD		0x00000400	/* capture nva dirty */
+#define	APC_CSR_CM		0x00000800	/* capture data lost */
+#define	APC_CSR_PMIE		0x00001000	/* pb pipe empty intr enable */
+#define	APC_CSR_PD		0x00002000	/* pb nva dirty */
+#define	APC_CSR_PM		0x00004000	/* pb pipe empty */
+#define	APC_CSR_PMI		0x00008000	/* pb pipe empty interrupt */
+#define	APC_CSR_EIE		0x00010000	/* error interrupt enable */
+#define	APC_CSR_CIE		0x00020000	/* capture intr enable */
+#define	APC_CSR_PIE		0x00040000	/* playback intr enable */
+#define	APC_CSR_GIE		0x00080000	/* general intr enable */
+#define	APC_CSR_EI		0x00100000	/* error interrupt */
+#define	APC_CSR_CI		0x00200000	/* capture interrupt */
+#define	APC_CSR_PI		0x00400000	/* playback interrupt */
+#define	APC_CSR_GI		0x00800000	/* general interrupt */
+
+#define	APC_CSR_PLAY			( \
 		APC_CSR_EI		| \
 	 	APC_CSR_GIE		| \
 		APC_CSR_PIE		| \
@@ -394,14 +390,14 @@
 		APC_CSR_PDMA_GO		| \
 		APC_CSR_PMIE		)
 
-#define APC_CSR_CAPTURE			( \
+#define	APC_CSR_CAPTURE			( \
 		APC_CSR_EI		| \
 	 	APC_CSR_GIE		| \
 		APC_CSR_CIE		| \
 		APC_CSR_EIE		| \
 		APC_CSR_CDMA_GO	)
 
-#define APC_CSR_PLAY_PAUSE		(~( \
+#define	APC_CSR_PLAY_PAUSE		(~( \
 		APC_CSR_PPAUSE		| \
 		APC_CSR_GI		| \
 		APC_CSR_PI		| \
@@ -412,7 +408,7 @@
 		APC_CSR_CMI		| \
 		APC_CSR_CMIE		) )
 
-#define APC_CSR_CAPTURE_PAUSE		(~( \
+#define	APC_CSR_CAPTURE_PAUSE		(~( \
 		APC_CSR_PPAUSE		| \
 		APC_CSR_GI		| \
 		APC_CSR_PI		| \
@@ -423,7 +419,7 @@
 		APC_CSR_CMI		| \
 		APC_CSR_CMIE		) )
 
-#define APC_CSR_INTR_MASK		( \
+#define	APC_CSR_INTR_MASK		( \
 		APC_CSR_GI		| \
 		APC_CSR_PI		| \
 		APC_CSR_CI		| \