diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2021-05-05 01:28:39 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2021-05-05 01:28:39 +0000 |
| commit | 987ebd1275f79c3aa01a4959b6849959b45584bc (patch) | |
| tree | 64b4cf8ac882be4c7380a147c002b012edb421ce | |
| parent | 441bbc2199fb67dfca7920d7185f1ef11844f14a (diff) | |
riscv: Assert that SUM is not set in SSTATUS for exceptions.
From John Baldwin
6a3a6fe34bf36b6e745b3e9ad1a991de057729c7 in FreeBSD
ok kettenis@ mlarkin@
| -rw-r--r-- | sys/arch/riscv64/riscv64/trap.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sys/arch/riscv64/riscv64/trap.c b/sys/arch/riscv64/riscv64/trap.c index fd84ee9a6ae..7e1286ee013 100644 --- a/sys/arch/riscv64/riscv64/trap.c +++ b/sys/arch/riscv64/riscv64/trap.c @@ -67,6 +67,9 @@ do_trap_supervisor(struct trapframe *frame) KASSERTMSG((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) == SSTATUS_SPP, "Came from S mode with interrupts enabled"); + KASSERTMSG((csr_read(sstatus) & (SSTATUS_SUM)) == 0, + "Came from S mode with SUM enabled"); + if (frame->tf_scause & EXCP_INTR) { /* Interrupt */ riscv_cpu_intr(frame); @@ -119,6 +122,9 @@ do_trap_user(struct trapframe *frame) KASSERTMSG((csr_read(sstatus) & (SSTATUS_SPP | SSTATUS_SIE)) == 0, "Came from U mode with interrupts enabled"); + KASSERTMSG((csr_read(sstatus) & (SSTATUS_SUM)) == 0, + "Came from U mode with SUM enabled"); + /* Save fpu context before (possibly) calling interrupt handler. * Could end up context switching in interrupt handler. */ |