rtw cleanup

5 files changed, 174 insertions, 1180 deletions

diff --git a/sys/dev/ic/rtwphy.c b/sys/dev/ic/rtwphy.c
deleted file mode 100644
index d27fbbc23f1..00000000000
--- a/sys/dev/ic/rtwphy.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/*	$OpenBSD: rtwphy.c,v 1.1 2004/12/29 01:02:31 jsg Exp $	*/
-/* $NetBSD: rtwphy.c,v 1.2 2004/12/12 06:37:59 dyoung Exp $ */
-/*-
- * Copyright (c) 2004, 2005 David Young.  All rights reserved.
- *
- * Programmed for NetBSD by David Young.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of David Young may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
- * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * Control the Philips SA2400 RF front-end and the baseband processor
- * built into the Realtek RTL8180.
- */
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/socket.h>
-#include <sys/systm.h>
-#include <sys/types.h>
-#include <sys/malloc.h>
-
-#include <machine/bus.h>
-
-#include <net/if.h>
-#include <net/if_media.h>
-#include <netinet/in.h>
-#include <netinet/if_ether.h>
-
-#include <net80211/ieee80211_var.h>
-#include <net80211/ieee80211_compat.h>
-#include <net80211/ieee80211_radiotap.h>
-
-#include <dev/ic/rtwreg.h>
-#include <dev/ic/max2820reg.h>
-#include <dev/ic/sa2400reg.h>
-#include <dev/ic/rtwvar.h>
-#include <dev/ic/rtwphyio.h>
-#include <dev/ic/rtwphy.h>
-
-int rtw_bbp_preinit(struct rtw_regs *, u_int, int, u_int);
-int rtw_bbp_init(struct rtw_regs *, struct rtw_bbpset *, int,
-    int, u_int8_t, u_int);
-
-void verify_syna(u_int, u_int32_t);
-
-int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
-int rtw_sa2400_txpower(struct rtw_rf *, u_int8_t);
-int rtw_sa2400_tune(struct rtw_rf *, u_int);
-int rtw_sa2400_manrx_init(struct rtw_sa2400 *);
-int rtw_sa2400_vcocal_start(struct rtw_sa2400 *, int);
-int rtw_sa2400_vco_calibration(struct rtw_sa2400 *);
-int rtw_sa2400_filter_calibration(struct rtw_sa2400 *);
-int rtw_sa2400_dc_calibration(struct rtw_sa2400 *);
-int rtw_sa2400_agc_init(struct rtw_sa2400 *);
-void rtw_sa2400_destroy(struct rtw_rf *);
-int rtw_sa2400_calibrate(struct rtw_rf *, u_int);
-int rtw_sa2400_init(struct rtw_rf *, u_int, u_int8_t,
-    enum rtw_pwrstate);
-
-int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate);
-void rtw_max2820_destroy(struct rtw_rf *);
-int rtw_max2820_init(struct rtw_rf *, u_int, u_int8_t,
-    enum rtw_pwrstate);
-int rtw_max2820_txpower(struct rtw_rf *, u_int8_t);
-int rtw_max2820_tune(struct rtw_rf *, u_int);
-
-int
-rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb,
-    u_int freq)
-{
-	u_int antatten = antatten0;
-	if (dflantb)
-		antatten |= RTW_BBP_ANTATTEN_DFLANTB;
-	if (freq == 2484) /* channel 14 */
-		antatten |= RTW_BBP_ANTATTEN_CHAN14;
-	return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten);
-}
-
-int
-rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv,
-    int dflantb, u_int8_t cs_threshold, u_int freq)
-{
-	int rc;
-	u_int32_t sys2, sys3;
-
-	sys2 = bb->bb_sys2;
-	if (antdiv)
-		sys2 |= RTW_BBP_SYS2_ANTDIV;
-	sys3 = bb->bb_sys3 |
-	    LSHIFT(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK);
-
-#define	RTW_BBP_WRITE_OR_RETURN(reg, val) \
-	if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
-		return rc;
-
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1,		bb->bb_sys1);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC,		bb->bb_txagc);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET,		bb->bb_lnadet);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI,	bb->bb_ifagcini);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT,	bb->bb_ifagclimit);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET,	bb->bb_ifagcdet);
-
-	if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0)
-		return rc;
-
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL,		bb->bb_trl);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2,		sys2);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3,		sys3);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM,	bb->bb_chestlim);
-	RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM,	bb->bb_chsqlim);
-	return 0;
-}
-
-int
-rtw_sa2400_txpower(struct rtw_rf *rf, u_int8_t opaque_txpower)
-{
-	struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
-	struct rtw_rfbus *bus = &sa->sa_bus;
-
-	return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX,
-	    opaque_txpower);
-}
-
-/* make sure we're using the same settings as the reference driver */
-void
-verify_syna(u_int freq, u_int32_t val)
-{
-	u_int32_t expected_val = ~val;
-
-	switch (freq) {
-	case 2412:
-		expected_val = 0x0000096c; /* ch 1 */
-		break;
-	case 2417:
-		expected_val = 0x00080970; /* ch 2 */
-		break;
-	case 2422:
-		expected_val = 0x00100974; /* ch 3 */
-		break;
-	case 2427:
-		expected_val = 0x00180978; /* ch 4 */
-		break;
-	case 2432:
-		expected_val = 0x00000980; /* ch 5 */
-		break;
-	case 2437:
-		expected_val = 0x00080984; /* ch 6 */
-		break;
-	case 2442:
-		expected_val = 0x00100988; /* ch 7 */
-		break;
-	case 2447:
-		expected_val = 0x0018098c; /* ch 8 */
-		break;
-	case 2452:
-		expected_val = 0x00000994; /* ch 9 */
-		break;
-	case 2457:
-		expected_val = 0x00080998; /* ch 10 */
-		break;
-	case 2462:
-		expected_val = 0x0010099c; /* ch 11 */
-		break;
-	case 2467:
-		expected_val = 0x001809a0; /* ch 12 */
-		break;
-        case 2472:
-		expected_val = 0x000009a8; /* ch 13 */
-		break;
-        case 2484:
-		expected_val = 0x000009b4; /* ch 14 */
-		break;
-	}
-	KASSERT(val == expected_val);
-}
-
-/* freq is in MHz */
-int
-rtw_sa2400_tune(struct rtw_rf *rf, u_int freq)
-{
-	struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
-	struct rtw_rfbus *bus = &sa->sa_bus;
-	int rc;
-	u_int32_t syna, synb, sync;
-
-	/* XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz.
-	 *
-	 * The channel spacing (5MHz) is not divisible by 4MHz, so
-	 * we set the fractional part of N to compensate.
-	 */
-	int n = freq / 4, nf = (freq % 4) * 2;
-
-	syna = LSHIFT(nf, SA2400_SYNA_NF_MASK) | LSHIFT(n, SA2400_SYNA_N_MASK);
-	verify_syna(freq, syna);
-
-	/* Divide the 44MHz crystal down to 4MHz. Set the fractional
-	 * compensation charge pump value to agree with the fractional
-	 * modulus.
-	 */
-	synb = LSHIFT(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL |
-	    SA2400_SYNB_ON | SA2400_SYNB_ONE |
-	    LSHIFT(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */
-
-	sync = SA2400_SYNC_CP_NORMAL;
-
-	if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA,
-	    syna)) != 0)
-		return rc;
-	if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB,
-	    synb)) != 0)
-		return rc;
-	if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC,
-	    sync)) != 0)
-		return rc;
-	return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0);
-}
-
-int
-rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
-{
-	struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
-	struct rtw_rfbus *bus = &sa->sa_bus;
-	u_int32_t opmode;
-	opmode = SA2400_OPMODE_DEFAULTS;
-	switch (power) {
-	case RTW_ON:
-		opmode |= SA2400_OPMODE_MODE_TXRX;
-		break;
-	case RTW_SLEEP:
-		opmode |= SA2400_OPMODE_MODE_WAIT;
-		break;
-	case RTW_OFF:
-		opmode |= SA2400_OPMODE_MODE_SLEEP;
-		break;
-	}
-
-	if (sa->sa_digphy)
-		opmode |= SA2400_OPMODE_DIGIN;
-
-	return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
-	    opmode);
-}
-
-int
-rtw_sa2400_manrx_init(struct rtw_sa2400 *sa)
-{
-	u_int32_t manrx;
-
-	/* XXX we are not supposed to be in RXMGC mode when we do
-	 * this?
-	 */
-	manrx = SA2400_MANRX_AHSN;
-	manrx |= SA2400_MANRX_TEN;
-	manrx |= LSHIFT(1023, SA2400_MANRX_RXGAIN_MASK);
-
-	return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX,
-	    manrx);
-}
-
-int
-rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start)
-{
-	u_int32_t opmode;
-
-	opmode = SA2400_OPMODE_DEFAULTS;
-	if (start)
-		opmode |= SA2400_OPMODE_MODE_VCOCALIB;
-	else
-		opmode |= SA2400_OPMODE_MODE_SLEEP;
-
-	if (sa->sa_digphy)
-		opmode |= SA2400_OPMODE_DIGIN;
-
-	return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
-	    opmode);
-}
-
-int
-rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa)
-{
-	int rc;
-	/* calibrate VCO */
-	if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0)
-		return rc;
-	DELAY(2200);	/* 2.2 milliseconds */
-	/* XXX superfluous: SA2400 automatically entered SLEEP mode. */
-	return rtw_sa2400_vcocal_start(sa, 0);
-}
-
-int
-rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa)
-{
-	u_int32_t opmode;
-
-	opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB;
-	if (sa->sa_digphy)
-		opmode |= SA2400_OPMODE_DIGIN;
-
-	return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
-	    opmode);
-}
-
-int
-rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa)
-{
-	struct rtw_rf *rf = &sa->sa_rf;
-	int rc;
-	u_int32_t dccal;
-
-	(*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 1);
-
-	dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX;
-
-	rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
-	    dccal);
-	if (rc != 0)
-		return rc;
-
-	DELAY(5);	/* DCALIB after being in Tx mode for 5
-			 * microseconds
-			 */
-
-	dccal &= ~SA2400_OPMODE_MODE_MASK; 
-	dccal |= SA2400_OPMODE_MODE_DCALIB;
-
-	rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE,
-	   dccal);
-	if (rc != 0)
-		return rc;
-
-	DELAY(20);	/* calibration takes at most 20 microseconds */
-
-	(*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 0);
-
-	return 0;
-}
-
-int
-rtw_sa2400_agc_init(struct rtw_sa2400 *sa)
-{
-	u_int32_t agc;
-
-	agc = LSHIFT(25, SA2400_AGC_MAXGAIN_MASK);
-	agc |= LSHIFT(7, SA2400_AGC_BBPDELAY_MASK);
-	agc |= LSHIFT(15, SA2400_AGC_LNADELAY_MASK);
-	agc |= LSHIFT(27, SA2400_AGC_RXONDELAY_MASK);
-
-	return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC,
-	    agc);
-}
-
-void
-rtw_sa2400_destroy(struct rtw_rf *rf)
-{
-	struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
-	memset(sa, 0, sizeof(*sa));
-	free(sa, M_DEVBUF);
-}
-
-int
-rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq)
-{
-	struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
-	int i, rc;
-
-	/* XXX reference driver calibrates VCO twice. Is it a bug? */
-	for (i = 0; i < 2; i++) {
-		if ((rc = rtw_sa2400_vco_calibration(sa)) != 0)
-			return rc;
-	}
-	/* VCO calibration erases synthesizer registers, so re-tune */
-	if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
-		return rc;
-	if ((rc = rtw_sa2400_filter_calibration(sa)) != 0)
-		return rc;
-	/* analog PHY needs DC calibration */
-	if (!sa->sa_digphy)
-		return rtw_sa2400_dc_calibration(sa);
-	return 0;
-}
-
-int
-rtw_sa2400_init(struct rtw_rf *rf, u_int freq, u_int8_t opaque_txpower,
-    enum rtw_pwrstate power)
-{
-	struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf;
-	int rc;
-
-	if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0)
-		return rc;
-
-	/* skip configuration if it's time to sleep or to power-down. */
-	if (power == RTW_SLEEP || power == RTW_OFF)
-		return rtw_sa2400_pwrstate(rf, power);
-
-	/* go to sleep for configuration */
-	if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0)
-		return rc;
-
-	if ((rc = rtw_sa2400_tune(rf, freq)) != 0)
-		return rc;
-	if ((rc = rtw_sa2400_agc_init(sa)) != 0)
-		return rc;
-	if ((rc = rtw_sa2400_manrx_init(sa)) != 0)
-		return rc;
-
-	if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0)
-		return rc;
-
-	/* enter Tx/Rx mode */
-	return rtw_sa2400_pwrstate(rf, power);
-}
-
-struct rtw_rf *
-rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy)
-{
-	struct rtw_sa2400 *sa;
-	struct rtw_rfbus *bus;
-	struct rtw_rf *rf;
-	struct rtw_bbpset *bb;
-
-	sa = malloc(sizeof(*sa), M_DEVBUF, M_NOWAIT);
-	if (sa == NULL)
-		return NULL;
-	bzero(sa, sizeof(struct rtw_sa2400));
-
-	sa->sa_digphy = digphy;
-
-	rf = &sa->sa_rf;
-	bus = &sa->sa_bus;
-
-	rf->rf_init = rtw_sa2400_init;
-	rf->rf_destroy = rtw_sa2400_destroy;
-	rf->rf_txpower = rtw_sa2400_txpower;
-	rf->rf_tune = rtw_sa2400_tune;
-	rf->rf_pwrstate = rtw_sa2400_pwrstate;
-	bb = &rf->rf_bbpset;
-
-	/* XXX magic */
-	bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC;
-	bb->bb_chestlim =	0x00;
-	bb->bb_chsqlim =	0xa0;
-	bb->bb_ifagcdet =	0x64;
-	bb->bb_ifagcini =	0x90;
-	bb->bb_ifagclimit =	0x1a;
-	bb->bb_lnadet =		0xe0;
-	bb->bb_sys1 =		0x98;
-	bb->bb_sys2 =		0x47;
-	bb->bb_sys3 =		0x90;
-	bb->bb_trl =		0x88;
-	bb->bb_txagc =		0x38;
-
-	bus->b_regs = regs;
-	bus->b_write = rf_write;
-
-	return &sa->sa_rf;
-}
-
-/* freq is in MHz */
-int
-rtw_max2820_tune(struct rtw_rf *rf, u_int freq)
-{
-	struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
-	struct rtw_rfbus *bus = &mx->mx_bus;
-
-	if (freq < 2400 || freq > 2499)
-		return -1;
-
-	return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL,
-	    LSHIFT(freq - 2400, MAX2820_CHANNEL_CF_MASK));
-}
-
-void
-rtw_max2820_destroy(struct rtw_rf *rf)
-{
-	struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
-	memset(mx, 0, sizeof(*mx));
-	free(mx, M_DEVBUF);
-}
-
-int
-rtw_max2820_init(struct rtw_rf *rf, u_int freq, u_int8_t opaque_txpower,
-    enum rtw_pwrstate power)
-{
-	struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
-	struct rtw_rfbus *bus = &mx->mx_bus;
-	int rc;
-
-	if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST,
-	    MAX2820_TEST_DEFAULT)) != 0)
-		return rc;
-
-	if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE,
-	    MAX2820_ENABLE_DEFAULT)) != 0)
-		return rc;
-
-	/* skip configuration if it's time to sleep or to power-down. */
-	if ((rc = rtw_max2820_pwrstate(rf, power)) != 0)
-		return rc;
-	else if (power == RTW_OFF || power == RTW_SLEEP)
-		return 0;
-
-	if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH,
-	    MAX2820_SYNTH_R_44MHZ)) != 0)
-		return rc;
-
-	if ((rc = rtw_max2820_tune(rf, freq)) != 0)
-		return rc;
-
-	/* XXX The MAX2820 datasheet indicates that 1C and 2C should not
-	 * be changed from 7, however, the reference driver sets them
-	 * to 4 and 1, respectively.
-	 */
-	if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE,
-	    MAX2820_RECEIVE_DL_DEFAULT |
-	    LSHIFT(4, MAX2820A_RECEIVE_1C_MASK) |
-	    LSHIFT(1, MAX2820A_RECEIVE_2C_MASK))) != 0)
-		return rc;
-
-	return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT,
-	    MAX2820_TRANSMIT_PA_DEFAULT);
-}
-
-int
-rtw_max2820_txpower(struct rtw_rf *rf, u_int8_t opaque_txpower)
-{
-	/* TBD */
-	return 0;
-}
-
-int
-rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power)
-{
-	uint32_t enable;
-	struct rtw_max2820 *mx;
-	struct rtw_rfbus *bus;
-
-	mx = (struct rtw_max2820 *)rf;
-	bus = &mx->mx_bus;
-
-	switch (power) {
-	case RTW_OFF:
-	case RTW_SLEEP:
-	default:
-		enable = 0x0;
-		break;
-	case RTW_ON:
-		enable = MAX2820_ENABLE_DEFAULT;
-		break;
-	}
-	return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable);
-}
-
-struct rtw_rf *
-rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a)
-{
-	struct rtw_max2820 *mx;
-	struct rtw_rfbus *bus;
-	struct rtw_rf *rf;
-	struct rtw_bbpset *bb;
-
-	mx = malloc(sizeof(*mx), M_DEVBUF, M_NOWAIT);
-	if (mx == NULL)
-		return NULL;
-	bzero(mx, sizeof(struct rtw_max2820));
-
-	mx->mx_is_a = is_a;
-
-	rf = &mx->mx_rf;
-	bus = &mx->mx_bus;
-
-	rf->rf_init = rtw_max2820_init;
-	rf->rf_destroy = rtw_max2820_destroy;
-	rf->rf_txpower = rtw_max2820_txpower;
-	rf->rf_tune = rtw_max2820_tune;
-	rf->rf_pwrstate = rtw_max2820_pwrstate;
-	bb = &rf->rf_bbpset;
-
-	/* XXX magic */
-	bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC;
-	bb->bb_chestlim =	0;
-	bb->bb_chsqlim =	159;
-	bb->bb_ifagcdet =	100;
-	bb->bb_ifagcini =	144;
-	bb->bb_ifagclimit =	26;
-	bb->bb_lnadet =		248;
-	bb->bb_sys1 =		136;
-	bb->bb_sys2 =		71;
-	bb->bb_sys3 =		155;
-	bb->bb_trl =		136;
-	bb->bb_txagc =		8;
-
-	bus->b_regs = regs;
-	bus->b_write = rf_write;
-
-	return &mx->mx_rf;
-}
-
-/* freq is in MHz */
-int
-rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, u_int8_t opaque_txpower,
-    u_int8_t cs_threshold, u_int freq, int antdiv, int dflantb,
-    enum rtw_pwrstate power)
-{
-	int rc;
-	RTW_DPRINTF(RTW_DEBUG_PHY,
-	    ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u "
-	     "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq,
-	     antdiv, dflantb, rtw_pwrstate_string(power)));
-
-	/* XXX is this really necessary? */
-	if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
-		return rc;
-	if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb,
-	    freq)) != 0)
-		return rc;
-	if ((rc = rtw_rf_tune(rf, freq)) != 0)
-		return rc;
-	/* initialize RF  */
-	if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0)
-		return rc;
-#if 0	/* what is this redundant tx power setting here for? */
-	if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0)
-		return rc;
-#endif
-	return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb,
-	    cs_threshold, freq);
-}
diff --git a/sys/dev/ic/rtwphy.h b/sys/dev/ic/rtwphy.h
deleted file mode 100644
index bade057ff08..00000000000
--- a/sys/dev/ic/rtwphy.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*	$OpenBSD: rtwphy.h,v 1.2 2004/12/30 06:31:57 jsg Exp $	*/
-/* $NetBSD: rtw.c,v 1.35 2004/12/29 01:13:07 dyoung Exp $ */
-/*-
- * Copyright (c) 2004, 2005 David Young.  All rights reserved.
- *
- * Programmed for NetBSD by David Young.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of David Young may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
- * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-#ifndef _DEV_IC_RTWPHY_H
-#define _DEV_IC_RTWPHY_H
-
-struct rtw_rf *rtw_sa2400_create(struct rtw_regs *, rtw_rf_write_t, int);
-struct rtw_rf *rtw_max2820_create(struct rtw_regs *, rtw_rf_write_t, int);
-
-int rtw_phy_init(struct rtw_regs *, struct rtw_rf *, u_int8_t, u_int8_t, u_int,
-    int, int, enum rtw_pwrstate);
-
-#endif /* _DEV_IC_RTWPHY_H */
diff --git a/sys/dev/ic/rtwphyio.c b/sys/dev/ic/rtwphyio.c
deleted file mode 100644
index 6aa44e466d9..00000000000
--- a/sys/dev/ic/rtwphyio.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*	$OpenBSD: rtwphyio.c,v 1.3 2005/01/19 11:29:27 jsg Exp $	*/
-/* $NetBSD: rtwphyio.c,v 1.4 2004/12/25 06:58:37 dyoung Exp $ */
-/*-
- * Copyright (c) 2004, 2005 David Young.  All rights reserved.
- *
- * Programmed for NetBSD by David Young.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of David Young may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
- * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-/*
- * Control input/output with the Philips SA2400 RF front-end and
- * the baseband processor built into the Realtek RTL8180.
- */
-
-#include <sys/cdefs.h>
-#include <sys/param.h>
-#include <sys/socket.h>
-#include <sys/systm.h>
-#include <sys/types.h>
-
-#include <machine/bus.h>
-
-#include <net/if.h>
-#include <net/if_media.h>
-#include <netinet/in.h>
-#include <netinet/if_ether.h>
-
-#include <net80211/ieee80211_var.h>
-#include <net80211/ieee80211_compat.h>
-#include <net80211/ieee80211_radiotap.h>
-
-#include <dev/ic/rtwreg.h>
-#include <dev/ic/max2820reg.h>
-#include <dev/ic/sa2400reg.h>
-#include <dev/ic/si4136reg.h>
-#include <dev/ic/rtwvar.h>
-#include <dev/ic/rtwphyio.h>
-#include <dev/ic/rtwphy.h>
-
-u_int32_t rtw_grf5101_host_crypt(u_int, u_int32_t);
-u_int32_t rtw_maxim_swizzle(u_int, uint32_t);
-u_int32_t rtw_grf5101_mac_crypt(u_int, u_int32_t);
-void rtw_rf_hostbangbits(struct rtw_regs *, u_int32_t, int, u_int);
-int rtw_rf_macbangbits(struct rtw_regs *, u_int32_t);
-const char *rtw_rfchipid_string(enum rtw_rfchipid);
-
-static int rtw_macbangbits_timeout = 100;
-
-u_int8_t
-rtw_bbp_read(struct rtw_regs *regs, u_int addr)
-{
-	KASSERT((addr & ~PRESHIFT(RTW_BB_ADDR_MASK)) == 0);
-	RTW_WRITE(regs, RTW_BB,
-	    LSHIFT(addr, RTW_BB_ADDR_MASK) | RTW_BB_RD_MASK | RTW_BB_WR_MASK);
-	delay(10);	/* XXX */
-	RTW_WBR(regs, RTW_BB, RTW_BB);
-	return MASK_AND_RSHIFT(RTW_READ(regs, RTW_BB), RTW_BB_RD_MASK);
-}
-
-int
-rtw_bbp_write(struct rtw_regs *regs, u_int addr, u_int val)
-{
-#define	BBP_WRITE_ITERS	50
-#define	BBP_WRITE_DELAY	1
-	int i;
-	u_int32_t wrbbp, rdbbp;
-
-	RTW_DPRINTF(RTW_DEBUG_PHYIO,
-	    ("%s: bbp[%u] <- %u\n", __func__, addr, val));
-
-	KASSERT((addr & ~PRESHIFT(RTW_BB_ADDR_MASK)) == 0);
-	KASSERT((val & ~PRESHIFT(RTW_BB_WR_MASK)) == 0);
-
-	wrbbp = LSHIFT(addr, RTW_BB_ADDR_MASK) | RTW_BB_WREN |
-	    LSHIFT(val, RTW_BB_WR_MASK) | RTW_BB_RD_MASK,
-
-	rdbbp = LSHIFT(addr, RTW_BB_ADDR_MASK) |
-	    RTW_BB_WR_MASK | RTW_BB_RD_MASK;
-
-	RTW_DPRINTF(RTW_DEBUG_PHYIO,
-	    ("%s: rdbbp = %#08x, wrbbp = %#08x\n", __func__, rdbbp, wrbbp));
-
-	for (i = BBP_WRITE_ITERS; --i >= 0; ) {
-		RTW_RBW(regs, RTW_BB, RTW_BB);
-		RTW_WRITE(regs, RTW_BB, wrbbp);
-		RTW_SYNC(regs, RTW_BB, RTW_BB);
-		RTW_WRITE(regs, RTW_BB, rdbbp);
-		RTW_SYNC(regs, RTW_BB, RTW_BB);
-		delay(BBP_WRITE_DELAY);	/* 1 microsecond */
-		if (MASK_AND_RSHIFT(RTW_READ(regs, RTW_BB),
-		                    RTW_BB_RD_MASK) == val) {
-			RTW_DPRINTF(RTW_DEBUG_PHYIO,
-			    ("%s: finished in %dus\n", __func__,
-			    BBP_WRITE_DELAY * (BBP_WRITE_ITERS - i)));
-			return 0;
-		}
-		delay(BBP_WRITE_DELAY);	/* again */
-	}
-	printf("%s: timeout\n", __func__);
-	return -1;
-}
-
-/* Help rtw_rf_hostwrite bang bits to RF over 3-wire interface. */
-void
-rtw_rf_hostbangbits(struct rtw_regs *regs, u_int32_t bits, int lo_to_hi,
-    u_int nbits)
-{
-	int i;
-	u_int32_t mask, reg;
-
-	KASSERT(nbits <= 32);
-
-	RTW_DPRINTF(RTW_DEBUG_PHYIO,
-	    ("%s: %u bits, %#08x, %s\n", __func__, nbits, bits,
-	    (lo_to_hi) ? "lo to hi" : "hi to lo"));
-
-	reg = RTW_PHYCFG_HST;
-	RTW_WRITE(regs, RTW_PHYCFG, reg);
-	RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG);
-
-	if (lo_to_hi)
-		mask = 0x1;
-	else
-		mask = 1 << (nbits - 1);
-
-	for (i = 0; i < nbits; i++) {
-		RTW_DPRINTF(RTW_DEBUG_PHYBITIO,
-		    ("%s: bits %#08x mask %#08x -> bit %#08x\n",
-		    __func__, bits, mask, bits & mask));
-
-		if ((bits & mask) != 0)
-			reg |= RTW_PHYCFG_HST_DATA;
-		else
-			reg &= ~RTW_PHYCFG_HST_DATA;
-
-		reg |= RTW_PHYCFG_HST_CLK;
-		RTW_WRITE(regs, RTW_PHYCFG, reg);
-		RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG);
-
-		DELAY(2);	/* arbitrary delay */
-
-		reg &= ~RTW_PHYCFG_HST_CLK;
-		RTW_WRITE(regs, RTW_PHYCFG, reg);
-		RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG);
-
-		if (lo_to_hi)
-			mask <<= 1;
-		else
-			mask >>= 1;
-	}
-
-	reg |= RTW_PHYCFG_HST_EN;
-	KASSERT((reg & RTW_PHYCFG_HST_CLK) == 0);
-	RTW_WRITE(regs, RTW_PHYCFG, reg);
-	RTW_SYNC(regs, RTW_PHYCFG, RTW_PHYCFG);
-}
-
-/* Help rtw_rf_macwrite: tell MAC to bang bits to RF over the 3-wire
- * interface.
- */
-int
-rtw_rf_macbangbits(struct rtw_regs *regs, u_int32_t reg)
-{
-	int i;
-
-	RTW_DPRINTF(RTW_DEBUG_PHY, ("%s: %#08x\n", __func__, reg));
-
-	RTW_WRITE(regs, RTW_PHYCFG, RTW_PHYCFG_MAC_POLL | reg);
-
-	RTW_WBR(regs, RTW_PHYCFG, RTW_PHYCFG);
-
-	for (i = rtw_macbangbits_timeout; --i >= 0; delay(1)) {
-		if ((RTW_READ(regs, RTW_PHYCFG) & RTW_PHYCFG_MAC_POLL) == 0) {
-			RTW_DPRINTF(RTW_DEBUG_PHY,
-			    ("%s: finished in %dus\n", __func__,
-			    rtw_macbangbits_timeout - i));
-			return 0;
-		}
-		RTW_RBR(regs, RTW_PHYCFG, RTW_PHYCFG);	/* XXX paranoia? */
-	}
-
-	printf("%s: RTW_PHYCFG_MAC_POLL still set.\n", __func__);
-	return -1;
-}
-
-u_int32_t
-rtw_grf5101_host_crypt(u_int addr, u_int32_t val)
-{
-	/* TBD */
-	return 0;
-}
-
-u_int32_t
-rtw_grf5101_mac_crypt(u_int addr, u_int32_t val)
-{
-	u_int32_t data_and_addr;
-#define EXTRACT_NIBBLE(d, which) (((d) >> (4 * (which))) & 0xf)
-	static u_int8_t caesar[16] = {0x0, 0x8, 0x4, 0xc,
-	                              0x2, 0xa, 0x6, 0xe,
-				      0x1, 0x9, 0x5, 0xd,
-				      0x3, 0xb, 0x7, 0xf};
-
-	data_and_addr =  caesar[EXTRACT_NIBBLE(val, 2)] |
-	                (caesar[EXTRACT_NIBBLE(val, 1)] <<  4) |
-	                (caesar[EXTRACT_NIBBLE(val, 0)] <<  8) |
-	                (caesar[(addr >> 1) & 0xf]      << 12) |
-	                ((addr & 0x1)                   << 16) |
-	                (caesar[EXTRACT_NIBBLE(val, 3)] << 24);
-	return LSHIFT(data_and_addr,
-	    RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK|RTW_PHYCFG_MAC_PHILIPS_DATA_MASK);
-#undef EXTRACT_NIBBLE
-}
-
-const char *
-rtw_rfchipid_string(enum rtw_rfchipid rfchipid)
-{
-	switch (rfchipid) {
-	case RTW_RFCHIPID_MAXIM:
-		return "Maxim";
-	case RTW_RFCHIPID_PHILIPS:
-		return "Philips";
-	case RTW_RFCHIPID_GCT:
-		return "GCT";
-	case RTW_RFCHIPID_RFMD:
-		return "RFMD";
-	case RTW_RFCHIPID_INTERSIL:
-		return "Intersil";
-	default:
-		return "unknown";
-	}
-}
-
-/* Bang bits over the 3-wire interface. */
-int
-rtw_rf_hostwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid,
-    u_int addr, u_int32_t val)
-{
-	u_int nbits;
-	int lo_to_hi;
-	u_int32_t bits;
-
-	RTW_DPRINTF(RTW_DEBUG_PHYIO, ("%s: %s[%u] <- %#08x\n", __func__,
-	    rtw_rfchipid_string(rfchipid), addr, val));
-
-	switch (rfchipid) {
-	case RTW_RFCHIPID_MAXIM:
-		nbits = 16;
-		lo_to_hi = 0;
-		bits = LSHIFT(val, MAX2820_TWI_DATA_MASK) |
-		       LSHIFT(addr, MAX2820_TWI_ADDR_MASK);
-		break;
-	case RTW_RFCHIPID_PHILIPS:
-		KASSERT((addr & ~PRESHIFT(SA2400_TWI_ADDR_MASK)) == 0);
-		KASSERT((val & ~PRESHIFT(SA2400_TWI_DATA_MASK)) == 0);
-		bits = LSHIFT(val, SA2400_TWI_DATA_MASK) |
-		       LSHIFT(addr, SA2400_TWI_ADDR_MASK) | SA2400_TWI_WREN;
-		nbits = 32;
-		lo_to_hi = 1;
-		break;
-	case RTW_RFCHIPID_GCT:
-	case RTW_RFCHIPID_RFMD:
-		KASSERT((addr & ~PRESHIFT(SI4126_TWI_ADDR_MASK)) == 0);
-		KASSERT((val & ~PRESHIFT(SI4126_TWI_DATA_MASK)) == 0);
-		if (rfchipid == RTW_RFCHIPID_GCT)
-			bits = rtw_grf5101_host_crypt(addr, val);
-		else {
-			bits = LSHIFT(val, SI4126_TWI_DATA_MASK) |
-			       LSHIFT(addr, SI4126_TWI_ADDR_MASK);
-		}
-		nbits = 22;
-		lo_to_hi = 0;
-		break;
-	case RTW_RFCHIPID_INTERSIL:
-	default:
-		printf("%s: unknown rfchipid %d\n", __func__, rfchipid);
-		return -1;
-	}
-
-	rtw_rf_hostbangbits(regs, bits, lo_to_hi, nbits);
-
-	return 0;
-}
-
-u_int32_t
-rtw_maxim_swizzle(u_int addr, u_int32_t val)
-{
-	u_int32_t hidata, lodata;
-
-	KASSERT((val & ~(RTW_MAXIM_LODATA_MASK|RTW_MAXIM_HIDATA_MASK)) == 0);
-	lodata = MASK_AND_RSHIFT(val, RTW_MAXIM_LODATA_MASK);
-	hidata = MASK_AND_RSHIFT(val, RTW_MAXIM_HIDATA_MASK);
-	return LSHIFT(lodata, RTW_PHYCFG_MAC_MAXIM_LODATA_MASK) |
-	    LSHIFT(hidata, RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK) |
-	    LSHIFT(addr, RTW_PHYCFG_MAC_MAXIM_ADDR_MASK);
-}
-
-/* Tell the MAC what to bang over the 3-wire interface. */
-int
-rtw_rf_macwrite(struct rtw_regs *regs, enum rtw_rfchipid rfchipid,
-    u_int addr, u_int32_t val)
-{
-	u_int32_t reg;
-
-	RTW_DPRINTF(RTW_DEBUG_PHYIO, ("%s: %s[%u] <- %#08x\n", __func__,
-	    rtw_rfchipid_string(rfchipid), addr, val));
-
-	switch (rfchipid) {
-	case RTW_RFCHIPID_GCT:
-		reg = rtw_grf5101_mac_crypt(addr, val);
-		break;
-	case RTW_RFCHIPID_MAXIM:
-		reg = rtw_maxim_swizzle(addr, val);
-		break;
-	default:		/* XXX */
-	case RTW_RFCHIPID_PHILIPS:
-		KASSERT(
-		    (addr & ~PRESHIFT(RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK)) == 0);
-		KASSERT(
-		    (val & ~PRESHIFT(RTW_PHYCFG_MAC_PHILIPS_DATA_MASK)) == 0);
-
-		reg = LSHIFT(addr, RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK) |
-		      LSHIFT(val, RTW_PHYCFG_MAC_PHILIPS_DATA_MASK);
-	}
-
-	switch (rfchipid) {
-	case RTW_RFCHIPID_GCT:
-	case RTW_RFCHIPID_MAXIM:
-	case RTW_RFCHIPID_RFMD:
-		reg |= RTW_PHYCFG_MAC_RFTYPE_RFMD;
-		break;
-	case RTW_RFCHIPID_INTERSIL:
-		reg |= RTW_PHYCFG_MAC_RFTYPE_INTERSIL;
-		break;
-	case RTW_RFCHIPID_PHILIPS:
-		reg |= RTW_PHYCFG_MAC_RFTYPE_PHILIPS;
-		break;
-	default:
-		printf("%s: unknown rfchipid %d\n", __func__, rfchipid);
-		return -1;
-	}
-
-	return rtw_rf_macbangbits(regs, reg);
-}
diff --git a/sys/dev/ic/rtwphyio.h b/sys/dev/ic/rtwphyio.h
deleted file mode 100644
index 90c44c072ff..00000000000
--- a/sys/dev/ic/rtwphyio.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*	$OpenBSD: rtwphyio.h,v 1.1 2004/12/29 01:02:31 jsg Exp $	*/
-/* $NetBSD: rtwphyio.h,v 1.1 2004/09/26 02:29:15 dyoung Exp $ */
-/*-
- * Copyright (c) 2004, 2005 David Young.  All rights reserved.
- *
- * Programmed for NetBSD by David Young.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of David Young may not be used to endorse or promote
- *    products derived from this software without specific prior
- *    written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
- * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
- * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- */
-#ifndef _DEV_IC_RTWPHYIO_H
-#define _DEV_IC_RTWPHYIO_H
-
-int rtw_rf_hostwrite(struct rtw_regs *, enum rtw_rfchipid, u_int, u_int32_t);
-int rtw_rf_macwrite(struct rtw_regs *, enum rtw_rfchipid, u_int, u_int32_t);
-u_int8_t rtw_bbp_read(struct rtw_regs *, u_int);
-int rtw_bbp_write(struct rtw_regs *, u_int, u_int);
-
-#endif /* _DEV_IC_RTWPHYIO_H */
diff --git a/sys/dev/ic/rtwreg.h b/sys/dev/ic/rtwreg.h
index 12dae298573..ea759e9cc8a 100644
--- a/sys/dev/ic/rtwreg.h
+++ b/sys/dev/ic/rtwreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rtwreg.h,v 1.5 2005/02/14 12:49:29 jsg Exp $	*/
+/*	$OpenBSD: rtwreg.h,v 1.6 2005/05/29 02:56:33 reyk Exp $	*/
 /*	$NetBSD: rtwreg.h,v 1.12 2005/01/16 11:50:43 dyoung Exp $	*/
 /*-
  * Copyright (c) 2004, 2005 David Young.  All rights reserved.
@@ -78,7 +78,7 @@
 
 #endif /* _BIT_TWIDDLE */
 
-/* RTL8180L Host Control and Status Registers */
+/* RTL8180/RTL8185 Host Control and Status Registers */
 
 #define RTW_IDR0	0x00	/* ID Register: MAC addr, 6 bytes.
 				 * Auto-loaded from EEPROM. Read by byte,
@@ -105,20 +105,25 @@
 				 */
 
 #define RTW_BRSR	0x2c	/* Basic Rate Set Register, 16b */
-#define	RTW_BRSR_BPLCP	BIT(8)	/* 1: use short PLCP header for CTS/ACK packet,
-				 * 0: use long PLCP header
-				 */
-#define RTW_BRSR_MBR8180_MASK	BITS(1,0)	/* Maximum Basic Service Rate */
-#define RTW_BRSR_MBR8180_1MBPS	LSHIFT(0, RTW_BRSR_MBR8180_MASK)
-#define RTW_BRSR_MBR8180_2MBPS	LSHIFT(1, RTW_BRSR_MBR8180_MASK)
-#define RTW_BRSR_MBR8180_5MBPS	LSHIFT(2, RTW_BRSR_MBR8180_MASK)
-#define RTW_BRSR_MBR8180_11MBPS	LSHIFT(3, RTW_BRSR_MBR8180_MASK)
-
-/* 8181 and 8180 docs conflict! */
-#define RTW_BRSR_MBR8181_1MBPS	BIT(0)
-#define RTW_BRSR_MBR8181_2MBPS	BIT(1)
-#define RTW_BRSR_MBR8181_5MBPS	BIT(2)
-#define RTW_BRSR_MBR8181_11MBPS	BIT(3)
+#define	RTW8180_BRSR_BPLCP	BIT(8)	/* 1: Short PLCP CTS/ACK header */
+#define RTW8180_BRSR_MBR_MASK	BITS(1,0)	/* Basic Service Rate */
+#define RTW8180_BRSR_MBR_1MBPS	LSHIFT(0, RTW8180_BRSR_MBR_MASK)
+#define RTW8180_BRSR_MBR_2MBPS	LSHIFT(1, RTW8180_BRSR_MBR_MASK)
+#define RTW8180_BRSR_MBR_5MBPS	LSHIFT(2, RTW8180_BRSR_MBR_MASK)
+#define RTW8180_BRSR_MBR_11MBPS	LSHIFT(3, RTW8180_BRSR_MBR_MASK)
+#define RTW8185_BRSR_MBR_MASK	BITS(11, 0)	/* Basic Service Rate */
+#define RTW8185_BRSR_MBR_1MBPS	BIT(0)
+#define RTW8185_BRSR_MBR_2MBPS	BIT(1)
+#define RTW8185_BRSR_MBR_5MBPS	BIT(2)
+#define RTW8185_BRSR_MBR_11MBPS	BIT(3)
+#define RTW8185_BRSR_MBR_6MBPS	BIT(4)
+#define RTW8185_BRSR_MBR_9MBPS	BIT(5)
+#define RTW8185_BRSR_MBR_12MBPS	BIT(6)
+#define RTW8185_BRSR_MBR_18MBPS	BIT(7)
+#define RTW8185_BRSR_MBR_24MBPS	BIT(8)
+#define RTW8185_BRSR_MBR_36MBPS	BIT(9)
+#define RTW8185_BRSR_MBR_48MBPS	BIT(10)
+#define RTW8185_BRSR_MBR_54MBPS	BIT(11)
 
 #define RTW_BSSID	0x2e
 /* BSSID, 6 bytes */
@@ -131,6 +136,36 @@
 #define RTW_BSSID4	(RTW_BSSID3 + 1)	/* BSSID[4], 8b */
 #define RTW_BSSID5	(RTW_BSSID4 + 1)	/* BSSID[5], 8b */
 
+#define RTW8185_RR		0x34	/* Response Rate Register, 8b */
+#define RTW8185_RR_MAX		BIT(7, 4)
+#define RTW8185_RR_MAX_1MPBS	LSHIFT(0, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_2MPBS	LSHIFT(1, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_5MPBS	LSHIFT(2, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_11MPBS	LSHIFT(3, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_6MPBS	LSHIFT(4, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_9MPBS	LSHIFT(5, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_12MPBS	LSHIFT(6, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_18MPBS	LSHIFT(7, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_24MPBS	LSHIFT(8, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_36MPBS	LSHIFT(9, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_48MPBS	LSHIFT(10, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MAX_54MPBS	LSHIFT(11, RTW8185_RR_MAX_MASK)
+#define RTW8185_RR_MIN_MASK	BIT(3, 0)
+#define RTW8185_RR_MIN_1MPBS	LSHIFT(0, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_2MPBS	LSHIFT(1, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_5MPBS	LSHIFT(2, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_11MPBS	LSHIFT(3, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_6MPBS	LSHIFT(4, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_9MPBS	LSHIFT(5, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_12MPBS	LSHIFT(6, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_18MPBS	LSHIFT(7, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_24MPBS	LSHIFT(8, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_36MPBS	LSHIFT(9, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_48MPBS	LSHIFT(10, RTW8185_RR_MIN_MASK)
+#define RTW8185_RR_MIN_54MPBS	LSHIFT(11, RTW8185_RR_MIN_MASK)
+
+#define RTW8185_EIFS_TIMER	0x35	/* Extended IFS Register, 16b ??? */
+
 #define	RTW_CR		0x37	/* Command Register, 8b */
 #define	RTW_CR_RST	BIT(4)	/* Reset: host sets to 1 to disable
 				 * transmitter & receiver, reinitialize FIFO.
@@ -204,17 +239,21 @@
 #define RTW_TCR_SWSEQ	BIT(30)	/* 1: host assigns 802.11 sequence number,
 				 * 0: hardware assigns sequence number
 				 */
+#define RTW8185_TCR_NOPROBERSPTO	BIT(29)	/* No Probe Rsp timeout */
 /* Hardware version ID, read-only */
-#define RTW_TCR_HWVERID_MASK	BITS(29, 25)
-#define RTW_TCR_HWVERID_D	LSHIFT(26, RTW_TCR_HWVERID_MASK)
-#define RTW_TCR_HWVERID_F	LSHIFT(27, RTW_TCR_HWVERID_MASK)
-#define RTW_TCR_HWVERID_RTL8180	RTW_TCR_HWVERID_F
-
+#define RTW_TCR_HWVERID_MASK		BITS(27, 25)
+#define RTW_TCR_HWVERID_RTL8180D	BIT(26)
+#define RTW_TCR_HWVERID_RTL8180F	BITS(26, 25)
+#define RTW_TCR_HWVERID_RTL8185		(BIT(27) | BIT(25))
 /* Set ACK/CTS Timeout (EIFS).
  * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
  * 0: ACK rate = 1Mbps
  */
-#define RTW_TCR_SAT	BIT(24)
+#define RTW8180_TCR_SAT		BIT(24)
+/* 1: Software PLCP length,
+ * 0: Hardware PLCP length
+ */
+#define RTW8185_TCR_PLCPLENGTH	BIT(24)
 /* Max DMA Burst Size per Tx DMA Burst */
 #define RTW_TCR_MXDMA_MASK	BITS(23,21)
 #define RTW_TCR_MXDMA_16	LSHIFT(0, RTW_TCR_MXDMA_MASK)
@@ -275,13 +314,13 @@
 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
  * bytes are received
  */
-#define RTW_RCR_RXFTH_MASK	BITS(15,13)
-#define RTW_RCR_RXFTH_64	LSHIFT(2, RTW_RCR_RXFTH_MASK)
-#define RTW_RCR_RXFTH_128	LSHIFT(3, RTW_RCR_RXFTH_MASK)
-#define RTW_RCR_RXFTH_256	LSHIFT(4, RTW_RCR_RXFTH_MASK)
-#define RTW_RCR_RXFTH_512	LSHIFT(5, RTW_RCR_RXFTH_MASK)
-#define RTW_RCR_RXFTH_1024	LSHIFT(6, RTW_RCR_RXFTH_MASK)
-#define RTW_RCR_RXFTH_WHOLE	LSHIFT(7, RTW_RCR_RXFTH_MASK)
+#define RTW8180_RCR_RXFTH_MASK	BITS(15,13)
+#define RTW8180_RCR_RXFTH_64	LSHIFT(2, RTW8180_RCR_RXFTH_MASK)
+#define RTW8180_RCR_RXFTH_128	LSHIFT(3, RTW8180_RCR_RXFTH_MASK)
+#define RTW8180_RCR_RXFTH_256	LSHIFT(4, RTW8180_RCR_RXFTH_MASK)
+#define RTW8180_RCR_RXFTH_512	LSHIFT(5, RTW8180_RCR_RXFTH_MASK)
+#define RTW8180_RCR_RXFTH_1024	LSHIFT(6, RTW8180_RCR_RXFTH_MASK)
+#define RTW8180_RCR_RXFTH_WHOLE	LSHIFT(7, RTW8180_RCR_RXFTH_MASK)
 
 #define RTW_RCR_AICV		BIT(12)	/* accept frames w/ ICV errors */
 
@@ -365,30 +404,24 @@
 #define RTW_9346CR_EEDO	BIT(0)	/* read-only */
 
 #define RTW_CONFIG0	0x51	/* Configuration Register 0, 8b */
-#define RTW_CONFIG0_WEP40	BIT(7)	/* implements 40-bit WEP,
-					 * XXX RTL8180 only?
-					 */
-#define RTW_CONFIG0_WEP104	BIT(6)	/* implements 104-bit WEP,
-					 * from EEPROM, read-only
-					 * XXX RTL8180 only?
-					 */
-#define RTW_CONFIG0_LEDGPOEN	BIT(4)	/* 1: RTW_PSR_LEDGPO[01] control
-					 *    LED[01] pins.
-					 * 0: LED behavior defined by
-					 *    RTW_CONFIG1_LEDS10_MASK
-					 * XXX RTL8180 only?
-					 */
+#define RTW8180_CONFIG0_WEP40		BIT(7)	/* implements 40-bit WEP,
+						 */
+#define RTW8180_CONFIG0_WEP104		BIT(6)	/* implements 104-bit WEP,
+						 * from EEPROM, read-only
+						 */
+#define RTW8180_CONFIG0_LEDGPOEN	BIT(4)	/* 1: RTW_PSR_LEDGPO[01] control
+						 *    LED[01] pins.
+						 * 0: LED behavior defined by
+						 *    RTW_CONFIG1_LEDS10_MASK
+						 */
 /* auxiliary power is present, read-only */
-#define RTW_CONFIG0_AUXPWR	BIT(3)
+#define RTW_CONFIG0_AUXPWR		BIT(3)
 /* Geographic Location, read-only */
-#define RTW_CONFIG0_GL_MASK		BITS(1,0)
-/* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_*
- * work.
- */
-#define _RTW_CONFIG0_GL_USA		LSHIFT(3, RTW_CONFIG0_GL_MASK)
-#define RTW_CONFIG0_GL_EUROPE		LSHIFT(2, RTW_CONFIG0_GL_MASK)
-#define RTW_CONFIG0_GL_JAPAN		LSHIFT(1, RTW_CONFIG0_GL_MASK)
-#define RTW_CONFIG0_GL_USA		LSHIFT(0, RTW_CONFIG0_GL_MASK)
+#define RTW8180_CONFIG0_GL_MASK		BITS(1,0)
+#define RTW8180_CONFIG0_GL_USA		LSHIFT(3, RTW8180_CONFIG0_GL_MASK)
+#define RTW8180_CONFIG0_GL_EUROPE	LSHIFT(2, RTW8180_CONFIG0_GL_MASK)
+#define RTW8180_CONFIG0_GL_JAPAN	LSHIFT(1, RTW8180_CONFIG0_GL_MASK)
+#define RTW8180_CONFIG0_GL_JAPAN2	LSHIFT(0, RTW8180_CONFIG0_GL_MASK)
 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */
 
 #define RTW_CONFIG1	0x52	/* Configuration Register 1, 8b */
@@ -431,7 +464,7 @@
 				 * Tx frequency & symbol clocks
 				 * are derived from the same OSC
 				 */
-#define RTW_CONFIG2_ANT	BIT(6)	/* diversity enabled, read-only */
+#define RTW8180_CONFIG2_ANT	BIT(6)	/* diversity enabled, read-only */
 #define RTW_CONFIG2_DPS	BIT(3)	/* Descriptor Polling State: enable
 				 * test mode.
 				 */
@@ -591,19 +624,21 @@
 #define RTW_PSR_UWF	BIT(1)	/* Enable Unicast Wakeup Frame */
 #define RTW_PSR_PSEN	BIT(0)	/* 1: page 1, 0: page 0 */
 
-#define RTW_SCR		0x5f	/* Security Configuration Register, 8b */
-#define RTW_SCR_KM_MASK	BITS(5,4)	/* Key Mode */
-#define RTW_SCR_KM_WEP104	LSHIFT(1, RTW_SCR_KM_MASK)
-#define RTW_SCR_KM_WEP40	LSHIFT(0, RTW_SCR_KM_MASK)
-#define RTW_SCR_TXSECON		BIT(1)	/* Enable Tx WEP. Invalid if
+#define RTW8180_SCR		0x5f	/* Security Configuration Register, 8b */
+#define RTW8180_SCR_KM_MASK	BITS(5,4)	/* Key Mode */
+#define RTW8180_SCR_KM_WEP104	LSHIFT(1, RTW8180_SCR_KM_MASK)
+#define RTW8180_SCR_KM_WEP40	LSHIFT(0, RTW8180_SCR_KM_MASK)
+#define RTW8180_SCR_TXSECON		BIT(1)	/* Enable Tx WEP. Invalid if
 					 * neither RTW_CONFIG0_WEP40 nor
 					 * RTW_CONFIG0_WEP104 is set. 
 					 */
-#define RTW_SCR_RXSECON		BIT(0)	/* Enable Rx WEP. Invalid if
+#define RTW8180_SCR_RXSECON		BIT(0)	/* Enable Rx WEP. Invalid if
 					 * neither RTW_CONFIG0_WEP40 nor
 					 * RTW_CONFIG0_WEP104 is set. 
 					 */
 
+#define RTW8185_RFPARM	0x60	/* RF Parameter Register, 32b */
+
 #define	RTW_BCNITV	0x70	/* Beacon Interval Register, 16b */
 #define	RTW_BCNITV_BCNITV_MASK	BITS(9,0)	/* TU between TBTT, written
 						 * by host.
@@ -648,27 +683,33 @@
 #define RTW_PHYDATAW	0x7d	/* Write data to PHY, 8b, write-only */
 #define RTW_PHYDATAR	0x7e	/* Read data from PHY, 8b (?), read-only */
 
-#define RTW_PHYCFG	0x80	/* PHY Configuration Register, 32b */
-#define RTW_PHYCFG_MAC_POLL	BIT(31)		/* if !RTW_PHYCFG_HST,
+#define RTW8180_PHYCFG	0x80	/* PHY Configuration Register, 32b */
+#define RTW8180_PHYCFG_MAC_POLL	BIT(31)		/* if !RTW8180_PHYCFG_HST,
 						 * host sets. MAC clears
 						 * after banging bits.
 						 */
-#define	RTW_PHYCFG_HST		BIT(30)		/* 1: host bangs bits
+#define	RTW8180_PHYCFG_HST		BIT(30)		/* 1: host bangs bits
 						 * 0: MAC bangs bits
 						 */
-#define RTW_PHYCFG_MAC_RFTYPE_MASK	BITS(29,28)
-#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL	LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK)
-#define RTW_PHYCFG_MAC_RFTYPE_RFMD	LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK)
-#define RTW_PHYCFG_MAC_RFTYPE_GCT	RTW_PHYCFG_MAC_RFTYPE_RFMD
-#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS	LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK)
-#define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK	BITS(27,24)
-#define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK	BITS(23,0)
-#define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK	BITS(27,24)
-#define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK		BITS(11,8)
-#define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK	BITS(7,0)
-#define	RTW_PHYCFG_HST_EN		BIT(2)
-#define	RTW_PHYCFG_HST_CLK		BIT(1)
-#define	RTW_PHYCFG_HST_DATA		BIT(0)
+#define RTW8180_PHYCFG_MAC_RFTYPE_MASK	BITS(29,28)
+#define RTW8180_PHYCFG_MAC_RFTYPE_INTERSIL	LSHIFT(0, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
+#define RTW8180_PHYCFG_MAC_RFTYPE_RFMD	LSHIFT(1, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
+#define RTW8180_PHYCFG_MAC_RFTYPE_GCT	RTW8180_PHYCFG_MAC_RFTYPE_RFMD
+#define RTW8180_PHYCFG_MAC_RFTYPE_PHILIPS	LSHIFT(3, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
+#define RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK	BITS(27,24)
+#define RTW8180_PHYCFG_MAC_PHILIPS_DATA_MASK	BITS(23,0)
+#define RTW8180_PHYCFG_MAC_MAXIM_LODATA_MASK	BITS(27,24)
+#define RTW8180_PHYCFG_MAC_MAXIM_ADDR_MASK	BITS(11,8)
+#define RTW8180_PHYCFG_MAC_MAXIM_HIDATA_MASK	BITS(7,0)
+#define	RTW8180_PHYCFG_HST_EN		BIT(2)
+#define	RTW8180_PHYCFG_HST_CLK		BIT(1)
+#define	RTW8180_PHYCFG_HST_DATA		BIT(0)
+
+#define RTW8185_RFPINSOUTPUT		0x80
+#define RTW8185_RFPINSOUTPUT_MASK	0xfff3
+
+#define RTW8185_RFPINSENABLE		0x82
+#define RTW8185_RFPINSENABLE_ENABLE	0x0007
 
 #define	RTW_MAXIM_HIDATA_MASK			BITS(11,4)
 #define	RTW_MAXIM_LODATA_MASK			BITS(3,0)
@@ -713,13 +754,66 @@
 
 /* Default Key Registers, each 128b
  *
- * If RTW_SCR_KM_WEP104, 104 lsb are the key.
- * If RTW_SCR_KM_WEP40, 40 lsb are the key.
+ * If RTW8180_SCR_KM_WEP104, 104 lsb are the key.
+ * If RTW8180_SCR_KM_WEP40, 40 lsb are the key.
  */
-#define RTW_DK0		0x90	/* Default Key 0 Register, 128b */
-#define RTW_DK1		0xa0	/* Default Key 1 Register, 128b */
-#define RTW_DK2		0xb0	/* Default Key 2 Register, 128b */
-#define RTW_DK3		0xc0	/* Default Key 3 Register, 128b */
+#define RTW8180_DK0		0x90	/* Default Key 0 Register, 128b */
+#define RTW8180_DK1		0xa0	/* Default Key 1 Register, 128b */
+#define RTW8180_DK2		0xb0	/* Default Key 2 Register, 128b */
+#define RTW8180_DK3		0xc0	/* Default Key 3 Register, 128b */
+
+#define RTW8185_RFPINSSELECT		0x84
+#define RTW8185_RFPINSSELECT_ENABLE	0x0007
+
+#define RTW8185_RFPINSINPUT	0x86
+#define RTW8185_RFPARA		0x88
+#define RTW8185_RFTIMING	0x8c
+#define RTW8185_GPO		0x90
+#define RTW8185_GPE		0x91
+#define RTW8185_GPI		0x92
+#define RTW8185_TXAGCCTL	0x9c
+#define RTW8185_CCKTXAGC	0x9d
+#define RTW8185_OFDMTXAGC	0x9e
+#define RTW8185_ANTSEL		0x9f
+
+#define RTW8185_CAMRW		0xa0		/* CAM R/W Register, 32b */
+#define RTW8185_CAMRW_POOLING	BIT(31)		/* Pooling bit */
+#define RTW8185_CAMRW_WRITE	BIT(16)		/* Write enable */
+#define RTW8185_CAMRW_ADDRESS	BITS(6, 0)	/* CAM address */
+
+#define RTW8185_CAMOUTPUT	0xa4
+#define RTW8185_CAMINPUT	0xa8
+
+#define RTW8185_CAMDEBUG		0xac	/* CAM Debug Interface, 32b */
+#define RTW8185_CAMDEBUG_SELTXRXINFO	BIT(31)
+#define RTW8185_CAMDEBUG_KEYFOUND	BIT(30)
+#define RTW8185_CAMDEBUG_WPACONFIG	BITS(29, 24)
+#define RTW8185_CAMDEBUG_CAMKEY		BITS(23, 0)
+
+#define RTW8185_WPACONFIG		0xb0	/* WPA Config Register, 16b */
+#define RTW8185_WPACONFIG_RXWPADUMMY	BIT(8) 
+#define RTW8185_WPACONFIG_DISRX_AESMIC	BIT(3)
+#define RTW8185_WPACONFIG_RXDECRYPT	BIT(2)
+#define RTW8185_WPACONFIG_TXENCRYPT	BIT(1)
+#define RTW8185_WPACONFIG_USEDEFAULTKEY	BIT(0)
+
+#define RTW8185_AESMASK		0xb2
+#define RTW8185_SIFS		0xb4
+#define RTW8185_DIFS		0xb5
+#define RTW8185_SLOTTIME	0xb6
+#define RTW8185_UTUNE		0xb7
+
+#define RTW8185_CWCONFIG		0xbc	/* CW Config Register, 8b */
+#define RTW8185_CWCONFIG_PPRETRYLIMIT	BIT(1)	/* Per-Packet Retry Limit */
+#define RTW8185_CWCONFIG_PPCW		BIT(1)	/* Per-Packet Cont. Window */
+
+#define RTW8185_CWVALUES	0xbd		/* CW Values, 8b */
+#define RTW8185_CWVALUES_CWMAX	BITS(7, 4)	/* Max Contention Window */
+#define RTW8185_CWVALUES_CWMIN	BITS(3, 0)	/* Min Contention Window */
+
+#define RTW8185_RATEFALLBACKCTL		0xbe	/* Auto Rate Fallback, 8b */
+#define RTW8185_RATEFALLBACKCTL_ENABLE	BIT(7)
+#define RTW8185_RATEFALLBACKCTL_STEP	BITS(1, 0)
 
 #define	RTW_CONFIG5	0xd8	/* Configuration Register 5, 8b */
 #define RTW_CONFIG5_TXFIFOOK	BIT(7)	/* Tx FIFO self-test pass, read-only */