Introduce a #define for the number of PFN bits in a pte, to be used in the

.S code when masking the upper bits, instead of hardcoding them. Makes code
easier to understand (and also I might have a need to reduce PFN width on
some particular CPU models in the future).
No change in generated code.

3 files changed, 31 insertions, 29 deletions

diff --git a/sys/arch/mips64/include/pte.h b/sys/arch/mips64/include/pte.h
index 6cd1600dd46..c579a8f1a71 100644
--- a/sys/arch/mips64/include/pte.h
+++ b/sys/arch/mips64/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.11 2011/04/09 20:20:31 deraadt Exp $	*/
+/*	$OpenBSD: pte.h,v 1.12 2012/04/24 20:00:59 miod Exp $	*/
 
 /*
  * Copyright (c) 1988 University of Utah.
@@ -88,6 +88,7 @@ typedef u_int32_t pt_entry_t;	/* Mips page table entry */
 #define	PG_CWPAGE	(PG_V | PG_CACHED)	   /* Not w-prot but clean */
 #define	PG_IOPAGE	(PG_G | PG_V | PG_M | PG_UNCACHED)
 #define	PG_FRAME	0x3fffffc0
+#define	PG_FRAMEBITS	30
 #define PG_SHIFT	6
 
 #define	pfn_to_pad(pa)	((((paddr_t)pa) & PG_FRAME) << PG_SHIFT)
diff --git a/sys/arch/mips64/mips64/context.S b/sys/arch/mips64/mips64/context.S
index 23af7f90105..3ceb45ba7f6 100644
--- a/sys/arch/mips64/mips64/context.S
+++ b/sys/arch/mips64/mips64/context.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: context.S,v 1.45 2010/04/28 16:20:28 syuu Exp $ */
+/*	$OpenBSD: context.S,v 1.46 2012/04/24 20:01:03 miod Exp $ */
 
 /*
  * Copyright (c) 2002-2003 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -31,6 +31,7 @@
 #include <machine/param.h>
 #include <machine/asm.h>
 #include <machine/cpu.h>
+#include <machine/pte.h>
 #include <machine/regnum.h>
 #include <machine/cpustate.h>
 #ifdef CPU_LOONGSON2
@@ -196,10 +197,10 @@ ctx1:
 	dmtc0	v0, COP_0_TLB_HI
 	lw	ta0, 0(t1)
 	lw	ta1, 4(t1)
-	dsll	ta0, ta0, 34
-	dsrl	ta0, ta0, 34
-	dsll	ta1, ta1, 34
-	dsrl	ta1, ta1, 34
+	dsll	ta0, ta0, (64 - PG_FRAMEBITS)	# clear bits left of PG_FRAME
+	dsrl	ta0, ta0, (64 - PG_FRAMEBITS)
+	dsll	ta1, ta1, (64 - PG_FRAMEBITS)
+	dsrl	ta1, ta1, (64 - PG_FRAMEBITS)
 	dmtc0	ta0, COP_0_TLB_LO0
 	dmtc0	ta1, COP_0_TLB_LO1
 	nop
@@ -212,12 +213,12 @@ ctx1:
 	dmtc0	v0, COP_0_TLB_HI		# init high entry (tlbid)
 	lw	ta0, 8(t1)
 	lw	ta1, 12(t1)
-	dsll	ta0, ta0, 34
-	dsrl	ta0, ta0, 34
+	dsll	ta0, ta0, (64 - PG_FRAMEBITS)	# clear bits left of PG_FRAME
+	dsrl	ta0, ta0, (64 - PG_FRAMEBITS)
 	tlbp
 	nop
-	dsll	ta1, ta1, 34
-	dsrl	ta1, ta1, 34
+	dsll	ta1, ta1, (64 - PG_FRAMEBITS)
+	dsrl	ta1, ta1, (64 - PG_FRAMEBITS)
 	mfc0	t0, COP_0_TLB_INDEX
 	nop
 	bltz	t0, ctx2			# not in tlb
diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S
index 8a9f82765d9..f395e47b387 100644
--- a/sys/arch/mips64/mips64/tlbhandler.S
+++ b/sys/arch/mips64/mips64/tlbhandler.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tlbhandler.S,v 1.34 2012/04/09 16:54:39 miod Exp $ */
+/*	$OpenBSD: tlbhandler.S,v 1.35 2012/04/24 20:01:03 miod Exp $ */
 
 /*
  * Copyright (c) 1995-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -142,11 +142,11 @@ xtlb_miss:
 	PTR_ADDU k1, k1, k0
 	lw	k0, 0(k1)
 	lw	k1, 4(k1)
-	dsll	k0, k0, 34
-	dsrl	k0, k0, 34
+	dsll	k0, k0, (64 - PG_FRAMEBITS)	# clear bits left of PG_FRAME
+	dsrl	k0, k0, (64 - PG_FRAMEBITS)
 	dmtc0	k0, COP_0_TLB_LO0
-	dsll	k1, k1, 34
-	dsrl	k1, k1, 34
+	dsll	k1, k1, (64 - PG_FRAMEBITS)
+	dsrl	k1, k1, (64 - PG_FRAMEBITS)
 	dmtc0	k1, COP_0_TLB_LO1
 	nop				# RM7000 needs 4 nops
 	nop
@@ -224,14 +224,14 @@ NLEAF(k_tlb_inv, 0)
 	bltz	k0, sys_stk_chk			# probe fail
 	lw	k0, 0(k1)			# get PTE entry
 
-	dsll	k0, k0, 34			# get rid of "wired" bit
-	dsrl	k0, k0, 34
+	dsll	k0, k0, (64 - PG_FRAMEBITS)	# clear bits left of PG_FRAME
+	dsrl	k0, k0, (64 - PG_FRAMEBITS)
 	dmtc0	k0, COP_0_TLB_LO0		# load PTE entry
 	and	k0, k0, PG_V			# check for valid entry
 	beq	k0, zero, go_k_general		# PTE invalid
 	lw	k0, 4(k1)			# get odd PTE entry
-	dsll	k0, k0, 34
-	dsrl	k0, k0, 34
+	dsll	k0, k0, (64 - PG_FRAMEBITS)
+	dsrl	k0, k0, (64 - PG_FRAMEBITS)
 	dmtc0	k0, COP_0_TLB_LO1		# load PTE entry
 	nop
 	nop
@@ -255,14 +255,14 @@ k_tlb_inv_odd:
 	bltz	k0, sys_stk_chk			# probe fail
 	lw	k0, 0(k1)			# get PTE entry
 
-	dsll	k0, k0, 34			# get rid of wired bit
-	dsrl	k0, k0, 34
+	dsll	k0, k0, (64 - PG_FRAMEBITS)	# clear bits left of PG_FRAME
+	dsrl	k0, k0, (64 - PG_FRAMEBITS)
 	dmtc0	k0, COP_0_TLB_LO1		# save PTE entry
 	and	k0, k0, PG_V			# check for valid entry
 	beq	k0, zero, go_k_general		# PTE invalid
 	lw	k0, -4(k1)			# get even PTE entry
-	dsll	k0, k0, 34
-	dsrl	k0, k0, 34
+	dsll	k0, k0, (64 - PG_FRAMEBITS)
+	dsrl	k0, k0, (64 - PG_FRAMEBITS)
 	dmtc0	k0, COP_0_TLB_LO0		# save PTE entry
 	nop
 	nop
@@ -307,11 +307,11 @@ NLEAF(k_tlb_miss, 0)
 	PTR_ADDU k1, k1, k0
 	lw	k0, 0(k1)			# get PTE entry
 	lw	k1, 4(k1)			# get odd PTE entry
-	dsll	k0, k0, 34			# get rid of "wired" bit
-	dsrl	k0, k0, 34
+	dsll	k0, k0, (64 - PG_FRAMEBITS)	# clear bits left of PG_FRAME
+	dsrl	k0, k0, (64 - PG_FRAMEBITS)
 	dmtc0	k0, COP_0_TLB_LO0		# load PTE entry
-	dsll	k1, k1, 34
-	dsrl	k1, k1, 34
+	dsll	k1, k1, (64 - PG_FRAMEBITS)
+	dsrl	k1, k1, (64 - PG_FRAMEBITS)
 	dmtc0	k1, COP_0_TLB_LO1		# load PTE entry
 	nop
 	nop
@@ -558,8 +558,8 @@ LEAF(tlb_update, 0)
 	nop
 	nop
 	tlbp				# Probe for the entry.
-	dsll	a1, a1, 34
-	dsrl	a1, a1, 34
+	dsll	a1, a1, (64 - PG_FRAMEBITS)	# clear bits left of PG_FRAME
+	dsrl	a1, a1, (64 - PG_FRAMEBITS)
 	bne	ta1, zero, 2f		# Decide even odd
 	mfc0	v0, COP_0_TLB_INDEX	# See what we got
 # EVEN