diff options
| author | Theo de Raadt <deraadt@cvs.openbsd.org> | 1999-03-22 07:17:14 +0000 |
|---|---|---|
| committer | Theo de Raadt <deraadt@cvs.openbsd.org> | 1999-03-22 07:17:14 +0000 |
| commit | a7b23dec87ab158c2011a2fa6cb22790cca1fb30 (patch) | |
| tree | f1d0f43b9375959e4f1de5f26a7ea5895774936d | |
| parent | 2744221654012ef7db2c72c8d8ff52fd1ca933dd (diff) | |
workaround for STP1020A errata #148494
| -rw-r--r-- | sys/arch/sparc/sparc/cache.c | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/sys/arch/sparc/sparc/cache.c b/sys/arch/sparc/sparc/cache.c index 00f9fba5bd6..9d44b3ee989 100644 --- a/sys/arch/sparc/sparc/cache.c +++ b/sys/arch/sparc/sparc/cache.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cache.c,v 1.6 1999/03/15 17:55:31 deraadt Exp $ */ +/* $OpenBSD: cache.c,v 1.7 1999/03/22 07:17:13 deraadt Exp $ */ /* $NetBSD: cache.c,v 1.33 1997/07/29 09:41:56 fair Exp $ */ /* @@ -202,8 +202,11 @@ hypersparc_cache_enable() /* Now reset cache tag memory if cache not yet enabled */ if ((pcr & HYPERSPARC_PCR_CE) == 0) - for (i = 0; i < ts; i += ls) + for (i = 0; i < ts; i += ls) { sta(i, ASI_DCACHETAG, 0); + while (lda(i, ASI_DCACHETAG)) + sta(i, ASI_DCACHETAG, 0); + } /* Enable write-back cache */ pcr |= (HYPERSPARC_PCR_CE | HYPERSPARC_PCR_CM); @@ -242,8 +245,11 @@ swift_cache_enable() ls = CACHEINFO.dc_linesize; ts = CACHEINFO.dc_totalsize; if ((pcr & SWIFT_PCR_DCE) == 0) - for (i = 0; i < ts; i += ls) + for (i = 0; i < ts; i += ls) { sta(i, ASI_DCACHETAG, 0); + while (lda(i, ASI_DCACHETAG)) + sta(i, ASI_DCACHETAG, 0); + } /* XXX - assume that an MS2 with ecache is really a turbo in disguise */ if (CACHEINFO.ec_totalsize == 0) @@ -268,8 +274,11 @@ cypress_cache_enable() ls = CACHEINFO.c_linesize; ts = CACHEINFO.c_totalsize; if ((pcr & CYPRESS_PCR_CE) == 0) - for (i = 0; i < ts; i += ls) + for (i = 0; i < ts; i += ls) { sta(i, ASI_DCACHETAG, 0); + while (lda(i, ASI_DCACHETAG)) + sta(i, ASI_DCACHETAG, 0); + } pcr |= CYPRESS_PCR_CE; @@ -309,8 +318,11 @@ turbosparc_cache_enable() ls = CACHEINFO.dc_linesize; ts = CACHEINFO.dc_totalsize; if ((pcr & TURBOSPARC_PCR_DCE) == 0) - for (i = 0; i < ts; i += ls) + for (i = 0; i < ts; i += ls) { sta(i, ASI_DCACHETAG, 0); + while (lda(i, ASI_DCACHETAG)) + sta(i, ASI_DCACHETAG, 0); + } pcr |= (TURBOSPARC_PCR_ICE | TURBOSPARC_PCR_DCE); sta(SRMMU_PCR, ASI_SRMMU, pcr); |