Add support for the newer 82575 and maybe 82576 chips. The cards work more

or less out of the box if one explicitly enables the TX DMA engine.
Only tested with 82575, people with 82576 cards may contact me for a diff.
OK kettenis@

3 files changed, 49 insertions, 17 deletions

diff --git a/sys/dev/pci/if_em.c b/sys/dev/pci/if_em.c
index ae60e392893..4c8e4a587d2 100644
--- a/sys/dev/pci/if_em.c
+++ b/sys/dev/pci/if_em.c
@@ -31,7 +31,7 @@ POSSIBILITY OF SUCH DAMAGE.
 
 ***************************************************************************/
 
-/* $OpenBSD: if_em.c,v 1.209 2009/05/31 04:47:50 deraadt Exp $ */
+/* $OpenBSD: if_em.c,v 1.210 2009/06/03 17:39:44 claudio Exp $ */
 /* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */
 
 #include <dev/pci/if_em.h>
@@ -116,6 +116,12 @@ const struct pci_matchid em_devices[] = {
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES },
+	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G },
 	{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT },
@@ -322,6 +328,7 @@ em_attach(struct device *parent, struct device *self, void *aux)
 		}
 		case em_82571:
 		case em_82572:
+		case em_82575:
 		case em_ich9lan:
 		case em_80003es2lan:	/* Limit Jumbo Frame size */
 			sc->hw.max_frame_size = 9234;
@@ -689,6 +696,7 @@ em_init(void *arg)
 		break;
 	case em_82571:
 	case em_82572: /* Total Packet Buffer on these is 48k */
+	case em_82575:
 	case em_80003es2lan:
 		pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
 		break;
@@ -1411,7 +1419,8 @@ em_update_link_status(struct em_softc *sc)
 			/* Check if we may set SPEED_MODE bit on PCI-E */
 			if ((sc->link_speed == SPEED_1000) &&
 			    ((sc->hw.mac_type == em_82571) ||
-			    (sc->hw.mac_type == em_82572))) {
+			    (sc->hw.mac_type == em_82572) ||
+			    (sc->hw.mac_type == em_82575))) {
 				int tarc0;
 
 				tarc0 = E1000_READ_REG(&sc->hw, TARC0);
@@ -1659,7 +1668,8 @@ em_hardware_init(struct em_softc *sc)
 	/* Set up smart power down as default off on newer adapters */
 	if (!em_smart_pwr_down &&
 	     (sc->hw.mac_type == em_82571 ||
-	      sc->hw.mac_type == em_82572)) {
+	      sc->hw.mac_type == em_82572 ||
+	      sc->hw.mac_type == em_82575)) {
 		uint16_t phy_tmp = 0;
 
 		/* Speed up time to link by disabling smart power down */
@@ -2037,11 +2047,23 @@ em_initialize_transmit_unit(struct em_softc *sc)
 		reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
 	}
 
+
 	E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg);
 	E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay);
 	if (sc->hw.mac_type >= em_82540)
 		E1000_WRITE_REG(&sc->hw, TADV, sc->tx_abs_int_delay);
 
+	/* Setup Transmit Descriptor Base Settings */   
+	sc->txd_cmd = E1000_TXD_CMD_IFCS;
+
+	if (sc->hw.mac_type == em_82575) {
+		/* 82575/6 need to enable the TX queue and lack the IDE bit */
+		reg_tctl = E1000_READ_REG(&sc->hw, TXDCTL);
+		reg_tctl |= E1000_TXDCTL_QUEUE_ENABLE;
+		E1000_WRITE_REG(&sc->hw, TXDCTL, reg_tctl);
+	} else if (sc->tx_int_delay > 0)
+		sc->txd_cmd |= E1000_TXD_CMD_IDE;
+
 	/* Program the Transmit Control Register */
 	reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
 		   (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
@@ -2053,12 +2075,6 @@ em_initialize_transmit_unit(struct em_softc *sc)
 		reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
 	/* This write will effectively turn on the transmit unit */
 	E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl);
-
-	/* Setup Transmit Descriptor Base Settings */   
-	sc->txd_cmd = E1000_TXD_CMD_IFCS;
-
-	if (sc->tx_int_delay > 0)
-		sc->txd_cmd |= E1000_TXD_CMD_IDE;
 }
 
 /*********************************************************************
diff --git a/sys/dev/pci/if_em_hw.c b/sys/dev/pci/if_em_hw.c
index eadfd67234f..5e77b2051c9 100644
--- a/sys/dev/pci/if_em_hw.c
+++ b/sys/dev/pci/if_em_hw.c
@@ -31,7 +31,7 @@
 
 *******************************************************************************/
 
-/* $OpenBSD: if_em_hw.c,v 1.31 2008/12/04 02:36:52 brad Exp $ */
+/* $OpenBSD: if_em_hw.c,v 1.32 2009/06/03 17:39:44 claudio Exp $ */
 
 /* if_em_hw.c
  * Shared functions for accessing and configuring the MAC
@@ -410,8 +410,8 @@ em_set_mac_type(struct em_hw *hw)
         hw->mac_type = em_82547;
         break;
     case E1000_DEV_ID_82547GI:
-        hw->mac_type = em_82547_rev_2;
-        break;
+	hw->mac_type = em_82547_rev_2;
+	break;
     case E1000_DEV_ID_82571EB_AF:
     case E1000_DEV_ID_82571EB_AT:
     case E1000_DEV_ID_82571EB_COPPER:
@@ -423,8 +423,8 @@ em_set_mac_type(struct em_hw *hw)
     case E1000_DEV_ID_82571EB_SERDES_DUAL:
     case E1000_DEV_ID_82571EB_SERDES_QUAD:
     case E1000_DEV_ID_82571PT_QUAD_COPPER:
-            hw->mac_type = em_82571;
-        break;
+	hw->mac_type = em_82571;
+	break;
     case E1000_DEV_ID_82572EI_COPPER:
     case E1000_DEV_ID_82572EI_FIBER:
     case E1000_DEV_ID_82572EI_SERDES:
@@ -440,6 +440,11 @@ em_set_mac_type(struct em_hw *hw)
     case E1000_DEV_ID_82573V_PM:
         hw->mac_type = em_82573;
         break;
+    case E1000_DEV_ID_82575EB_PT:
+    case E1000_DEV_ID_82575EB_PF:
+	hw->mac_type = em_82575;
+	hw->initialize_hw_bits_disable = 1;
+	break;
     case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
     case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
     case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
@@ -1043,6 +1048,7 @@ em_init_hw(struct em_hw *hw)
         /* FALLTHROUGH */
     case em_82571:
     case em_82572:
+    case em_82575:
     case em_ich8lan:
     case em_ich9lan:
         ctrl = E1000_READ_REG(hw, TXDCTL1);
@@ -4044,7 +4050,8 @@ em_detect_gig_phy(struct em_hw *hw)
      * case, we cannot access the PHY until the configuration is done.  So
      * we explicitly set the PHY values. */
     if (hw->mac_type == em_82571 ||
-        hw->mac_type == em_82572) {
+        hw->mac_type == em_82572 ||
+	hw->mac_type == em_82575) {
         hw->phy_id = IGP01E1000_I_PHY_ID;
         hw->phy_type = em_phy_igp_2;
         return E1000_SUCCESS;
@@ -4235,6 +4242,7 @@ em_init_eeprom_params(struct em_hw *hw)
         break;
     case em_82571:
     case em_82572:
+    case em_82575:
         eeprom->type = em_eeprom_spi;
         eeprom->opcode_bits = 8;
         eeprom->delay_usec = 1;
@@ -6115,6 +6123,7 @@ em_get_bus_info(struct em_hw *hw)
     case em_82571:
     case em_82572:
     case em_82573:
+    case em_82575:
     case em_80003es2lan:
         hw->bus_type = em_bus_type_pci_express;
         hw->bus_speed = em_bus_speed_2500;
@@ -7264,6 +7273,7 @@ em_get_auto_rd_done(struct em_hw *hw)
     case em_82571:
     case em_82572:
     case em_82573:
+    case em_82575:
     case em_80003es2lan:
     case em_ich8lan:
     case em_ich9lan:
@@ -7318,6 +7328,7 @@ em_get_phy_cfg_done(struct em_hw *hw)
         /* FALLTHROUGH */
     case em_82571:
     case em_82572:
+    case em_82575:
         while (timeout) {
             if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
                 break;
diff --git a/sys/dev/pci/if_em_hw.h b/sys/dev/pci/if_em_hw.h
index ed75d9ca9e6..c0ac5ab857e 100644
--- a/sys/dev/pci/if_em_hw.h
+++ b/sys/dev/pci/if_em_hw.h
@@ -31,7 +31,7 @@
 
 *******************************************************************************/
 
-/* $OpenBSD: if_em_hw.h,v 1.27 2008/08/28 01:17:29 brad Exp $ */
+/* $OpenBSD: if_em_hw.h,v 1.28 2009/06/03 17:39:44 claudio Exp $ */
 /* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */
 
 /* if_em_hw.h
@@ -67,6 +67,7 @@ typedef enum {
     em_82571,
     em_82572,
     em_82573,
+    em_82575,
     em_80003es2lan,
     em_ich8lan,
     em_ich9lan,
@@ -509,6 +510,8 @@ int32_t em_check_phy_reset_block(struct em_hw *hw);
 #define E1000_DEV_ID_ICH10_R_BM_V        0x10CE
 #define E1000_DEV_ID_ICH10_D_BM_LM       0x10DE
 #define E1000_DEV_ID_ICH10_D_BM_LF       0x10DF
+#define E1000_DEV_ID_82575EB_PT          0x10A7
+#define E1000_DEV_ID_82575EB_PF          0x10A9
 
 #define NODE_ADDRESS_SIZE 6
 #define ETH_LENGTH_OF_ADDRESS 6
@@ -971,7 +974,7 @@ struct em_ffvt_entry {
 #define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
 #define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
 #define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
-#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
+#define E1000_TDT      0x03818  /* TX Descriptor Tail - RW */
 #define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
 #define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
 #define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
@@ -1989,6 +1992,8 @@ struct em_hw {
 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
                                               still to be processed. */
+#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000
+
 /* Transmit Configuration Word */
 #define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
 #define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */