Import siop, a replacement for the ncr SCSI driver, from NetBSD.

Written for NetBSD by Manuel Bouyer.

Tested with various cards on i386 and alpha.

Outstanding issue: doesn't work with PowerPC yet.

14 files changed, 6000 insertions, 2 deletions

diff --git a/sys/conf/files b/sys/conf/files
index 37e843446cb..51a0deb2e31 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -1,4 +1,4 @@
-#	$OpenBSD: files,v 1.187 2001/02/10 10:42:34 niklas Exp $
+#	$OpenBSD: files,v 1.188 2001/02/15 04:07:57 krw Exp $
 #	$NetBSD: files,v 1.87 1996/05/19 17:17:50 jonathan Exp $
 
 #	@(#)files.newconf	7.5 (Berkeley) 5/10/93
@@ -122,6 +122,14 @@ define	ncr53c9x
 device	esp: scsi, ncr53c9x
 file	dev/ic/ncr53c9x.c	ncr53c9x
 
+# common stuff for siop and esiop
+define siop_common
+file dev/ic/siop_common.c		siop_common
+
+# Symbios/NCR 53c720/53c8xx SCSI controllers
+device siop: scsi,siop_common
+file dev/ic/siop.c			siop
+
 # 3Com Etherlink-III Ethernet controller
 device	ep: ether, ifnet, ifmedia, mii
 file	dev/ic/elink3.c		ep
diff --git a/sys/dev/ic/siop.c b/sys/dev/ic/siop.c
new file mode 100644
index 00000000000..c00398df08d
--- /dev/null
+++ b/sys/dev/ic/siop.c
@@ -0,0 +1,2017 @@
+/*	$OpenBSD: siop.c,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$NetBSD: siop.c,v 1.39 2001/02/11 18:04:49 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* SYM53c7/8xx PCI-SCSI I/O Processors driver */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/buf.h>
+#include <sys/kernel.h>
+
+#include <machine/endian.h>
+#include <machine/bus.h>
+
+#include <dev/microcode/siop/siop.out>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsi_message.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/ic/siopreg.h>
+#include <dev/ic/siopvar.h>
+#include <dev/ic/siopvar_common.h>
+
+#ifndef DEBUG
+#undef DEBUG
+#endif
+#undef SIOP_DEBUG
+#undef SIOP_DEBUG_DR
+#undef SIOP_DEBUG_INTR
+#undef SIOP_DEBUG_SCHED
+#undef DUMP_SCRIPT
+
+#define SIOP_STATS
+
+#ifndef SIOP_DEFAULT_TARGET
+#define SIOP_DEFAULT_TARGET 7
+#endif
+
+/* number of cmd descriptors per block */
+#define SIOP_NCMDPB (PAGE_SIZE / sizeof(struct siop_xfer))
+
+/* Number of scheduler slot (needs to match script) */
+#define SIOP_NSLOTS 40
+
+void	siop_reset __P((struct siop_softc *));
+void	siop_handle_reset __P((struct siop_softc *));
+int	siop_handle_qtag_reject __P((struct siop_cmd *));
+void	siop_scsicmd_end __P((struct siop_cmd *));
+void	siop_start __P((struct siop_softc *));
+void 	siop_timeout __P((void *));
+int	siop_scsicmd __P((struct scsi_xfer *));
+void	siop_dump_script __P((struct siop_softc *));
+int	siop_morecbd __P((struct siop_softc *));
+struct siop_lunsw *siop_get_lunsw __P((struct siop_softc *));
+void	siop_add_reselsw __P((struct siop_softc *, int));
+void	siop_update_scntl3 __P((struct siop_softc *, struct siop_target *));
+
+struct cfdriver siop_cd = {
+	NULL, "siop", DV_DULL
+};
+
+struct scsi_adapter siop_adapter = {
+	siop_scsicmd,
+	siop_minphys,
+	NULL,
+	NULL,
+};
+
+struct scsi_device siop_dev = {
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+};
+
+#ifdef SIOP_STATS
+static int siop_stat_intr = 0;
+static int siop_stat_intr_shortxfer = 0;
+static int siop_stat_intr_sdp = 0;
+static int siop_stat_intr_done = 0;
+static int siop_stat_intr_xferdisc = 0;
+static int siop_stat_intr_lunresel = 0;
+static int siop_stat_intr_qfull = 0;
+void siop_printstats __P((void));
+#define INCSTAT(x) x++
+#else
+#define INCSTAT(x) 
+#endif
+
+static __inline__ void siop_script_sync __P((struct siop_softc *, int));
+static __inline__ void
+siop_script_sync(sc, ops)
+	struct siop_softc *sc;
+	int ops;
+{
+	if ((sc->features & SF_CHIP_RAM) == 0)
+		bus_dmamap_sync(sc->sc_dmat, sc->sc_scriptdma, ops);
+}
+
+static __inline__ u_int32_t siop_script_read __P((struct siop_softc *, u_int));
+static __inline__ u_int32_t
+siop_script_read(sc, offset)
+	struct siop_softc *sc;
+	u_int offset;
+{
+	if (sc->features & SF_CHIP_RAM) {
+		return bus_space_read_4(sc->sc_ramt, sc->sc_ramh, offset * 4);
+	} else {
+		return letoh32(sc->sc_script[offset]);
+	}
+}
+
+static __inline__ void siop_script_write __P((struct siop_softc *, u_int,
+	u_int32_t));
+static __inline__ void
+siop_script_write(sc, offset, val)
+	struct siop_softc *sc;
+	u_int offset;
+	u_int32_t val;
+{
+	if (sc->features & SF_CHIP_RAM) {
+		bus_space_write_4(sc->sc_ramt, sc->sc_ramh, offset * 4, val);
+	} else {
+		sc->sc_script[offset] = htole32(val);
+	}
+}
+
+void
+siop_attach(sc)
+	struct siop_softc *sc;
+{
+	int error, i;
+	bus_dma_segment_t seg;
+	int rseg;
+
+	/*
+	 * Allocate DMA-safe memory for the script and map it.
+	 */
+	if ((sc->features & SF_CHIP_RAM) == 0) {
+		error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 
+		    PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT);
+		if (error) {
+			printf("%s: unable to allocate script DMA memory, "
+			    "error = %d\n", sc->sc_dev.dv_xname, error);
+			return;
+		}
+		error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, PAGE_SIZE,
+		    (caddr_t *)&sc->sc_script, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
+		if (error) {
+			printf("%s: unable to map script DMA memory, "
+			    "error = %d\n", sc->sc_dev.dv_xname, error);
+			return;
+		}
+		error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1,
+		    PAGE_SIZE, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma);
+		if (error) {
+			printf("%s: unable to create script DMA map, "
+			    "error = %d\n", sc->sc_dev.dv_xname, error);
+			return;
+		}
+		error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma,
+		    sc->sc_script, PAGE_SIZE, NULL, BUS_DMA_NOWAIT);
+		if (error) {
+			printf("%s: unable to load script DMA map, "
+			    "error = %d\n", sc->sc_dev.dv_xname, error);
+			return;
+		}
+		sc->sc_scriptaddr = sc->sc_scriptdma->dm_segs[0].ds_addr;
+		sc->ram_size = PAGE_SIZE;
+	}
+	TAILQ_INIT(&sc->free_list);
+	TAILQ_INIT(&sc->ready_list);
+	TAILQ_INIT(&sc->urgent_list);
+	TAILQ_INIT(&sc->cmds);
+	TAILQ_INIT(&sc->lunsw_list);
+	sc->sc_currschedslot = 0;
+#ifdef SIOP_DEBUG
+	printf("%s: script size = %d, PHY addr=0x%x, VIRT=%p\n",
+	    sc->sc_dev.dv_xname, (int)sizeof(siop_script),
+	    (u_int32_t)sc->sc_scriptaddr, sc->sc_script);
+#endif
+
+	sc->sc_link.adapter_softc = sc;
+	sc->sc_link.openings = 2;
+	sc->sc_link.adapter_buswidth =
+	    (sc->features & SF_BUS_WIDE) ? 16 : 8;
+	sc->sc_link.adapter_target = bus_space_read_1(sc->sc_rt,
+	    sc->sc_rh, SIOP_SCID);
+	if (sc->sc_link.adapter_target == 0 ||
+	    sc->sc_link.adapter_target >=
+	    sc->sc_link.adapter_buswidth)
+		sc->sc_link.adapter_target = SIOP_DEFAULT_TARGET;
+	sc->sc_link.adapter = &siop_adapter;
+	sc->sc_link.device = &siop_dev;
+	sc->sc_link.flags  = 0;
+
+	for (i = 0; i < 16; i++)
+		sc->targets[i] = NULL;
+
+	/* find min/max sync period for this chip */
+	sc->maxsync = 0;
+	sc->minsync = 255;
+	for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); i++) {
+		if (sc->clock_period != scf_period[i].clock)
+			continue;
+		if (sc->maxsync < scf_period[i].period)
+			sc->maxsync = scf_period[i].period;
+		if (sc->minsync > scf_period[i].period)
+			sc->minsync = scf_period[i].period;
+	}
+	if (sc->maxsync == 255 || sc->minsync == 0)
+		panic("siop: can't find my sync parameters\n");
+	/* Do a bus reset, so that devices fall back to narrow/async */
+	siop_resetbus(sc);
+	/*
+	 * siop_reset() will reset the chip, thus clearing pending interrupts
+	 */
+	siop_reset(sc);
+#ifdef DUMP_SCRIPT
+	siop_dump_script(sc);
+#endif
+
+	config_found((struct device*)sc, &sc->sc_link, scsiprint);
+}
+
+void
+siop_reset(sc)
+	struct siop_softc *sc;
+{
+	int i, j;
+	struct siop_lunsw *lunsw;
+
+	siop_common_reset(sc);
+
+	/* copy and patch the script */
+	if (sc->features & SF_CHIP_RAM) {
+		bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh, 0,
+		    siop_script, sizeof(siop_script) / sizeof(siop_script[0]));
+		for (j = 0; j <
+		    (sizeof(E_abs_msgin_Used) / sizeof(E_abs_msgin_Used[0]));
+		    j++) {
+			bus_space_write_4(sc->sc_ramt, sc->sc_ramh,
+			    E_abs_msgin_Used[j] * 4,
+			    sc->sc_scriptaddr + Ent_msgin_space);
+		}
+	} else {
+		for (j = 0;
+		    j < (sizeof(siop_script) / sizeof(siop_script[0])); j++) {
+			sc->sc_script[j] = htole32(siop_script[j]);
+		}
+		for (j = 0; j <
+		    (sizeof(E_abs_msgin_Used) / sizeof(E_abs_msgin_Used[0]));
+		    j++) {
+			sc->sc_script[E_abs_msgin_Used[j]] =
+			    htole32(sc->sc_scriptaddr + Ent_msgin_space);
+		}
+	}
+	sc->script_free_lo = sizeof(siop_script) / sizeof(siop_script[0]);
+	sc->script_free_hi = sc->ram_size / 4;
+
+	/* free used and unused lun switches */
+	while((lunsw = TAILQ_FIRST(&sc->lunsw_list)) != NULL) {
+#ifdef SIOP_DEBUG
+		printf("%s: free lunsw at offset %d\n",
+				sc->sc_dev.dv_xname, lunsw->lunsw_off);
+#endif
+		TAILQ_REMOVE(&sc->lunsw_list, lunsw, next);
+		free(lunsw, M_DEVBUF);
+	}
+	TAILQ_INIT(&sc->lunsw_list);
+	/* restore reselect switch */
+	for (i = 0; i < sc->sc_link.adapter_buswidth; i++) {
+		if (sc->targets[i] == NULL)
+			continue;
+#ifdef SIOP_DEBUG
+		printf("%s: restore sw for target %d\n",
+				sc->sc_dev.dv_xname, i);
+#endif
+		free(sc->targets[i]->lunsw, M_DEVBUF);
+		sc->targets[i]->lunsw = siop_get_lunsw(sc);
+		if (sc->targets[i]->lunsw == NULL) {
+			printf("%s: can't alloc lunsw for target %d\n",
+			    sc->sc_dev.dv_xname, i);
+			break;
+		}
+		siop_add_reselsw(sc, i);
+	}
+
+	/* start script */
+	if ((sc->features & SF_CHIP_RAM) == 0) {
+		bus_dmamap_sync(sc->sc_dmat, sc->sc_scriptdma,
+		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+	}
+	bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP,
+	    sc->sc_scriptaddr + Ent_reselect);
+}
+
+#if 0
+#define CALL_SCRIPT(ent) do {\
+	printf ("start script DSA 0x%lx DSP 0x%lx\n", \
+	    siop_cmd->dsa, \
+	    sc->sc_scriptaddr + ent); \
+bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \
+} while (0)
+#else
+#define CALL_SCRIPT(ent) do {\
+bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \
+} while (0)
+#endif
+
+int
+siop_intr(v)
+	void *v;
+{
+	struct siop_softc *sc = v;
+	struct siop_target *siop_target;
+	struct siop_cmd *siop_cmd;
+	struct siop_lun *siop_lun;
+	struct scsi_xfer *xs;
+	int istat, sist, sstat1, dstat;
+	u_int32_t irqcode;
+	int need_reset = 0;
+	int offset, target, lun, tag;
+	bus_addr_t dsa;
+	struct siop_cbd *cbdp;
+	int freetarget = 0;
+	int restart = 0;
+
+	istat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT);
+	if ((istat & (ISTAT_INTF | ISTAT_DIP | ISTAT_SIP)) == 0)
+		return 0;
+	INCSTAT(siop_stat_intr);
+	if (istat & ISTAT_INTF) {
+		printf("INTRF\n");
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_INTF);
+	}
+	/* use DSA to find the current siop_cmd */
+	dsa = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA);
+	for (cbdp = TAILQ_FIRST(&sc->cmds); cbdp != NULL;
+	    cbdp = TAILQ_NEXT(cbdp, next)) {
+		if (dsa >= cbdp->xferdma->dm_segs[0].ds_addr &&
+	    	    dsa < cbdp->xferdma->dm_segs[0].ds_addr + PAGE_SIZE) {
+			dsa -= cbdp->xferdma->dm_segs[0].ds_addr;
+			siop_cmd = &cbdp->cmds[dsa / sizeof(struct siop_xfer)];
+			siop_table_sync(siop_cmd,
+			    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+			break;
+		}
+	} 
+	if (cbdp == NULL) {
+		siop_cmd = NULL;
+	}
+	if (siop_cmd) {
+		xs = siop_cmd->xs;
+		siop_target = siop_cmd->siop_target;
+		target = siop_cmd->xs->sc_link->target;
+		lun = siop_cmd->xs->sc_link->lun;
+		tag = siop_cmd->tag;
+		siop_lun = siop_target->siop_lun[lun];
+#ifdef DIAGNOSTIC
+		if (siop_cmd->status != CMDST_ACTIVE &&
+		    siop_cmd->status != CMDST_SENSE_ACTIVE) {
+			printf("siop_cmd (lun %d) not active (%d)\n",
+				lun, siop_cmd->status);
+			xs = NULL;
+			siop_target = NULL;
+			target = -1;
+			lun = -1;
+			tag = -1;
+			siop_lun = NULL;
+			siop_cmd = NULL;
+		} else if (siop_lun->siop_tag[tag].active != siop_cmd) {
+			printf("siop_cmd (lun %d tag %d) not in siop_lun "
+			    "active (%p != %p)\n", lun, tag, siop_cmd,
+			    siop_lun->siop_tag[tag].active);
+		}
+#endif
+	} else {
+		xs = NULL;
+		siop_target = NULL;
+		target = -1;
+		lun = -1;
+		tag = -1;
+		siop_lun = NULL;
+	}
+	if (istat & ISTAT_DIP) {
+		dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DSTAT);
+		if (dstat & DSTAT_SSI) {
+			printf("single step dsp 0x%08x dsa 0x08%x\n",
+			    (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) -
+			    sc->sc_scriptaddr),
+			    bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA));
+			if ((dstat & ~(DSTAT_DFE | DSTAT_SSI)) == 0 &&
+			    (istat & ISTAT_SIP) == 0) {
+				bus_space_write_1(sc->sc_rt, sc->sc_rh,
+				    SIOP_DCNTL, bus_space_read_1(sc->sc_rt,
+				    sc->sc_rh, SIOP_DCNTL) | DCNTL_STD);
+			}
+			return 1;
+		}
+		if (dstat & ~(DSTAT_SIR | DSTAT_DFE | DSTAT_SSI)) {
+		printf("DMA IRQ:");
+		if (dstat & DSTAT_IID)
+			printf(" Illegal instruction");
+		if (dstat & DSTAT_ABRT)
+			printf(" abort");
+		if (dstat & DSTAT_BF)
+			printf(" bus fault");
+		if (dstat & DSTAT_MDPE)
+			printf(" parity");
+		if (dstat & DSTAT_DFE)
+			printf(" dma fifo empty");
+		printf(", DSP=0x%x DSA=0x%x: ",
+		    (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) -
+		    sc->sc_scriptaddr),
+		    bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA));
+		if (siop_cmd)
+			printf("last msg_in=0x%x status=0x%x\n",
+			    siop_cmd->siop_tables.msg_in[0],
+			    letoh32(siop_cmd->siop_tables.status));
+		else 
+			printf("%s: current DSA invalid\n",
+			    sc->sc_dev.dv_xname);
+		need_reset = 1;
+		}
+	}
+	if (istat & ISTAT_SIP) {
+		if (istat & ISTAT_DIP)
+			delay(10);
+		/*
+		 * Can't read sist0 & sist1 independantly, or we have to
+		 * insert delay
+		 */
+		sist = bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_SIST0);
+		sstat1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1);
+#ifdef SIOP_DEBUG_INTR
+		printf("scsi interrupt, sist=0x%x sstat1=0x%x "
+		    "DSA=0x%x DSP=0x%lx\n", sist,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1),
+		    bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA),
+		    (u_long)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) -
+		    sc->sc_scriptaddr));
+#endif
+		if (sist & SIST0_RST) {
+			siop_handle_reset(sc);
+			siop_start(sc);
+			/* no table to flush here */
+			return 1;
+		}
+		if (sist & SIST0_SGE) {
+			if (siop_cmd)
+				sc_print_addr(xs->sc_link);
+			else
+				printf("%s:", sc->sc_dev.dv_xname);
+			printf("scsi gross error\n");
+			goto reset;
+		}
+		if ((sist & SIST0_MA) && need_reset == 0) {
+			if (siop_cmd) { 
+				int scratcha0;
+				dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+				    SIOP_DSTAT);
+				/*
+				 * first restore DSA, in case we were in a S/G
+				 * operation.
+				 */
+				bus_space_write_4(sc->sc_rt, sc->sc_rh,
+				    SIOP_DSA, siop_cmd->dsa);
+				scratcha0 = bus_space_read_1(sc->sc_rt,
+				    sc->sc_rh, SIOP_SCRATCHA);
+				switch (sstat1 & SSTAT1_PHASE_MASK) {
+				case SSTAT1_PHASE_STATUS:
+				/*
+				 * previous phase may be aborted for any reason
+				 * ( for example, the target has less data to
+				 * transfer than requested). Just go to status
+				 * and the command should terminate.
+				 */
+					INCSTAT(siop_stat_intr_shortxfer);
+					if ((dstat & DSTAT_DFE) == 0)
+						siop_clearfifo(sc);
+					/* no table to flush here */
+					CALL_SCRIPT(Ent_status);
+					return 1;
+				case SSTAT1_PHASE_MSGIN:
+					/*
+					 * target may be ready to disconnect
+					 * Save data pointers just in case.
+					 */
+					INCSTAT(siop_stat_intr_xferdisc);
+					if (scratcha0 & A_flag_data)
+						siop_sdp(siop_cmd);
+					else if ((dstat & DSTAT_DFE) == 0)
+						siop_clearfifo(sc);
+					bus_space_write_1(sc->sc_rt, sc->sc_rh,
+					    SIOP_SCRATCHA,
+					    scratcha0 & ~A_flag_data);
+					siop_table_sync(siop_cmd,
+					    BUS_DMASYNC_PREREAD |
+					    BUS_DMASYNC_PREWRITE);
+					CALL_SCRIPT(Ent_msgin);
+					return 1;
+				}
+				printf("%s: unexpected phase mismatch %d\n",
+				    sc->sc_dev.dv_xname,
+				    sstat1 & SSTAT1_PHASE_MASK);
+			} else {
+				printf("%s: phase mismatch without command\n",
+				    sc->sc_dev.dv_xname);
+			}
+			need_reset = 1;
+		}
+		if (sist & SIST0_PAR) {
+			/* parity error, reset */
+			if (siop_cmd)
+				sc_print_addr(xs->sc_link);
+			else
+				printf("%s:", sc->sc_dev.dv_xname);
+			printf("parity error\n");
+			goto reset;
+		}
+		if ((sist & (SIST1_STO << 8)) && need_reset == 0) {
+			/* selection time out, assume there's no device here */
+			if (siop_cmd) {
+				siop_cmd->status = CMDST_DONE;
+				xs->error = XS_SELTIMEOUT;
+				freetarget = 1;
+				goto end;
+			} else {
+				printf("%s: selection timeout without "
+				    "command\n", sc->sc_dev.dv_xname);
+				need_reset = 1;
+			}
+		}
+		if (sist & SIST0_UDC) {
+			/*
+			 * unexpected disconnect. Usually the target signals
+			 * a fatal condition this way. Attempt to get sense.
+			 */
+			 if (siop_cmd) {
+				siop_cmd->siop_tables.status =
+				    htole32(SCSI_CHECK);
+				goto end;
+			}
+			printf("%s: unexpected disconnect without "
+			    "command\n", sc->sc_dev.dv_xname);
+			goto reset;
+		}
+		if (sist & (SIST1_SBMC << 8)) {
+			/* SCSI bus mode change */
+			if (siop_modechange(sc) == 0 || need_reset == 1)
+				goto reset;
+			if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) {
+				/*
+				 * we have a script interrupt, it will
+				 * restart the script.
+				 */
+				goto scintr;
+			}
+			/*
+			 * else we have to restart it ourselve, at the
+			 * interrupted instruction.
+			 */
+			bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP,
+			    bus_space_read_4(sc->sc_rt, sc->sc_rh,
+			    SIOP_DSP) - 8);
+			return 1;
+		}
+		/* Else it's an unhandled exeption (for now). */
+		printf("%s: unhandled scsi interrupt, sist=0x%x sstat1=0x%x "
+		    "DSA=0x%x DSP=0x%x\n", sc->sc_dev.dv_xname, sist,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1),
+		    bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA),
+		    (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) -
+		    sc->sc_scriptaddr));
+		if (siop_cmd) {
+			siop_cmd->status = CMDST_DONE;
+			xs->error = XS_SELTIMEOUT;
+			goto end;
+		}
+		need_reset = 1;
+	}
+	if (need_reset) {
+reset:
+		/* fatal error, reset the bus */
+		siop_resetbus(sc);
+		/* no table to flush here */
+		return 1;
+	}
+
+scintr:
+	if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { /* script interrupt */
+		irqcode = bus_space_read_4(sc->sc_rt, sc->sc_rh,
+		    SIOP_DSPS);
+#ifdef SIOP_DEBUG_INTR
+		printf("script interrupt 0x%x\n", irqcode);
+#endif
+		/*
+		 * no command, or an inactive command is only valid for a
+		 * reselect interrupt
+		 */
+		if ((irqcode & 0x80) == 0) {
+			if (siop_cmd == NULL) {
+				printf("%s: script interrupt (0x%x) with
+				    invalid DSA !!!\n", sc->sc_dev.dv_xname,
+				    irqcode);
+				goto reset;
+			}
+			if (siop_cmd->status != CMDST_ACTIVE &&
+			    siop_cmd->status != CMDST_SENSE_ACTIVE) {
+				printf("%s: command with invalid status "
+				    "(IRQ code 0x%x current status %d) !\n",
+				    sc->sc_dev.dv_xname,
+				    irqcode, siop_cmd->status);
+				xs = NULL;
+			}
+		}
+		switch(irqcode) {
+		case A_int_err:
+			printf("error, DSP=0x%x\n",
+			    (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh,
+			    SIOP_DSP) - sc->sc_scriptaddr));
+			if (xs) {
+				xs->error = XS_SELTIMEOUT;
+				goto end;
+			} else {
+				goto reset;
+			}
+		case A_int_reseltarg:
+			printf("%s: reselect with invalid target\n",
+				    sc->sc_dev.dv_xname);
+			goto reset;
+		case A_int_resellun: 
+			INCSTAT(siop_stat_intr_lunresel);
+			target = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_SCRATCHA) & 0xf;
+			lun = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_SCRATCHA + 1);
+			tag = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_SCRATCHA + 2);
+			siop_target = sc->targets[target];
+			if (siop_target == NULL) {
+				printf("%s: reselect with invalid "
+				    "target %d\n", sc->sc_dev.dv_xname, target);
+				goto reset;
+			}
+			siop_lun = siop_target->siop_lun[lun];
+			if (siop_lun == NULL) {
+				printf("%s: target %d reselect with invalid "
+				    "lun %d\n", sc->sc_dev.dv_xname,
+				    target, lun);
+				goto reset;
+			}
+			if (siop_lun->siop_tag[tag].active == NULL) {
+				printf("%s: target %d lun %d tag %d reselect "
+				    "without command\n", sc->sc_dev.dv_xname,
+				    target, lun, tag);
+				goto reset;
+			}
+			siop_cmd = siop_lun->siop_tag[tag].active;
+			bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP,
+			    siop_cmd->dsa + sizeof(struct siop_xfer_common) +
+			    Ent_ldsa_reload_dsa);
+			siop_table_sync(siop_cmd, BUS_DMASYNC_PREWRITE);
+			return 1;
+		case A_int_reseltag:
+			printf("%s: reselect with invalid tag\n",
+				    sc->sc_dev.dv_xname);
+			goto reset;
+		case A_int_msgin:
+		{
+			int msgin = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_SFBR);
+			if (msgin == MSG_MESSAGE_REJECT) {
+				int msg, extmsg;
+				if (siop_cmd->siop_tables.msg_out[0] & 0x80) {
+					/*
+					 * message was part of a identify +
+					 * something else. Identify shoudl't
+					 * have been rejected.
+					 */
+					msg = siop_cmd->siop_tables.msg_out[1];
+					extmsg =
+					    siop_cmd->siop_tables.msg_out[3];
+				} else {
+					msg = siop_cmd->siop_tables.msg_out[0];
+					extmsg =
+					    siop_cmd->siop_tables.msg_out[2];
+				}
+				if (msg == MSG_MESSAGE_REJECT) {
+					/* MSG_REJECT  for a MSG_REJECT  !*/
+					if (xs)
+						sc_print_addr(xs->sc_link);
+					else
+						printf("%s: ",
+						   sc->sc_dev.dv_xname);
+					printf("our reject message was "
+					    "rejected\n");
+					goto reset;
+				}
+				if (msg == MSG_EXTENDED &&
+				    extmsg == MSG_EXT_WDTR) {
+					/* WDTR rejected, initiate sync */
+					printf("%s: target %d using 8bit "
+					    "transfers\n", sc->sc_dev.dv_xname,
+					    target);
+					if ((siop_target->flags & TARF_SYNC)
+					    == 0) {
+						siop_target->status = TARST_OK;
+						/* no table to flush here */
+						CALL_SCRIPT(Ent_msgin_ack);
+						return 1;
+					}
+					siop_target->status = TARST_SYNC_NEG;
+					siop_sdtr_msg(siop_cmd, 0,
+					    sc->minsync, sc->maxoff);
+					siop_table_sync(siop_cmd,
+					    BUS_DMASYNC_PREREAD |
+					    BUS_DMASYNC_PREWRITE);
+					CALL_SCRIPT(Ent_send_msgout);
+					return 1;
+				} else if (msg == MSG_EXTENDED &&
+				    extmsg == MSG_EXT_SDTR) {
+					/* sync rejected */
+					printf("%s: target %d asynchronous\n",
+					    sc->sc_dev.dv_xname,
+					    target);
+					siop_target->status = TARST_OK;
+					/* no table to flush here */
+					CALL_SCRIPT(Ent_msgin_ack);
+					return 1;
+				} else if (msg == MSG_SIMPLE_Q_TAG || 
+				    msg == MSG_HEAD_OF_Q_TAG ||
+				    msg == MSG_ORDERED_Q_TAG) {
+					if (siop_handle_qtag_reject(
+					    siop_cmd) == -1)
+						goto reset;
+					CALL_SCRIPT(Ent_msgin_ack);
+					return 1;
+				}
+				if (xs)
+					sc_print_addr(xs->sc_link);
+				else
+					printf("%s: ", sc->sc_dev.dv_xname);
+				if (msg == MSG_EXTENDED) {
+					printf("scsi message reject, extended "
+					    "message sent was 0x%x\n", extmsg);
+				} else {
+					printf("scsi message reject, message "
+					    "sent was 0x%x\n", msg);
+				}
+				/* no table to flush here */
+				CALL_SCRIPT(Ent_msgin_ack);
+				return 1;
+			}
+			if (xs)
+				sc_print_addr(xs->sc_link);
+			else
+				printf("%s: ", sc->sc_dev.dv_xname);
+			printf("unhandled message 0x%x\n",
+			    siop_cmd->siop_tables.msg_in[0]);
+			siop_cmd->siop_tables.msg_out[0] = MSG_MESSAGE_REJECT;
+			siop_cmd->siop_tables.t_msgout.count= htole32(1);
+			siop_table_sync(siop_cmd,
+			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+			CALL_SCRIPT(Ent_send_msgout);
+			return 1;
+		}
+		case A_int_extmsgin:
+#ifdef SIOP_DEBUG_INTR
+			printf("extended message: msg 0x%x len %d\n",
+			    siop_cmd->siop_tables.msg_in[2], 
+			    siop_cmd->siop_tables.msg_in[1]);
+#endif
+			if (siop_cmd->siop_tables.msg_in[1] > 6)
+				printf("%s: extended message too big (%d)\n",
+				    sc->sc_dev.dv_xname,
+				    siop_cmd->siop_tables.msg_in[1]);
+			siop_cmd->siop_tables.t_extmsgdata.count =
+			    htole32(siop_cmd->siop_tables.msg_in[1] - 1);
+			siop_table_sync(siop_cmd,
+			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+			CALL_SCRIPT(Ent_get_extmsgdata);
+			return 1;
+		case A_int_extmsgdata:
+#ifdef SIOP_DEBUG_INTR
+			{
+			int i;
+			printf("extended message: 0x%x, data:",
+			    siop_cmd->siop_tables.msg_in[2]);
+			for (i = 3; i < 2 + siop_cmd->siop_tables.msg_in[1];
+			    i++)
+				printf(" 0x%x",
+				    siop_cmd->siop_tables.msg_in[i]);
+			printf("\n");
+			}
+#endif
+			if (siop_cmd->siop_tables.msg_in[2] == MSG_EXT_WDTR) {
+				switch (siop_wdtr_neg(siop_cmd)) {
+				case SIOP_NEG_MSGOUT:
+					siop_update_scntl3(sc,
+					    siop_cmd->siop_target);
+					siop_table_sync(siop_cmd,
+					    BUS_DMASYNC_PREREAD |
+					    BUS_DMASYNC_PREWRITE);
+					CALL_SCRIPT(Ent_send_msgout);
+					return(1);
+				case SIOP_NEG_ACK:
+					siop_update_scntl3(sc,
+					    siop_cmd->siop_target);
+					CALL_SCRIPT(Ent_msgin_ack);
+					return(1);
+				default:
+					panic("invalid retval from "
+					    "siop_wdtr_neg()");
+				}
+				return(1);
+			}
+			if (siop_cmd->siop_tables.msg_in[2] == MSG_EXT_SDTR) {
+				switch (siop_sdtr_neg(siop_cmd)) {
+				case SIOP_NEG_MSGOUT:
+					siop_update_scntl3(sc,
+					    siop_cmd->siop_target);
+					siop_table_sync(siop_cmd,
+					    BUS_DMASYNC_PREREAD |
+					    BUS_DMASYNC_PREWRITE);
+					CALL_SCRIPT(Ent_send_msgout);
+					return(1);
+				case SIOP_NEG_ACK:
+					siop_update_scntl3(sc,
+					    siop_cmd->siop_target);
+					CALL_SCRIPT(Ent_msgin_ack);
+					return(1);
+				default:
+					panic("invalid retval from "
+					    "siop_wdtr_neg()");
+				}
+				return(1);
+			}
+			/* send a message reject */
+			siop_cmd->siop_tables.msg_out[0] = MSG_MESSAGE_REJECT;
+			siop_cmd->siop_tables.t_msgout.count = htole32(1);
+			siop_table_sync(siop_cmd,
+			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+			CALL_SCRIPT(Ent_send_msgout);
+			return 1;
+		case A_int_disc:
+			INCSTAT(siop_stat_intr_sdp);
+			offset = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_SCRATCHA + 1);
+#ifdef SIOP_DEBUG_DR
+			printf("disconnect offset %d\n", offset);
+#endif
+			if (offset > SIOP_NSG) {
+				printf("%s: bad offset for disconnect (%d)\n",
+				    sc->sc_dev.dv_xname, offset);
+				goto reset;
+			}
+			/* 
+			 * offset == SIOP_NSG may be a valid condition if
+			 * we get a sdp when the xfer is done.
+			 * Don't call memmove in this case.
+			 */
+			if (offset < SIOP_NSG) {
+				bcopy(&siop_cmd->siop_tables.data[offset],
+				    &siop_cmd->siop_tables.data[0],
+				    (SIOP_NSG - offset) * sizeof(scr_table_t));
+				siop_table_sync(siop_cmd,
+				    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+			}
+			CALL_SCRIPT(Ent_script_sched);
+			/* check if we can put some command in scheduler */
+			siop_start(sc);
+			return 1;
+		case A_int_resfail:
+			printf("reselect failed\n");
+			CALL_SCRIPT(Ent_script_sched);
+			return  1;
+		case A_int_done:
+			if (xs == NULL) {
+				printf("%s: done without command, DSA=0x%lx\n",
+				    sc->sc_dev.dv_xname, (u_long)siop_cmd->dsa);
+				siop_cmd->status = CMDST_FREE;
+				siop_start(sc);
+				CALL_SCRIPT(Ent_script_sched);
+				return 1;
+			}
+#ifdef SIOP_DEBUG_INTR
+			printf("done, DSA=0x%lx target id 0x%x last msg "
+			    "in=0x%x status=0x%x\n", (u_long)siop_cmd->dsa,
+			    letoh32(siop_cmd->siop_tables.id),
+			    siop_cmd->siop_tables.msg_in[0],
+			    letoh32(siop_cmd->siop_tables.status));
+#endif
+			INCSTAT(siop_stat_intr_done);
+			if (siop_cmd->status == CMDST_SENSE_ACTIVE)
+				siop_cmd->status = CMDST_SENSE_DONE;
+			else
+				siop_cmd->status = CMDST_DONE;
+			goto end;
+		default:
+			printf("unknown irqcode %x\n", irqcode);
+			if (xs) {
+				xs->error = XS_SELTIMEOUT;
+				goto end;
+			}
+			goto reset;
+		}
+		return 1;
+	}
+	/* We just should't get there */
+	panic("siop_intr: I shouldn't be there !");
+	return 1;
+end:
+	/*
+	 * restart the script now if command completed properly
+	 * Otherwise wait for siop_scsicmd_end(), it may need to put
+	 * a cmd in front of the queue
+	 */
+	if (letoh32(siop_cmd->siop_tables.status) == SCSI_OK &&
+	    TAILQ_FIRST(&sc->urgent_list) != NULL)
+		CALL_SCRIPT(Ent_script_sched);
+	else
+		restart = 1;
+	siop_scsicmd_end(siop_cmd);
+	siop_lun->siop_tag[tag].active = NULL;
+	if (siop_cmd->status == CMDST_FREE) {
+		TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next);
+		siop_lun->lun_flags &= ~SIOP_LUNF_FULL;
+		if (freetarget && siop_target->status == TARST_PROBING)
+			siop_del_dev(sc, target, lun);
+	}
+	siop_start(sc);
+	if (restart)
+		CALL_SCRIPT(Ent_script_sched);
+	return 1;
+}
+
+void
+siop_scsicmd_end(siop_cmd)
+	struct siop_cmd *siop_cmd;
+{
+	struct scsi_xfer *xs = siop_cmd->xs;
+	struct siop_softc *sc = siop_cmd->siop_sc;
+
+	switch(letoh32(siop_cmd->siop_tables.status)) {
+	case SCSI_OK:
+		xs->error = (siop_cmd->status == CMDST_DONE) ?
+		    XS_NOERROR : XS_SENSE;
+		break;
+	case SCSI_BUSY:
+		xs->error = XS_BUSY;
+		break;
+	case SCSI_CHECK:
+		if (siop_cmd->status == CMDST_SENSE_DONE) {
+			/* request sense on a request sense ? */
+			printf("request sense failed\n");
+			xs->error = XS_DRIVER_STUFFUP;
+		} else {
+			siop_cmd->status = CMDST_SENSE;
+		}
+		break;
+	case SCSI_QUEUE_FULL:
+		{
+		struct siop_lun *siop_lun = siop_cmd->siop_target->siop_lun[
+		    xs->sc_link->lun];
+		/*
+		 * device didn't queue the command. We have to
+		 * retry it.
+		 * We insert it in the urgent list, hoping to preserve order.
+		 * But unfortunably, commands already in the scheduler may
+		 * be accepted before this one.
+		 * Also remember the condition, to avoid starting new commands
+		 * for this device before one is done.
+		 */
+		INCSTAT(siop_stat_intr_qfull);
+#ifdef SIOP_DEBUG
+		printf("%s:%d:%d: queue full (tag %d)\n", sc->sc_dev.dv_xname,
+		    xs->sc_link->target,
+		    xs->sc_link->lun, siop_cmd->tag);
+#endif
+		timeout_del(&xs->stimeout);
+		siop_lun->lun_flags |= SIOP_LUNF_FULL;
+		siop_cmd->status = CMDST_READY;
+		siop_setuptables(siop_cmd);
+		TAILQ_INSERT_TAIL(&sc->urgent_list, siop_cmd, next);
+		return;
+		}
+	case SCSI_SIOP_NOCHECK:
+		/*
+		 * don't check status, xs->error is already valid
+		 */
+		break;
+	case SCSI_SIOP_NOSTATUS:
+		/*
+		 * the status byte was not updated, cmd was
+		 * aborted
+		 */
+		xs->error = XS_SELTIMEOUT;
+		break;
+	default:
+		xs->error = XS_DRIVER_STUFFUP;
+	}
+	if (siop_cmd->status != CMDST_SENSE_DONE &&
+	    xs->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)) {
+		bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data,
+		    (xs->flags & SCSI_DATA_IN) ?
+		    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
+		bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data);
+	}
+	bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd);
+	if (siop_cmd->status == CMDST_SENSE) {
+		/* issue a request sense for this target */
+		int error;
+		siop_cmd->rs_cmd.opcode = REQUEST_SENSE;
+		siop_cmd->rs_cmd.byte2 = xs->sc_link->lun << 5;
+		siop_cmd->rs_cmd.unused[0] = siop_cmd->rs_cmd.unused[1] = 0;
+		siop_cmd->rs_cmd.length = sizeof(struct scsi_sense_data);
+		siop_cmd->rs_cmd.control = 0;
+		siop_cmd->flags &= ~CMDFL_TAG;
+		error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd,
+		    &siop_cmd->rs_cmd, sizeof(struct scsi_sense),
+		    NULL, BUS_DMA_NOWAIT);
+		if (error) {
+			printf("%s: unable to load cmd DMA map: %d",
+			    sc->sc_dev.dv_xname, error);
+			xs->error = XS_DRIVER_STUFFUP;
+			goto out;
+		}
+		error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data,
+		    &xs->sense, sizeof(struct scsi_sense_data),
+		    NULL, BUS_DMA_NOWAIT);
+		if (error) {
+			printf("%s: unable to load sense DMA map: %d",
+			    sc->sc_dev.dv_xname, error);
+			xs->error = XS_DRIVER_STUFFUP;
+			bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd);
+			goto out;
+		}
+		bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data,
+		    BUS_DMASYNC_PREREAD);
+		bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd,
+		    BUS_DMASYNC_PREWRITE);
+
+		siop_setuptables(siop_cmd);
+		/* arrange for the cmd to be handled now */
+		TAILQ_INSERT_HEAD(&sc->urgent_list, siop_cmd, next);
+		return;
+	} else if (siop_cmd->status == CMDST_SENSE_DONE) {
+		bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data,
+		    BUS_DMASYNC_POSTREAD);
+		bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data);
+	}
+out:
+	timeout_del(&siop_cmd->xs->stimeout);
+	siop_cmd->status = CMDST_FREE;
+	xs->flags |= ITSDONE;
+	xs->resid = 0;
+	if ((xs->flags & SCSI_POLL) == 0)
+		scsi_done (xs);
+}
+
+/*
+ * handle a rejected queue tag message: the command will run untagged,
+ * has to adjust the reselect script.
+ */
+int
+siop_handle_qtag_reject(siop_cmd)
+	struct siop_cmd *siop_cmd;
+{
+	struct siop_softc *sc = siop_cmd->siop_sc;
+	int target = siop_cmd->xs->sc_link->target;
+	int lun = siop_cmd->xs->sc_link->lun;
+	int tag = siop_cmd->siop_tables.msg_out[2];
+	struct siop_lun *siop_lun = sc->targets[target]->siop_lun[lun];
+
+#ifdef SIOP_DEBUG
+	printf("%s:%d:%d: tag message %d (%d) rejected (status %d)\n",
+	    sc->sc_dev.dv_xname, target, lun, tag, siop_cmd->tag,
+	    siop_cmd->status);
+#endif
+
+	if (siop_lun->siop_tag[0].active != NULL) {
+		printf("%s: untagged command already running for target %d "
+		    "lun %d (status %d)\n", sc->sc_dev.dv_xname, target, lun,
+		    siop_lun->siop_tag[0].active->status);
+		return -1;
+	}
+	/* clear tag slot */
+	siop_lun->siop_tag[tag].active = NULL;
+	/* add command to non-tagged slot */
+	siop_lun->siop_tag[0].active = siop_cmd;
+	siop_cmd->tag = 0;
+	/* adjust reselect script if there is one */
+	if (siop_lun->siop_tag[0].reseloff > 0) {
+		siop_script_write(sc,
+		    siop_lun->siop_tag[0].reseloff + 1,
+		    siop_cmd->dsa + sizeof(struct siop_xfer_common) +
+		    Ent_ldsa_reload_dsa);
+		siop_table_sync(siop_cmd, BUS_DMASYNC_PREWRITE);
+	}
+	return 0;
+}
+
+/*
+ * handle a bus reset: reset chip, unqueue all active commands, free all
+ * target struct and report loosage to upper layer.
+ * As the upper layer may requeue immediatly we have to first store
+ * all active commands in a temporary queue.
+ */
+void
+siop_handle_reset(sc)
+	struct siop_softc *sc;
+{
+	struct cmd_list reset_list;
+	struct siop_cmd *siop_cmd, *next_siop_cmd;
+	struct siop_lun *siop_lun;
+	int target, lun, tag;
+	/*
+	 * scsi bus reset. reset the chip and restart
+	 * the queue. Need to clean up all active commands
+	 */
+	printf("%s: scsi bus reset\n", sc->sc_dev.dv_xname);
+	/* stop, reset and restart the chip */
+	siop_reset(sc);
+	TAILQ_INIT(&reset_list);
+	/*
+	 * Process all commands: first commmands being executed
+	 */
+	for (target = 0; target < sc->sc_link.adapter_buswidth;
+	    target++) {
+		if (sc->targets[target] == NULL)
+			continue;
+		for (lun = 0; lun < 8; lun++) {
+			siop_lun = sc->targets[target]->siop_lun[lun];
+			if (siop_lun == NULL)
+				continue;
+			siop_lun->lun_flags &= ~SIOP_LUNF_FULL;
+			for (tag = 0; tag <
+			    ((sc->targets[target]->flags & TARF_TAG) ?
+			    SIOP_NTAG : 1);
+			    tag++) {
+				siop_cmd = siop_lun->siop_tag[tag].active;
+				if (siop_cmd == NULL)
+					continue;
+				printf("cmd %p (target %d:%d) in reset list\n",
+				    siop_cmd, target, lun);
+				TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next);
+				siop_lun->siop_tag[tag].active = NULL;
+			}
+		}
+		sc->targets[target]->status = TARST_ASYNC;
+		sc->targets[target]->flags &= ~TARF_ISWIDE;
+	}
+	/* Next commands from the urgent list */
+	for (siop_cmd = TAILQ_FIRST(&sc->urgent_list); siop_cmd != NULL;
+	    siop_cmd = next_siop_cmd) {
+		next_siop_cmd = TAILQ_NEXT(siop_cmd, next);
+		siop_cmd->flags &= ~CMDFL_TAG;
+		printf("cmd %p (target %d:%d) in reset list (wait)\n",
+		    siop_cmd, siop_cmd->xs->sc_link->target,
+		    siop_cmd->xs->sc_link->lun);
+		TAILQ_REMOVE(&sc->urgent_list, siop_cmd, next);
+		TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next);
+	}
+	/* Then command waiting in the input list */
+	for (siop_cmd = TAILQ_FIRST(&sc->ready_list); siop_cmd != NULL;
+	    siop_cmd = next_siop_cmd) {
+		next_siop_cmd = TAILQ_NEXT(siop_cmd, next);
+		siop_cmd->flags &= ~CMDFL_TAG;
+		printf("cmd %p (target %d:%d) in reset list (wait)\n",
+		    siop_cmd, siop_cmd->xs->sc_link->target,
+		    siop_cmd->xs->sc_link->lun);
+		TAILQ_REMOVE(&sc->ready_list, siop_cmd, next);
+		TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next);
+	}
+
+	for (siop_cmd = TAILQ_FIRST(&reset_list); siop_cmd != NULL;
+	    siop_cmd = next_siop_cmd) {
+		next_siop_cmd = TAILQ_NEXT(siop_cmd, next);
+		siop_cmd->xs->error = (siop_cmd->flags & CMDFL_TIMEOUT) ?
+		    XS_TIMEOUT : XS_RESET;
+		siop_cmd->siop_tables.status = htole32(SCSI_SIOP_NOCHECK);
+		printf("cmd %p (status %d) about to be processed\n", siop_cmd,
+		    siop_cmd->status);
+		if (siop_cmd->status == CMDST_SENSE ||
+		    siop_cmd->status == CMDST_SENSE_ACTIVE) 
+			siop_cmd->status = CMDST_SENSE_DONE;
+		else
+			siop_cmd->status = CMDST_DONE;
+		TAILQ_REMOVE(&reset_list, siop_cmd, next);
+		siop_scsicmd_end(siop_cmd);
+		TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next);
+	}
+}
+
+int
+siop_scsicmd(xs)
+	struct scsi_xfer *xs;
+{
+	struct siop_softc *sc = (struct siop_softc *)xs->sc_link->adapter_softc;
+	struct siop_cmd *siop_cmd;
+	int s, error, i;
+	const int target = xs->sc_link->target;
+	const int lun = xs->sc_link->lun;
+
+	s = splbio();
+#ifdef SIOP_DEBUG_SCHED
+	printf("starting cmd for %d:%d\n", target, lun);
+#endif
+	siop_cmd = TAILQ_FIRST(&sc->free_list);
+	if (siop_cmd) {
+		TAILQ_REMOVE(&sc->free_list, siop_cmd, next);
+	} else {
+		if (siop_morecbd(sc) == 0) {
+			siop_cmd = TAILQ_FIRST(&sc->free_list);
+#ifdef DIAGNOSTIC
+			if (siop_cmd == NULL)
+				panic("siop_morecbd succeed and does nothing");
+#endif
+			TAILQ_REMOVE(&sc->free_list, siop_cmd, next);
+		}
+	}
+	if (siop_cmd == NULL) {
+		xs->error = XS_DRIVER_STUFFUP;
+		splx(s);
+		return(TRY_AGAIN_LATER);
+	}
+
+	/* Always reset xs->stimeout, lest we timeout_del() with trash */
+	timeout_set(&xs->stimeout, siop_timeout, siop_cmd);
+
+#ifdef DIAGNOSTIC
+	if (siop_cmd->status != CMDST_FREE)
+		panic("siop_scsicmd: new cmd not free");
+#endif
+	if (sc->targets[target] == NULL) {
+#ifdef SIOP_DEBUG
+		printf("%s: alloc siop_target for target %d\n",
+			sc->sc_dev.dv_xname, target);
+#endif
+		sc->targets[target] =
+		    malloc(sizeof(struct siop_target), M_DEVBUF, M_NOWAIT);
+		if (sc->targets[target] == NULL) {
+			printf("%s: can't malloc memory for target %d\n",
+			    sc->sc_dev.dv_xname, target);
+			xs->error = XS_DRIVER_STUFFUP;
+			splx(s);
+			return(TRY_AGAIN_LATER);
+		}
+		sc->targets[target]->status = TARST_PROBING;
+		sc->targets[target]->flags = 0;
+		sc->targets[target]->id = sc->clock_div << 24; /* scntl3 */
+		sc->targets[target]->id |=  target << 16; /* id */
+		/* sc->targets[target]->id |= 0x0 << 8; scxfer is 0 */
+
+		/* get a lun switch script */
+		sc->targets[target]->lunsw = siop_get_lunsw(sc);
+		if (sc->targets[target]->lunsw == NULL) {
+			printf("%s: can't alloc lunsw for target %d\n",
+			    sc->sc_dev.dv_xname, target);
+			xs->error = XS_DRIVER_STUFFUP;
+			splx(s);
+			return(TRY_AGAIN_LATER);
+		}
+		for (i=0; i < 8; i++)
+			sc->targets[target]->siop_lun[i] = NULL;
+		siop_add_reselsw(sc, target);
+	}
+	if (sc->targets[target]->siop_lun[lun] == NULL) {
+		sc->targets[target]->siop_lun[lun] =
+		    malloc(sizeof(struct siop_lun), M_DEVBUF, M_NOWAIT);
+		if (sc->targets[target]->siop_lun[lun] == NULL) {
+			printf("%s: can't alloc siop_lun for target %d "
+			    "lun %d\n", sc->sc_dev.dv_xname, target, lun);
+			xs->error = XS_DRIVER_STUFFUP;
+			splx(s);
+			return(TRY_AGAIN_LATER);
+		}
+		memset(sc->targets[target]->siop_lun[lun], 0,
+		    sizeof(struct siop_lun));
+	}
+	siop_cmd->siop_target = sc->targets[target];
+	siop_cmd->xs = xs;
+	siop_cmd->flags = 0;
+	siop_cmd->status = CMDST_READY;
+
+	/* load the DMA maps */
+	error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd,
+	    xs->cmd, xs->cmdlen, NULL, BUS_DMA_NOWAIT);
+	if (error) {
+		printf("%s: unable to load cmd DMA map: %d",
+		    sc->sc_dev.dv_xname, error);
+		xs->error = XS_DRIVER_STUFFUP;
+		splx(s);
+		return(TRY_AGAIN_LATER);
+	}
+	if (xs->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)) {
+		error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data,
+		    xs->data, xs->datalen, NULL, BUS_DMA_NOWAIT);
+		if (error) {
+			printf("%s: unable to load cmd DMA map: %d",
+			    sc->sc_dev.dv_xname, error);
+			xs->error = XS_DRIVER_STUFFUP;
+			bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd);
+			splx(s);
+			return(TRY_AGAIN_LATER);
+		}
+		bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data,
+		    (xs->flags & SCSI_DATA_IN) ?
+		    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
+	}
+	bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd,
+	    BUS_DMASYNC_PREWRITE);
+
+	siop_setuptables(siop_cmd);
+
+	TAILQ_INSERT_TAIL(&sc->ready_list, siop_cmd, next);
+
+	siop_start(sc);
+	if (xs->flags & SCSI_POLL) {
+		/* poll for command completion */
+		while ((xs->flags & ITSDONE) == 0) {
+			delay(1000);
+			siop_intr(sc);
+		}
+		splx(s);
+		return (COMPLETE);
+	}
+	splx(s);
+	return (SUCCESSFULLY_QUEUED);
+}
+
+void
+siop_start(sc)
+	struct siop_softc *sc;
+{
+	struct siop_cmd *siop_cmd, *next_siop_cmd;
+	struct siop_lun *siop_lun;
+	u_int32_t dsa;
+	int timeout;
+	int target, lun, tag, slot;
+	int newcmd = 0; 
+	int doingready = 0;
+
+	/*
+	 * first make sure to read valid data
+	 */
+	siop_script_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+	/*
+	 * The queue management here is a bit tricky: the script always looks
+	 * at the slot from first to last, so if we always use the first 
+	 * free slot commands can stay at the tail of the queue ~forever.
+	 * The algorithm used here is to restart from the head when we know
+	 * that the queue is empty, and only add commands after the last one.
+	 * When we're at the end of the queue wait for the script to clear it.
+	 * The best thing to do here would be to implement a circular queue,
+	 * but using only 53c720 features this can be "interesting".
+	 * A mid-way solution could be to implement 2 queues and swap orders.
+	 */
+	slot = sc->sc_currschedslot;
+	/*
+	 * If the instruction is 0x80000000 (JUMP foo, IF FALSE) the slot is
+	 * free. As this is the last used slot, all previous slots are free,
+	 * we can restart from 1.
+	 * slot 0 is reserved for request sense commands.
+	 */
+	if (siop_script_read(sc, (Ent_script_sched_slot0 / 4) + slot * 2) ==
+	    0x80000000) {
+		slot = sc->sc_currschedslot = 1;
+	} else {
+		slot++;
+	}
+	/* first handle commands from the urgent list */
+	siop_cmd = TAILQ_FIRST(&sc->urgent_list);
+again:
+	for (; siop_cmd != NULL; siop_cmd = next_siop_cmd) {
+		next_siop_cmd = TAILQ_NEXT(siop_cmd, next);
+#ifdef DIAGNOSTIC
+		if (siop_cmd->status != CMDST_READY &&
+		    siop_cmd->status != CMDST_SENSE)
+			panic("siop: non-ready cmd in ready list");
+#endif	
+		target = siop_cmd->xs->sc_link->target;
+		lun = siop_cmd->xs->sc_link->lun;
+		siop_lun = sc->targets[target]->siop_lun[lun];
+		/* if non-tagged command active, wait */
+		if (siop_lun->siop_tag[0].active != NULL)
+			continue;
+		/*
+		 * if we're in a queue full condition don't start a new
+		 * command, unless it's a request sense
+		 */
+		if ((siop_lun->lun_flags & SIOP_LUNF_FULL) &&
+		    siop_cmd->status == CMDST_READY)
+			continue;
+		/* find a free tag if needed */
+		if (siop_cmd->flags & CMDFL_TAG) {
+			for (tag = 1; tag < SIOP_NTAG; tag++) {
+				if (siop_lun->siop_tag[tag].active == NULL)
+					break;
+			}
+			if (tag == SIOP_NTAG) /* no free tag */
+				continue;
+		} else {
+			tag = 0;
+		}
+		siop_cmd->tag = tag;
+		/*
+		 * find a free scheduler slot and load it. If it's a request
+		 * sense we need to use slot 0.
+		 */
+		if (siop_cmd->status != CMDST_SENSE) {
+			for (; slot < SIOP_NSLOTS; slot++) {
+				/*
+				 * If cmd if 0x80000000 the slot is free
+				 */
+				if (siop_script_read(sc,
+				    (Ent_script_sched_slot0 / 4) + slot * 2) ==
+				    0x80000000)
+					break;
+			}
+			/* no more free slot, no need to continue */
+			if (slot == SIOP_NSLOTS) {
+				goto end;
+			}
+		} else {
+			slot = 0;
+			if (siop_script_read(sc, Ent_script_sched_slot0 / 4)
+			    != 0x80000000) 
+				goto end;
+		}
+
+#ifdef SIOP_DEBUG_SCHED
+		printf("using slot %d for DSA 0x%lx\n", slot,
+		    (u_long)siop_cmd->dsa);
+#endif
+		/* Ok, we can add the tag message */
+		if (tag > 0) {
+#ifdef DIAGNOSTIC
+			int msgcount =
+			    letoh32(siop_cmd->siop_tables.t_msgout.count);
+			if (msgcount != 1)
+				printf("%s:%d:%d: tag %d with msgcount %d\n",
+				    sc->sc_dev.dv_xname, target, lun, tag,
+				    msgcount);
+#endif
+			if (siop_cmd->xs->bp != NULL &&
+			    (siop_cmd->xs->bp->b_flags & B_ASYNC))
+				siop_cmd->siop_tables.msg_out[1] =
+				    MSG_SIMPLE_Q_TAG;
+			else
+				siop_cmd->siop_tables.msg_out[1] =
+				    MSG_ORDERED_Q_TAG;
+			siop_cmd->siop_tables.msg_out[2] = tag;
+			siop_cmd->siop_tables.t_msgout.count = htole32(3);
+		}
+		/* note that we started a new command */
+		newcmd = 1;
+		/* mark command as active */
+		if (siop_cmd->status == CMDST_READY) {
+			siop_cmd->status = CMDST_ACTIVE;
+		} else if (siop_cmd->status == CMDST_SENSE) {
+			siop_cmd->status = CMDST_SENSE_ACTIVE;
+		} else
+			panic("siop_start: bad status");
+		if (doingready)
+			TAILQ_REMOVE(&sc->ready_list, siop_cmd, next);
+		else
+			TAILQ_REMOVE(&sc->urgent_list, siop_cmd, next);
+		siop_lun->siop_tag[tag].active = siop_cmd;
+		/* patch scripts with DSA addr */
+		dsa = siop_cmd->dsa;
+		/* first reselect switch, if we have an entry */
+		if (siop_lun->siop_tag[tag].reseloff > 0)
+			siop_script_write(sc,
+			    siop_lun->siop_tag[tag].reseloff + 1,
+			    dsa + sizeof(struct siop_xfer_common) +
+			    Ent_ldsa_reload_dsa);
+		/* CMD script: MOVE MEMORY addr */
+		siop_cmd->siop_xfer->resel[E_ldsa_abs_slot_Used[0]] = 
+		   htole32(sc->sc_scriptaddr + Ent_script_sched_slot0 +
+		   slot * 8);
+		siop_table_sync(siop_cmd, BUS_DMASYNC_PREWRITE);
+		/* scheduler slot: JUMP ldsa_select */
+		siop_script_write(sc,
+		    (Ent_script_sched_slot0 / 4) + slot * 2 + 1,
+		    dsa + sizeof(struct siop_xfer_common) + Ent_ldsa_select);
+		/* handle timeout */
+		if (siop_cmd->status == CMDST_ACTIVE) {
+			if ((siop_cmd->xs->flags & SCSI_POLL) == 0) {
+				/* start exire timer */
+				timeout = (u_int64_t) siop_cmd->xs->timeout *
+				    (u_int64_t)hz / 1000;
+				if (timeout == 0)
+					timeout = 1;
+				timeout_add(&siop_cmd->xs->stimeout, timeout);
+			}
+		}
+		/*
+		 * Change JUMP cmd so that this slot will be handled
+		 */
+		siop_script_write(sc, (Ent_script_sched_slot0 / 4) + slot * 2,
+		    0x80080000);
+		/* if we're using the request sense slot, stop here */
+		if (slot == 0)
+			goto end;
+		sc->sc_currschedslot = slot;
+		slot++;
+	}
+	if (doingready == 0) {
+		/* now process ready list */
+		doingready = 1;
+		siop_cmd = TAILQ_FIRST(&sc->ready_list);
+		goto again;
+	}
+
+end:
+	/* if nothing changed no need to flush cache and wakeup script */
+	if (newcmd == 0)
+		return;
+	/* make sure SCRIPT processor will read valid data */
+	siop_script_sync(sc,BUS_DMASYNC_PREREAD |  BUS_DMASYNC_PREWRITE);
+	/* Signal script it has some work to do */
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SIGP);
+	/* and wait for IRQ */
+	return;
+}
+
+void
+siop_timeout(v)
+	void *v;
+{
+	struct siop_cmd *siop_cmd = v;
+	struct siop_softc *sc = siop_cmd->siop_sc;
+	int s;
+
+	sc_print_addr(siop_cmd->xs->sc_link);
+	printf("command timeout\n");
+
+	s = splbio();
+	/* reset the scsi bus */
+	siop_resetbus(sc);
+
+	/* deactivate callout */
+	timeout_del(&siop_cmd->xs->stimeout);
+	/* mark command as being timed out; siop_intr will handle it */
+	/*
+	 * mark command has being timed out and just return;
+	 * the bus reset will generate an interrupt,
+	 * it will be handled in siop_intr()
+	 */
+	siop_cmd->flags |= CMDFL_TIMEOUT;
+	splx(s);
+	return;
+
+}
+
+void
+siop_dump_script(sc)
+	struct siop_softc *sc;
+{
+	int i;
+	for (i = 0; i < PAGE_SIZE / 4; i += 2) {
+		printf("0x%04x: 0x%08x 0x%08x", i * 4,
+		    letoh32(sc->sc_script[i]), letoh32(sc->sc_script[i+1]));
+		if ((letoh32(sc->sc_script[i]) & 0xe0000000) == 0xc0000000) {
+			i++;
+			printf(" 0x%08x", letoh32(sc->sc_script[i+1]));
+		}
+		printf("\n");
+	}
+}
+
+int
+siop_morecbd(sc)
+	struct siop_softc *sc;
+{
+	int error, i, j;
+	bus_dma_segment_t seg;
+	int rseg;
+	struct siop_cbd *newcbd;
+	bus_addr_t dsa;
+	u_int32_t *scr;
+
+	/* allocate a new list head */
+	newcbd = malloc(sizeof(struct siop_cbd), M_DEVBUF, M_NOWAIT);
+	if (newcbd == NULL) {
+		printf("%s: can't allocate memory for command descriptors "
+		    "head\n", sc->sc_dev.dv_xname);
+		return ENOMEM;
+	}
+	memset(newcbd, 0, sizeof(struct siop_cbd));
+
+	/* allocate cmd list */
+	newcbd->cmds =
+	    malloc(sizeof(struct siop_cmd) * SIOP_NCMDPB, M_DEVBUF, M_NOWAIT);
+	if (newcbd->cmds == NULL) {
+		printf("%s: can't allocate memory for command descriptors\n",
+		    sc->sc_dev.dv_xname);
+		error = ENOMEM;
+		goto bad3;
+	}
+	memset(newcbd->cmds, 0, sizeof(struct siop_cmd) * SIOP_NCMDPB);
+	error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE, 0, &seg,
+	    1, &rseg, BUS_DMA_NOWAIT);
+	if (error) {
+		printf("%s: unable to allocate cbd DMA memory, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto bad2;
+	}
+	error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, PAGE_SIZE,
+	    (caddr_t *)&newcbd->xfers, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
+	if (error) {
+		printf("%s: unable to map cbd DMA memory, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto bad2;
+	}
+	error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE, 0,
+	    BUS_DMA_NOWAIT, &newcbd->xferdma);
+	if (error) {
+		printf("%s: unable to create cbd DMA map, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto bad1;
+	}
+	error = bus_dmamap_load(sc->sc_dmat, newcbd->xferdma, newcbd->xfers,
+	    PAGE_SIZE, NULL, BUS_DMA_NOWAIT);
+	if (error) {
+		printf("%s: unable to load cbd DMA map, error = %d\n",
+		    sc->sc_dev.dv_xname, error);
+		goto bad0;
+	}
+#ifdef DEBUG
+	printf("%s: alloc newcdb at PHY addr 0x%lx\n", sc->sc_dev.dv_xname,
+	    (unsigned long)newcbd->xferdma->dm_segs[0].ds_addr);
+#endif
+	
+	for (i = 0; i < SIOP_NCMDPB; i++) {
+		error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, SIOP_NSG,
+		    MAXPHYS, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
+		    &newcbd->cmds[i].dmamap_data);
+		if (error) {
+			printf("%s: unable to create data DMA map for cbd: "
+			    "error %d\n",
+			    sc->sc_dev.dv_xname, error);
+			goto bad0;
+		}
+		error = bus_dmamap_create(sc->sc_dmat,
+		    sizeof(struct scsi_generic), 1,
+		    sizeof(struct scsi_generic), 0,
+		    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
+		    &newcbd->cmds[i].dmamap_cmd);
+		if (error) {
+			printf("%s: unable to create cmd DMA map for cbd %d\n",
+			    sc->sc_dev.dv_xname, error);
+			goto bad0;
+		}
+		newcbd->cmds[i].siop_sc = sc;
+		newcbd->cmds[i].siop_cbdp = newcbd;
+		newcbd->cmds[i].siop_xfer = &newcbd->xfers[i];
+		memset(newcbd->cmds[i].siop_xfer, 0,
+		    sizeof(struct siop_xfer));
+		newcbd->cmds[i].dsa = newcbd->xferdma->dm_segs[0].ds_addr +
+		    i * sizeof(struct siop_xfer);
+		dsa = newcbd->cmds[i].dsa;
+		newcbd->cmds[i].status = CMDST_FREE;
+		newcbd->cmds[i].siop_tables.t_msgout.count= htole32(1);
+		newcbd->cmds[i].siop_tables.t_msgout.addr = htole32(dsa);
+		newcbd->cmds[i].siop_tables.t_msgin.count= htole32(1);
+		newcbd->cmds[i].siop_tables.t_msgin.addr = htole32(dsa + 8);
+		newcbd->cmds[i].siop_tables.t_extmsgin.count= htole32(2);
+		newcbd->cmds[i].siop_tables.t_extmsgin.addr = htole32(dsa + 9);
+		newcbd->cmds[i].siop_tables.t_extmsgdata.addr =
+		    htole32(dsa + 11);
+		newcbd->cmds[i].siop_tables.t_status.count= htole32(1);
+		newcbd->cmds[i].siop_tables.t_status.addr = htole32(dsa + 16);
+
+		/* The select/reselect script */
+		scr = &newcbd->cmds[i].siop_xfer->resel[0];
+		for (j = 0; j < sizeof(load_dsa) / sizeof(load_dsa[0]); j++)
+			scr[j] = htole32(load_dsa[j]);
+		/*
+		 * 0x78000000 is a 'move data8 to reg'. data8 is the second
+		 * octet, reg offset is the third.
+		 */
+		scr[Ent_rdsa0 / 4] =
+		    htole32(0x78100000 | ((dsa & 0x000000ff) <<  8));
+		scr[Ent_rdsa1 / 4] =
+		    htole32(0x78110000 | ( dsa & 0x0000ff00       ));
+		scr[Ent_rdsa2 / 4] =
+		    htole32(0x78120000 | ((dsa & 0x00ff0000) >>  8));
+		scr[Ent_rdsa3 / 4] =
+		    htole32(0x78130000 | ((dsa & 0xff000000) >> 16));
+		scr[E_ldsa_abs_reselected_Used[0]] =
+		    htole32(sc->sc_scriptaddr + Ent_reselected);
+		scr[E_ldsa_abs_reselect_Used[0]] =
+		    htole32(sc->sc_scriptaddr + Ent_reselect);
+		scr[E_ldsa_abs_selected_Used[0]] =
+		    htole32(sc->sc_scriptaddr + Ent_selected);
+		scr[E_ldsa_abs_data_Used[0]] =
+		    htole32(dsa + sizeof(struct siop_xfer_common) +
+		    Ent_ldsa_data);
+		/* JUMP foo, IF FALSE - used by MOVE MEMORY to clear the slot */
+		scr[Ent_ldsa_data / 4] = htole32(0x80000000);
+		TAILQ_INSERT_TAIL(&sc->free_list, &newcbd->cmds[i], next);
+#ifdef SIOP_DEBUG
+		printf("tables[%d]: in=0x%x out=0x%x status=0x%x\n", i,
+		    letoh32(newcbd->cmds[i].siop_tables.t_msgin.addr),
+		    letoh32(newcbd->cmds[i].siop_tables.t_msgout.addr),
+		    letoh32(newcbd->cmds[i].siop_tables.t_status.addr));
+#endif
+	}
+	TAILQ_INSERT_TAIL(&sc->cmds, newcbd, next);
+	return 0;
+bad0:
+	bus_dmamap_destroy(sc->sc_dmat, newcbd->xferdma);
+bad1:
+	bus_dmamem_free(sc->sc_dmat, &seg, rseg);
+bad2:
+	free(newcbd->cmds, M_DEVBUF);
+bad3:
+	free(newcbd, M_DEVBUF);
+	return error;
+}
+
+struct siop_lunsw *
+siop_get_lunsw(sc)
+	struct siop_softc *sc;
+{
+	struct siop_lunsw *lunsw;
+	int i;
+
+	if (sc->script_free_lo + (sizeof(lun_switch) / sizeof(lun_switch[0])) >=
+	    sc->script_free_hi)
+		return NULL;
+	lunsw = TAILQ_FIRST(&sc->lunsw_list);
+	if (lunsw != NULL) {
+#ifdef SIOP_DEBUG
+		printf("siop_get_lunsw got lunsw at offset %d\n",
+		    lunsw->lunsw_off);
+#endif
+		TAILQ_REMOVE(&sc->lunsw_list, lunsw, next);
+		return lunsw;
+	}
+	lunsw = malloc(sizeof(struct siop_lunsw), M_DEVBUF, M_NOWAIT);
+	if (lunsw == NULL)
+		return NULL;
+	memset(lunsw, 0, sizeof(struct siop_lunsw));
+#ifdef SIOP_DEBUG
+	printf("allocating lunsw at offset %d\n", sc->script_free_lo);
+#endif
+	if (sc->features & SF_CHIP_RAM) {
+		bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh,
+		    sc->script_free_lo * 4, lun_switch,
+		    sizeof(lun_switch) / sizeof(lun_switch[0]));
+		bus_space_write_4(sc->sc_ramt, sc->sc_ramh,
+		    (sc->script_free_lo + E_abs_lunsw_return_Used[0]) * 4,
+		    sc->sc_scriptaddr + Ent_lunsw_return);
+	} else {
+		for (i = 0; i < sizeof(lun_switch) / sizeof(lun_switch[0]);
+		    i++)
+			sc->sc_script[sc->script_free_lo + i] =
+			    htole32(lun_switch[i]);
+		sc->sc_script[sc->script_free_lo + E_abs_lunsw_return_Used[0]] = 
+		    htole32(sc->sc_scriptaddr + Ent_lunsw_return);
+	}
+	lunsw->lunsw_off = sc->script_free_lo;
+	lunsw->lunsw_size = sizeof(lun_switch) / sizeof(lun_switch[0]);
+	sc->script_free_lo += lunsw->lunsw_size;
+	if (sc->script_free_lo > 1024)
+		printf("%s: script_free_lo (%d) > 1024\n", sc->sc_dev.dv_xname,
+		    sc->script_free_lo);
+	siop_script_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+	return lunsw;
+}
+
+void
+siop_add_reselsw(sc, target)
+	struct siop_softc *sc;
+	int target;
+{
+	int i;
+	struct siop_lun *siop_lun;
+	/*
+	 * add an entry to resel switch
+	 */
+	siop_script_sync(sc, BUS_DMASYNC_POSTWRITE);
+	for (i = 0; i < 15; i++) {
+		sc->targets[target]->reseloff = Ent_resel_targ0 / 4 + i * 2;
+		if ((siop_script_read(sc, sc->targets[target]->reseloff) & 0xff)
+		    == 0xff) { /* it's free */
+#ifdef SIOP_DEBUG
+			printf("siop: target %d slot %d offset %d\n",
+			    target, i, sc->targets[target]->reseloff);
+#endif
+			/* JUMP abs_foo, IF target | 0x80; */
+			siop_script_write(sc, sc->targets[target]->reseloff,
+			    0x800c0080 | target);
+			siop_script_write(sc, sc->targets[target]->reseloff + 1,
+			    sc->sc_scriptaddr +
+			    sc->targets[target]->lunsw->lunsw_off * 4 +
+			    Ent_lun_switch_entry);
+			break;
+		}
+	}
+	if (i == 15) /* no free slot, shouldn't happen */
+		panic("siop: resel switch full");
+
+	sc->sc_ntargets++;
+	for (i = 0; i < 8; i++) {
+		siop_lun = sc->targets[target]->siop_lun[i];
+		if (siop_lun == NULL)
+			continue;
+		if (siop_lun->reseloff > 0) {
+			siop_lun->reseloff = 0;
+			siop_add_dev(sc, target, i);
+		}
+	}
+	siop_update_scntl3(sc, sc->targets[target]);
+	siop_script_sync(sc, BUS_DMASYNC_PREWRITE);
+}
+
+void
+siop_update_scntl3(sc, siop_target)
+	struct siop_softc *sc;
+	struct siop_target *siop_target;
+{
+	/* MOVE target->id >> 24 TO SCNTL3 */
+	siop_script_write(sc,
+	    siop_target->lunsw->lunsw_off + (Ent_restore_scntl3 / 4),
+	    0x78030000 | ((siop_target->id >> 16) & 0x0000ff00));
+	/* MOVE target->id >> 8 TO SXFER */
+	siop_script_write(sc,
+	    siop_target->lunsw->lunsw_off + (Ent_restore_scntl3 / 4) + 2,
+	    0x78050000 | (siop_target->id & 0x0000ff00));
+	siop_script_sync(sc, BUS_DMASYNC_PREWRITE);
+}
+
+void
+siop_add_dev(sc, target, lun)
+	struct siop_softc *sc;
+	int target;
+	int lun;
+{
+	struct siop_lunsw *lunsw;
+	struct siop_lun *siop_lun = sc->targets[target]->siop_lun[lun];
+	int i, ntargets;
+
+	if (siop_lun->reseloff > 0)
+		return;
+	lunsw = sc->targets[target]->lunsw;
+	if ((lunsw->lunsw_off + lunsw->lunsw_size) < sc->script_free_lo) {
+		/*
+		 * can't extend this slot. Probably not worth trying to deal
+		 * with this case
+		 */
+#ifdef DEBUG
+		printf("%s:%d:%d: can't allocate a lun sw slot\n",
+		    sc->sc_dev.dv_xname, target, lun);
+#endif
+		return;
+	}
+	/* count how many free targets we still have to probe */
+	ntargets =  (sc->sc_link.adapter_buswidth - 1) - 1 - sc->sc_ntargets;
+
+	/*
+	 * we need 8 bytes for the lun sw additionnal entry, and
+	 * eventually sizeof(tag_switch) for the tag switch entry.
+	 * Keep enouth free space for the free targets that could be
+	 * probed later.
+	 */
+	if (sc->script_free_lo + 2 +
+	    (ntargets * sizeof(lun_switch) / sizeof(lun_switch[0])) >=
+	    ((sc->targets[target]->flags & TARF_TAG) ?
+	    sc->script_free_hi - (sizeof(tag_switch) / sizeof(tag_switch[0])) :
+	    sc->script_free_hi)) {
+		/*
+		 * not enouth space, probably not worth dealing with it.
+		 * We can hold 13 tagged-queuing capable devices in the 4k RAM.
+		 */
+#ifdef DEBUG
+		printf("%s:%d:%d: not enouth memory for a lun sw slot\n",
+		    sc->sc_dev.dv_xname, target, lun);
+#endif
+		return;
+	}
+#ifdef SIOP_DEBUG
+	printf("%s:%d:%d: allocate lun sw entry\n",
+	    sc->sc_dev.dv_xname, target, lun);
+#endif
+	/* INT int_resellun */
+	siop_script_write(sc, sc->script_free_lo, 0x98080000);
+	siop_script_write(sc, sc->script_free_lo + 1, A_int_resellun);
+	/* Now the slot entry: JUMP abs_foo, IF lun */
+	siop_script_write(sc, sc->script_free_lo - 2,
+	    0x800c0000 | lun);
+	siop_script_write(sc, sc->script_free_lo - 1, 0);
+	siop_lun->reseloff = sc->script_free_lo - 2;
+	lunsw->lunsw_size += 2;
+	sc->script_free_lo += 2;
+	if (sc->targets[target]->flags & TARF_TAG) {
+		/* we need a tag switch */
+		sc->script_free_hi -=
+		    sizeof(tag_switch) / sizeof(tag_switch[0]);
+		if (sc->features & SF_CHIP_RAM) {
+			bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh,
+			    sc->script_free_hi * 4, tag_switch,
+			    sizeof(tag_switch) / sizeof(tag_switch[0]));
+		} else {
+			for(i = 0;
+			    i < sizeof(tag_switch) / sizeof(tag_switch[0]);
+			    i++) {
+				sc->sc_script[sc->script_free_hi + i] = 
+				    htole32(tag_switch[i]);
+			}
+		}
+		siop_script_write(sc, 
+		    siop_lun->reseloff + 1,
+		    sc->sc_scriptaddr + sc->script_free_hi * 4 +
+		    Ent_tag_switch_entry);
+
+		for (i = 0; i < SIOP_NTAG; i++) {
+			siop_lun->siop_tag[i].reseloff =
+			    sc->script_free_hi + (Ent_resel_tag0 / 4) + i * 2;
+		}
+	} else {
+		/* non-tag case; just work with the lun switch */
+		siop_lun->siop_tag[0].reseloff = 
+		    sc->targets[target]->siop_lun[lun]->reseloff;
+	}
+	siop_script_sync(sc, BUS_DMASYNC_PREWRITE);
+}
+
+void
+siop_del_dev(sc, target, lun)
+	struct siop_softc *sc;
+	int target;
+	int lun;
+{
+	int i;
+#ifdef SIOP_DEBUG
+		printf("%s:%d:%d: free lun sw entry\n",
+		    sc->sc_dev.dv_xname, target, lun);
+#endif
+	if (sc->targets[target] == NULL)
+		return;
+	free(sc->targets[target]->siop_lun[lun], M_DEVBUF);
+	sc->targets[target]->siop_lun[lun] = NULL;
+	/* XXX compact sw entry too ? */
+	/* check if we can free the whole target */
+	for (i = 0; i < 8; i++) {
+		if (sc->targets[target]->siop_lun[i] != NULL)
+			return;
+	}
+#ifdef SIOP_DEBUG
+	printf("%s: free siop_target for target %d lun %d lunsw offset %d\n",
+	    sc->sc_dev.dv_xname, target, lun,
+	    sc->targets[target]->lunsw->lunsw_off);
+#endif
+	/*
+	 * nothing here, free the target struct and resel
+	 * switch entry
+	 */
+	siop_script_write(sc, sc->targets[target]->reseloff, 0x800c00ff);
+	siop_script_sync(sc, BUS_DMASYNC_PREWRITE);
+	TAILQ_INSERT_TAIL(&sc->lunsw_list, sc->targets[target]->lunsw, next);
+	free(sc->targets[target], M_DEVBUF);
+	sc->targets[target] = NULL;
+	sc->sc_ntargets--;
+}
+
+#ifdef SIOP_STATS
+void
+siop_printstats()
+{
+	printf("siop_stat_intr %d\n", siop_stat_intr);
+	printf("siop_stat_intr_shortxfer %d\n", siop_stat_intr_shortxfer);
+	printf("siop_stat_intr_xferdisc %d\n", siop_stat_intr_xferdisc);
+	printf("siop_stat_intr_sdp %d\n", siop_stat_intr_sdp);
+	printf("siop_stat_intr_done %d\n", siop_stat_intr_done);
+	printf("siop_stat_intr_lunresel %d\n", siop_stat_intr_lunresel);
+	printf("siop_stat_intr_qfull %d\n", siop_stat_intr_qfull);
+}
+#endif
diff --git a/sys/dev/ic/siop_common.c b/sys/dev/ic/siop_common.c
new file mode 100644
index 00000000000..1300c91c117
--- /dev/null
+++ b/sys/dev/ic/siop_common.c
@@ -0,0 +1,568 @@
+/*	$OpenBSD: siop_common.c,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$NetBSD: siop_common.c,v 1.12 2001/02/11 18:04:50 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* SYM53c7/8xx PCI-SCSI I/O Processors driver */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/buf.h>
+#include <sys/kernel.h>
+#include <sys/scsiio.h>
+
+#include <machine/endian.h>
+#include <machine/bus.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsi_message.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/ic/siopreg.h>
+#include <dev/ic/siopvar.h>
+#include <dev/ic/siopvar_common.h>
+
+#undef DEBUG
+#undef DEBUG_DR
+
+void
+siop_common_reset(sc)
+	struct siop_softc *sc;
+{
+	u_int32_t stest3;
+
+	/* reset the chip */
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST);
+	delay(1000);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0);
+
+	/* init registers */
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0,
+	    SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0,
+	    0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL));
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1,
+	    0xff & ~(SIEN1_HTH | SIEN1_GEN));
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0,
+	    (0xb << STIME0_SEL_SHIFT));
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID,
+	    sc->sc_link.adapter_target | SCID_RRE);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0,
+	    1 << sc->sc_link.adapter_target);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
+	    (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM);
+
+	/* enable clock doubler or quadruler if appropriate */
+	if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) {
+		stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3);
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
+		    STEST1_DBLEN);
+		if (sc->features & SF_CHIP_QUAD) {
+			/* wait for PPL to lock */
+			while ((bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_STEST4) & STEST4_LOCK) == 0)
+				delay(10);
+		} else {
+			/* data sheet says 20us - more won't hurt */
+			delay(100);
+		}
+		/* halt scsi clock, select doubler/quad, restart clock */
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3,
+		    stest3 | STEST3_HSC);
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
+		    STEST1_DBLEN | STEST1_DBLSEL);
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3);
+	} else {
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0);
+	}
+	if (sc->features & SF_CHIP_FIFO)
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) |
+		    CTEST5_DFS);
+		
+	sc->sc_reset(sc);
+}
+
+/* prepare tables before sending a cmd */
+void
+siop_setuptables(siop_cmd)
+	struct siop_cmd *siop_cmd;
+{
+	int i;
+	struct siop_softc *sc = siop_cmd->siop_sc;
+	struct scsi_xfer *xs = siop_cmd->xs;
+	int target = xs->sc_link->target;
+	int lun = xs->sc_link->lun;
+
+	siop_cmd->siop_tables.id = htole32(sc->targets[target]->id);
+	memset(siop_cmd->siop_tables.msg_out, 0, 8);
+	if (siop_cmd->status != CMDST_SENSE)
+		siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1);
+	else
+		siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 0);
+	siop_cmd->siop_tables.t_msgout.count= htole32(1);
+	if (sc->targets[target]->status == TARST_ASYNC) {
+		if (sc->targets[target]->flags & TARF_WIDE) {
+			sc->targets[target]->status = TARST_WIDE_NEG;
+			siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT);
+		} else if (sc->targets[target]->flags & TARF_SYNC) {
+			sc->targets[target]->status = TARST_SYNC_NEG;
+			siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff);
+		} else {
+			sc->targets[target]->status = TARST_OK;
+		}
+	} else if (sc->targets[target]->status == TARST_OK &&
+	    (sc->targets[target]->flags & TARF_TAG) &&
+	    siop_cmd->status != CMDST_SENSE) {
+		siop_cmd->flags |= CMDFL_TAG;
+	}
+	siop_cmd->siop_tables.status =
+	    htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */
+
+	siop_cmd->siop_tables.cmd.count =
+	    htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len);
+	siop_cmd->siop_tables.cmd.addr =
+	    htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr);
+	if ((xs->flags & (SCSI_DATA_IN | SCSI_DATA_OUT)) ||
+	    siop_cmd->status == CMDST_SENSE) {
+		for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) {
+			siop_cmd->siop_tables.data[i].count =
+			    htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len);
+			siop_cmd->siop_tables.data[i].addr =
+			    htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr);
+		}
+	}
+	siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+}
+
+int
+siop_wdtr_neg(siop_cmd)
+	struct siop_cmd *siop_cmd;
+{
+	struct siop_softc *sc = siop_cmd->siop_sc;
+	struct siop_target *siop_target = siop_cmd->siop_target;
+	int target = siop_cmd->xs->sc_link->target;
+	struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables;
+
+	if (siop_target->status == TARST_WIDE_NEG) {
+		/* we initiated wide negotiation */
+		switch (tables->msg_in[3]) {
+		case MSG_EXT_WDTR_BUS_8_BIT:
+			printf("%s: target %d using 8bit transfers\n",
+			    sc->sc_dev.dv_xname, target);
+			siop_target->flags &= ~TARF_ISWIDE;
+			sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
+			break;
+		case MSG_EXT_WDTR_BUS_16_BIT:
+			if (siop_target->flags & TARF_WIDE) {
+				printf("%s: target %d using 16bit transfers\n",
+				    sc->sc_dev.dv_xname, target);
+				siop_target->flags |= TARF_ISWIDE;
+				sc->targets[target]->id |= (SCNTL3_EWS << 24);
+				break;
+			}
+		/* FALLTHROUH */
+		default:
+			/*
+ 			 * hum, we got more than what we can handle, shoudn't
+			 * happen. Reject, and stay async
+			 */
+			siop_target->flags &= ~TARF_ISWIDE;
+			siop_target->status = TARST_OK;
+			printf("%s: rejecting invalid wide negotiation from "
+			    "target %d (%d)\n", sc->sc_dev.dv_xname, target,
+			    tables->msg_in[3]);
+			tables->t_msgout.count= htole32(1);
+			tables->msg_out[0] = MSG_MESSAGE_REJECT;
+			return SIOP_NEG_MSGOUT;
+		}
+		tables->id = htole32(sc->targets[target]->id);
+		bus_space_write_1(sc->sc_rt, sc->sc_rh,
+		    SIOP_SCNTL3,
+		    (sc->targets[target]->id >> 24) & 0xff);
+		/* we now need to do sync */
+		if (siop_target->flags & TARF_SYNC) {
+			siop_target->status = TARST_SYNC_NEG;
+			siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff);
+			return SIOP_NEG_MSGOUT;
+		} else {
+			siop_target->status = TARST_OK;
+			return SIOP_NEG_ACK;
+		}
+	} else {
+		/* target initiated wide negotiation */
+		if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT
+		    && (siop_target->flags & TARF_WIDE)) {
+			printf("%s: target %d using 16bit transfers\n",
+			    sc->sc_dev.dv_xname, target);
+			siop_target->flags |= TARF_ISWIDE;
+			sc->targets[target]->id |= SCNTL3_EWS << 24;
+		} else {
+			printf("%s: target %d using 8bit transfers\n",
+			    sc->sc_dev.dv_xname, target);
+			siop_target->flags &= ~TARF_ISWIDE;
+			sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
+		}
+		tables->id = htole32(sc->targets[target]->id);
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
+		    (sc->targets[target]->id >> 24) & 0xff);
+		/*
+		 * we did reset wide parameters, so fall back to async,
+		 * but don't schedule a sync neg, target should initiate it
+		 */
+		siop_target->status = TARST_OK;
+		siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ?
+		    MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT);
+		return SIOP_NEG_MSGOUT;
+	}
+}
+
+int
+siop_sdtr_neg(siop_cmd)
+	struct siop_cmd *siop_cmd;
+{
+	struct siop_softc *sc = siop_cmd->siop_sc;
+	struct siop_target *siop_target = siop_cmd->siop_target;
+	int target = siop_cmd->xs->sc_link->target;
+	int sync, offset, i;
+	int send_msgout = 0;
+	struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables;
+
+	sync = tables->msg_in[3];
+	offset = tables->msg_in[4];
+
+	if (siop_target->status == TARST_SYNC_NEG) {
+		/* we initiated sync negotiation */
+		siop_target->status = TARST_OK;
+#ifdef DEBUG
+		printf("sdtr: sync %d offset %d\n", sync, offset);
+#endif
+		if (offset > sc->maxoff || sync < sc->minsync ||
+			sync > sc->maxsync)
+			goto reject;
+		for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
+		    i++) {
+			if (sc->clock_period != scf_period[i].clock)
+				continue;
+			if (scf_period[i].period == sync) {
+				/* ok, found it. we now are sync. */
+				printf("%s: target %d now synchronous at "
+				    "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
+				    target, scf_period[i].rate, offset);
+				sc->targets[target]->id &=
+				    ~(SCNTL3_SCF_MASK << 24);
+				sc->targets[target]->id |= scf_period[i].scf
+				    << (24 + SCNTL3_SCF_SHIFT);
+				if (sync < 25) /* Ultra */
+					sc->targets[target]->id |=
+					    SCNTL3_ULTRA << 24;
+				else
+					sc->targets[target]->id &=
+					    ~(SCNTL3_ULTRA << 24);
+				sc->targets[target]->id &=
+				    ~(SXFER_MO_MASK << 8);
+				sc->targets[target]->id |=
+				    (offset & SXFER_MO_MASK) << 8;
+				goto end;
+			}
+		}
+		/*
+		 * we didn't find it in our table, do async and send reject
+		 * msg
+		 */
+reject:
+		send_msgout = 1;
+		tables->t_msgout.count= htole32(1);
+		tables->msg_out[0] = MSG_MESSAGE_REJECT;
+		printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname,
+		    target);
+		sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
+		sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
+		sc->targets[target]->id &= ~(SXFER_MO_MASK << 8);
+	} else { /* target initiated sync neg */
+#ifdef DEBUG
+		printf("sdtr (target): sync %d offset %d\n", sync, offset);
+#endif
+		if (offset == 0 || sync > sc->maxsync) { /* async */
+			goto async;
+		}
+		if (offset > sc->maxoff)
+			offset = sc->maxoff;
+		if (sync < sc->minsync)
+			sync = sc->minsync;
+		/* look for sync period */
+		for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
+		    i++) {
+			if (sc->clock_period != scf_period[i].clock)
+				continue;
+			if (scf_period[i].period == sync) {
+				/* ok, found it. we now are sync. */
+				printf("%s: target %d now synchronous at "
+				    "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
+				    target, scf_period[i].rate, offset);
+				sc->targets[target]->id &=
+				    ~(SCNTL3_SCF_MASK << 24);
+				sc->targets[target]->id |= scf_period[i].scf
+				    << (24 + SCNTL3_SCF_SHIFT);
+				if (sync < 25) /* Ultra */
+					sc->targets[target]->id |=
+					    SCNTL3_ULTRA << 24;
+				else
+					sc->targets[target]->id &=
+					    ~(SCNTL3_ULTRA << 24);
+				sc->targets[target]->id &=
+				    ~(SXFER_MO_MASK << 8);
+				sc->targets[target]->id |=
+				    (offset & SXFER_MO_MASK) << 8;
+				siop_sdtr_msg(siop_cmd, 0, sync, offset);
+				send_msgout = 1;
+				goto end;
+			}
+		}
+async:
+		printf("%s: target %d asynchronous\n",
+		    sc->sc_dev.dv_xname, target);
+		sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
+		sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
+		sc->targets[target]->id &= ~(SXFER_MO_MASK << 8);
+		siop_sdtr_msg(siop_cmd, 0, 0, 0);
+		send_msgout = 1;
+	}
+end:
+#ifdef DEBUG
+	printf("id now 0x%x\n", sc->targets[target]->id);
+#endif
+	tables->id = htole32(sc->targets[target]->id);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
+	    (sc->targets[target]->id >> 24) & 0xff);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER,
+	    (sc->targets[target]->id >> 8) & 0xff);
+	if (send_msgout) {
+		return SIOP_NEG_MSGOUT;
+	} else {
+		return SIOP_NEG_ACK;
+	}
+}
+
+void
+siop_sdtr_msg(siop_cmd, offset, ssync, soff)
+	struct siop_cmd *siop_cmd;
+	int offset;
+	int ssync, soff;
+{
+	siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED;
+	siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN;
+	siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR;
+	siop_cmd->siop_tables.msg_out[offset + 3] = ssync;
+	siop_cmd->siop_tables.msg_out[offset + 4] = soff;
+	siop_cmd->siop_tables.t_msgout.count =
+	    htole32(offset + MSG_EXT_SDTR_LEN + 2);
+}
+
+void
+siop_wdtr_msg(siop_cmd, offset, wide)
+	struct siop_cmd *siop_cmd;
+	int offset;
+{
+	siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED;
+	siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN;
+	siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR;
+	siop_cmd->siop_tables.msg_out[offset + 3] = wide;
+	siop_cmd->siop_tables.t_msgout.count =
+	    htole32(offset + MSG_EXT_WDTR_LEN + 2);
+}
+
+void
+siop_minphys(bp)
+	struct buf *bp;
+{
+	minphys(bp);
+}
+
+void
+siop_sdp(siop_cmd)
+	struct siop_cmd *siop_cmd;
+{
+	/* save data pointer. Handle async only for now */
+	int offset, dbc, sstat;
+	struct siop_softc *sc = siop_cmd->siop_sc;
+	scr_table_t *table; /* table to patch */
+
+	if ((siop_cmd->xs->flags & (SCSI_DATA_OUT | SCSI_DATA_IN))
+	    == 0)
+	    return; /* no data pointers to save */
+	offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1);
+	if (offset >= SIOP_NSG) {
+		printf("%s: bad offset in siop_sdp (%d)\n",
+		    sc->sc_dev.dv_xname, offset);
+		return;
+	}
+	table = &siop_cmd->siop_xfer->tables.data[offset];
+#ifdef DEBUG_DR
+	printf("sdp: offset %d count=%d addr=0x%x ", offset,
+	    table->count, table->addr);
+#endif
+	dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff;
+	if (siop_cmd->xs->flags & SCSI_DATA_OUT) {
+		/* need to account stale data in FIFO */
+		int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO);
+		if (sc->features & SF_CHIP_FIFO) {
+			dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_CTEST5) & CTEST5_BOMASK) << 8;
+			dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff;
+		} else {
+			dbc += (dfifo - (dbc & 0x7f)) & 0x7f;
+		}
+		sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0);
+		if (sstat & SSTAT0_OLF)
+			dbc++;
+		if (sstat & SSTAT0_ORF)
+			dbc++;
+		if (siop_cmd->siop_target->flags & TARF_ISWIDE) {
+			sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_SSTAT2);
+			if (sstat & SSTAT2_OLF1)
+				dbc++;
+			if (sstat & SSTAT2_ORF1)
+				dbc++;
+		}
+		/* clear the FIFO */
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
+		    CTEST3_CLF);
+	}
+	table->addr =
+	    htole32(letoh32(table->addr) + letoh32(table->count) - dbc);
+	table->count = htole32(dbc);
+#ifdef DEBUG_DR
+	printf("now count=%d addr=0x%x\n", table->count, table->addr);
+#endif
+}
+
+void
+siop_clearfifo(sc)
+	struct siop_softc *sc;
+{
+	int timeout = 0;
+	int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3);
+
+#ifdef DEBUG_INTR
+	printf("DMA fifo not empty !\n");
+#endif
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
+	    ctest3 | CTEST3_CLF);
+	while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) &
+	    CTEST3_CLF) != 0) {
+		delay(1);
+		if (++timeout > 1000) {
+			printf("clear fifo failed\n");
+			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
+			    bus_space_read_1(sc->sc_rt, sc->sc_rh,
+			    SIOP_CTEST3) & ~CTEST3_CLF);
+			return;
+		}
+	}
+}
+
+int
+siop_modechange(sc)
+	struct siop_softc *sc;
+{
+	int retry;
+	int sist0, sist1, stest2, stest4;
+	for (retry = 0; retry < 5; retry++) {
+		/*
+		 * datasheet says to wait 100ms and re-read SIST1,
+		 * to check that DIFFSENSE is srable.
+		 * We may delay() 5 times for  100ms at interrupt time;
+		 * hopefully this will not happen often.
+		 */
+		delay(100000);
+		sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0);
+		sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1);
+		if (sist1 & SIEN1_SBMC)
+			continue; /* we got an irq again */
+		stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) &
+		    STEST4_MODE_MASK;
+		stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2);
+		switch(stest4) {
+		case STEST4_MODE_DIF:
+			printf("%s: switching to differential mode\n",
+			    sc->sc_dev.dv_xname);
+			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
+			    stest2 | STEST2_DIF);
+			break;
+		case STEST4_MODE_SE:
+			printf("%s: switching to single-ended mode\n",
+			    sc->sc_dev.dv_xname);
+			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
+			    stest2 & ~STEST2_DIF);
+			break;
+		case STEST4_MODE_LVD:
+			printf("%s: switching to LVD mode\n",
+			    sc->sc_dev.dv_xname);
+			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
+			    stest2 & ~STEST2_DIF);
+			break;
+		default:
+			printf("%s: invalid SCSI mode 0x%x\n",
+			    sc->sc_dev.dv_xname, stest4);
+			return 0;
+		}
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0,
+		    stest4 >> 2);
+		return 1;
+	}
+	printf("%s: timeout waiting for DIFFSENSE to stabilise\n",
+	    sc->sc_dev.dv_xname);
+	return 0;
+}
+
+void
+siop_resetbus(sc)
+	struct siop_softc *sc;
+{
+	int scntl1;
+	scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1,
+	    scntl1 | SCNTL1_RST);
+	/* minimum 25 us, more time won't hurt */
+	delay(100);
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1);
+}
diff --git a/sys/dev/ic/siopreg.h b/sys/dev/ic/siopreg.h
new file mode 100644
index 00000000000..739afca27f5
--- /dev/null
+++ b/sys/dev/ic/siopreg.h
@@ -0,0 +1,377 @@
+/*	$OpenBSD: siopreg.h,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$NetBSD: siopreg.h,v 1.7 2000/10/06 16:35:13 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Devices definitions for Symbios/NCR M53c8xx PCI-SCSI I/O Processors
+ * Docs available from http://www.symbios.com/
+ */
+
+#define SIOP_SCNTL0 	0x00 /* SCSI control 0, R/W */
+#define SCNTL0_ARB_MASK	0xc0
+#define SCNTL0_SARB	0x00
+#define SCNTL0_FARB	0xc0
+#define SCNTL0_START	0x20
+#define SCNTL0_WATM	0x10
+#define SCNTL0_EPC	0x08
+#define SCNTL0_AAP	0x02
+#define SCNTL0_TRG	0x01
+
+#define SIOP_SCNTL1 	0x01 /* SCSI control 1, R/W */
+#define SCNTL1_EXC	0x80
+#define SCNTL1_ADB	0x40
+#define SCNTL1_DHP	0x20
+#define SCNTL1_CON	0x10
+#define SCNTL1_RST	0x08
+#define SCNTL1_AESP	0x04
+#define SCNTL1_IARB	0x02
+#define SCNTL1_SST	0x01
+
+#define SIOP_SCNTL2 	0x02 /* SCSI control 2, R/W */
+#define SCNTL2_SDU	0x80
+#define SCNTL2_CHM	0x40	/* 875 only */
+#define SCNTL2_SLPMD	0x20	/* 875 only */
+#define SCNTL2_SLPHBEN	0x10	/* 875 only */
+#define SCNTL2_WSS	0x08	/* 875 only */
+#define SCNTL2_VUE0	0x04	/* 875 only */
+#define SCNTL2_VUE1	0x02	/* 875 only */
+#define SCNTL2_WSR	0x01	/* 875 only */
+
+#define SIOP_SCNTL3 	0x03 /* SCSI control 3, R/W */
+#define SCNTL3_ULTRA	0x80	/* 875 only */
+#define SCNTL3_SCF_SHIFT 4
+#define SCNTL3_SCF_MASK	0x70
+#define SCNTL3_EWS	0x08	/* 875 only */
+#define SCNTL3_CCF_SHIFT 0
+#define SCNTL3_CCF_MASK	0x07
+
+/* periods for various SCF values, assume transfer period of 4 */
+struct scf_period {
+	int clock; /* clock period (ns * 10) */
+	int period; /* scsi period, as set in the SDTR message */
+	int scf; /* scf value to use */
+	char *rate; /* the resulting rate */
+};
+
+static const struct scf_period scf_period[] __attribute__((__unused__)) = {
+	{250, 25, 1, "10.0"},
+	{250, 37, 2, "6.67"},
+	{250, 50, 3, "5.0"},
+	{250, 75, 4, "3.33"},
+	{125, 12, 1, "20.0"},
+	{125, 18, 2, "13.33"},
+	{125, 25, 3, "10.0"},
+	{125, 37, 4, "6.67"},
+	{125, 50, 5, "5.0"},
+	{ 62, 10, 1, "40.0"},
+	{ 62, 12, 3, "20.0"},
+	{ 62, 18, 4, "13.3"},
+	{ 62, 25, 5, "10.0"},
+};
+
+#define SIOP_SCID	0x04 /* SCSI chip ID R/W */
+#define SCID_RRE	0x40
+#define SCID_SRE	0x20
+#define SCID_ENCID_SHIFT 0
+#define SCID_ENCID_MASK	0x07
+
+#define SIOP_SXFER	0x05 /* SCSI transfer, R/W */
+#define SXFER_TP_SHIFT	 5
+#define SXFER_TP_MASK	0xe0
+#define SXFER_MO_SHIFT  0
+#define SXFER_MO_MASK  0x1f
+
+#define SIOP_SDID	0x06 /* SCSI destiation ID, R/W */
+#define SDID_ENCID_SHIFT 0
+#define SDID_ENCID_MASK	0x07
+
+#define SIOP_GPREG	0x07 /* General purpose, R/W */
+#define GPREG_GPIO4	0x10	/* 875 only */
+#define GPREG_GPIO3	0x08	/* 875 only */
+#define GPREG_GPIO2	0x04	/* 875 only */
+#define GPREG_GPIO1	0x02
+#define GPREG_GPIO0	0x01
+
+#define SIOP_SFBR	0x08 /* SCSI first byte received, R/W */
+
+#define SIOP_SOCL	0x09 /* SCSI output control latch, RW */
+
+#define SIOP_SSID	0x0A /* SCSI selector ID, RO */
+#define SSID_VAL	0x80
+#define SSID_ENCID_SHIFT 0
+#define SSID_ENCID_MASK 0x0f
+
+#define SIOP_SBCL	0x0B /* SCSI control line, RO */
+
+#define SIOP_DSTAT	0x0C /* DMA status, RO */
+#define DSTAT_DFE	0x80
+#define DSTAT_MDPE	0x40
+#define DSTAT_BF	0x20
+#define DSTAT_ABRT	0x10
+#define DSTAT_SSI	0x08
+#define DSTAT_SIR	0x04
+#define DSTAT_IID	0x01
+
+#define SIOP_SSTAT0	0x0D /* STSI status 0, RO */
+#define SSTAT0_ILF	0x80
+#define SSTAT0_ORF	0x40
+#define SSTAT0_OLF	0x20
+#define SSTAT0_AIP	0x10
+#define SSTAT0_LOA	0x08
+#define SSTAT0_WOA	0x04
+#define SSTAT0_RST	0x02
+#define SSTAT0_SDP	0x01
+
+#define SIOP_SSTAT1	0x0E /* STSI status 1, RO */
+#define SSTAT1_FFO_SHIFT 4
+#define SSTAT1_FFO_MASK 0x80
+#define SSTAT1_SDPL	0x08
+#define SSTAT1_MSG	0x04
+#define SSTAT1_CD	0x02
+#define SSTAT1_IO	0x01
+#define SSTAT1_PHASE_MASK (SSTAT1_IO | SSTAT1_CD | SSTAT1_MSG)
+#define SSTAT1_PHASE_DATAOUT	0
+#define SSTAT1_PHASE_DATAIN	SSTAT1_IO
+#define SSTAT1_PHASE_CMD	SSTAT1_CD
+#define SSTAT1_PHASE_STATUS	(SSTAT1_CD | SSTAT1_IO)
+#define SSTAT1_PHASE_MSGOUT	(SSTAT1_MSG | SSTAT1_CD)
+#define SSTAT1_PHASE_MSGIN	(SSTAT1_MSG | SSTAT1_CD | SSTAT1_IO)
+
+#define SIOP_SSTAT2	0x0F /* STSI status 2, RO */
+#define SSTAT2_ILF1	0x80	/* 875 only */
+#define SSTAT2_ORF1	0x40	/* 875 only */
+#define SSTAT2_OLF1	0x20	/* 875 only */
+#define SSTAT2_FF4	0x10	/* 875 only */
+#define SSTAT2_SPL1	0x08	/* 875 only */
+#define SSTAT2_DF	0x04	/* 875 only */
+#define SSTAT2_LDSC	0x02
+#define SSTAT2_SDP1	0x01	/* 875 only */
+
+#define SIOP_DSA	0x10 /* data struct addr, R/W */
+
+#define SIOP_ISTAT	0x14 /* IRQ status, R/W */
+#define ISTAT_ABRT	0x80
+#define ISTAT_SRST	0x40
+#define ISTAT_SIGP	0x20
+#define ISTAT_SEM	0x10
+#define ISTAT_CON	0x08
+#define ISTAT_INTF	0x04
+#define ISTAT_SIP	0x02
+#define ISTAT_DIP	0x01
+
+#define SIOP_CTEST0	0x18 /* Chip test 0, R/W */
+
+#define SIOP_CTEST1	0x19 /* Chip test 1, R/W */
+
+#define SIOP_CTEST2	0x1A /* Chip test 2, R/W */
+#define CTEST2_SRTCH	0x04	/* 875 only */
+
+#define SIOP_CTEST3	0x1B /* Chip test 3, R/W */
+#define CTEST3_FLF	0x08
+#define CTEST3_CLF	0x04
+#define CTEST3_FM	0x02
+#define CTEST3_WRIE	0x01
+
+#define SIOP_TEMP	0x1C /* Temp register (used by CALL/RET), R/W */
+
+#define SIOP_DFIFO	0x20 /* DMA FIFO */
+
+#define SIOP_CTEST4	0x21 /* Chip test 4, R/W */
+#define CTEST4_BDIS	0x80
+#define CTEST_ZMOD	0x40
+#define CTEST_ZSD	0x20
+#define CTEST_SRTM	0x10
+#define CTEST_MPEE	0x08
+
+#define SIOP_CTEST5	0x22 /* Chip test 5, R/W */
+#define CTEST5_ADCK	0x80
+#define CTEST5_BBCK	0x40
+#define CTEST5_DFS	0x20
+#define CTEST5_MASR	0x10
+#define CTEST5_DDIR	0x08
+#define CTEST5_BOMASK	0x03
+
+#define SIOP_CTEST6	0x23 /* Chip test 6, R/W */
+
+#define SIOP_DBC	0x24 /* DMA byte counter, R/W */
+
+#define SIOP_DCMD	0x27 /* DMA command, R/W */
+
+#define SIOP_DNAD	0x28 /* DMA next addr, R/W */
+
+#define SIOP_DSP	0x2C /* DMA scripts pointer, R/W */
+
+#define SIOP_DSPS	0x30 /* DMA scripts pointer save, R/W */
+
+#define SIOP_SCRATCHA	0x34 /* scratch register A. R/W */
+
+#define SIOP_DMODE	0x38 /* DMA mode, R/W */
+#define DMODE_BL_SHIFT   6
+#define DMODE_BL_MASK	0xC0
+#define DMODE_SIOM	0x20
+#define DMODE_DIOM	0x10
+#define DMODE_ERL	0x08
+#define DMODE_ERMP	0x04
+#define DMODE_BOF	0x02
+#define DMODE_MAN	0x01
+
+#define SIOP_DIEN	0x39 /* DMA interrupt enable, R/W */
+#define DIEN_MDPE	0x40
+#define DIEN_BF		0x20
+#define DIEN_AVRT	0x10
+#define DIEN_SSI	0x08
+#define DIEN_SIR	0x04
+#define DIEN_IID	0x01
+
+#define SIOP_SBR	0x3A /* scratch byte register, R/W */
+
+#define SIOP_DCNTL	0x3B /* DMA control, R/W */
+#define DCNTL_CLSE	0x80
+#define DCNTL_PFF	0x40
+#define DCNTL_PFEN	0x20
+#define DCNTL_SSM	0x10
+#define DCNTL_IRQM	0x08
+#define DCNTL_STD	0x04
+#define DCNTL_IRQD	0x02
+#define DCNTL_COM	0x01
+
+#define SIOP_ADDER	0x3C /* adder output sum, RO */
+
+#define SIOP_SIEN0	0x40 /* SCSI interrupt enable 0, R/W */
+#define SIEN0_MA	0x80
+#define SIEN0_CMP	0x40
+#define SIEN0_SEL	0x20
+#define SIEN0_RSL	0x10
+#define SIEN0_SGE	0x08
+#define SIEN0_UDC	0x04
+#define SIEN0_SRT	0x02
+#define SIEN0_PAR	0x01
+
+#define SIOP_SIEN1	0x41 /* SCSI interrupt enable 1, R/W */
+#define SIEN1_SBMC	0x10 /* 895 only */
+#define SIEN1_STO	0x04
+#define SIEN1_GEN	0x02
+#define SIEN1_HTH	0x01
+
+#define SIOP_SIST0	0x42 /* SCSI interrupt status 0, RO */
+#define SIST0_MA	0x80
+#define SIST0_CMP	0x40
+#define SIST0_SEL	0x20
+#define SIST0_RSL	0x10
+#define SIST0_SGE	0x08
+#define SIST0_UDC	0x04
+#define SIST0_RST	0x02
+#define SIST0_PAR	0x01
+
+#define SIOP_SIST1	0x43 /* SCSI interrut status 1, RO */
+#define SIST1_SBMC	0x10 /* 895 only */
+#define SIST1_STO	0x04
+#define SIST1_GEN	0x02
+#define SIST1_HTH	0x01
+
+#define SIOP_SLPAR	0x44 /* scsi longitudinal parity, R/W */
+
+#define SIOP_SWIDE	0x45 /* scsi wide residue, RW, 875 only */
+
+#define SIOP_MACNTL	0x46 /* memory access control, R/W */
+
+#define SIOP_GPCNTL	0x47 /* General Purpose Pin control, R/W */
+#define GPCNTL_ME	0x80	/* 875 only */
+#define GPCNTL_FE	0x40	/* 875 only */
+#define GPCNTL_IN4	0x10	/* 875 only */
+#define GPCNTL_IN3	0x08	/* 875 only */
+#define GPCNTL_IN2	0x04	/* 875 only */
+#define GPCNTL_IN1	0x02
+#define GPCNTL_IN0	0x01
+
+#define SIOP_STIME0	0x48 /* SCSI timer 0, R/W */
+#define STIME0_HTH_SHIFT 4
+#define STIME0_HTH_MASK	0xf0
+#define STIME0_SEL_SHIFT 0
+#define STIME0_SEL_MASK	0x0f
+
+#define SIOP_STIME1	0x49 /* SCSI timer 1, R/W */
+#define STIME1_HTHBA	0x40	/* 875 only */
+#define STIME1_GENSF	0x20	/* 875 only */
+#define STIME1_HTHSF	0x10	/* 875 only */
+#define STIME1_GEN_SHIFT 0
+#define STIME1_GEN_MASK	0x0f
+
+#define SIOP_RESPID0	0x4A /* response ID, R/W */
+
+#define SIOP_RESPID1	0x4B /* response ID, R/W, 875-only */
+
+#define SIOP_STEST0	0x4C /* SCSI test 0, RO */
+
+#define SIOP_STEST1	0x4D /* SCSI test 1, RO, RW on 875 */
+#define STEST1_DBLEN	0x08	/* 875-only */
+#define STEST1_DBLSEL	0x04	/* 875-only */
+
+#define SIOP_STEST2	0x4E /* SCSI test 2, RO, R/W on 875 */
+#define STEST2_DIF	0x20	/* 875 only */
+#define STEST2_EXT	0x02
+
+#define SIOP_STEST3	0x4F /* SCSI test 3, RO, RW on 875 */
+#define STEST3_TE	0x80
+#define STEST3_HSC	0x20
+
+#define SIOP_STEST4	0x52 /* SCSI test 4, 895 only */
+#define STEST4_MODE_MASK 0xc0
+#define STEST4_MODE_DIF	0x40
+#define STEST4_MODE_SE	0x80
+#define STEST4_MODE_LVD	0xc0
+#define STEST4_LOCK	0x20
+#define STEST4_
+
+#define SIOP_SIDL	0x50 /* SCSI input data latch, RO */
+
+#define SIOP_SODL	0x54 /* SCSI output data latch, R/W */
+
+#define SIOP_SBDL	0x58 /* SCSI bus data lines, RO */
+
+#define SIOP_SCRATCHB	0x5C /* Scratch register B, R/W */
+
+#define SIOP_SCRATCHC	0x60 /* Scratch register C, R/W, 875 only */
+
+#define SIOP_SCRATCHD	0x64 /* Scratch register D, R/W, 875-only */
+
+#define SIOP_SCRATCHE	0x68 /* Scratch register E, R/W, 875-only */
+
+#define SIOP_SCRATCHF	0x6c /* Scratch register F, R/W, 875-only */
+
+#define SIOP_SCRATCHG	0x70 /* Scratch register G, R/W, 875-only */
+
+#define SIOP_SCRATCHH	0x74 /* Scratch register H, R/W, 875-only */
+
+#define SIOP_SCRATCHI	0x78 /* Scratch register I, R/W, 875-only */
+
+#define SIOP_SCRATCHJ	0x7c /* Scratch register J, R/W, 875-only */
diff --git a/sys/dev/ic/siopvar.h b/sys/dev/ic/siopvar.h
new file mode 100644
index 00000000000..c4b99252067
--- /dev/null
+++ b/sys/dev/ic/siopvar.h
@@ -0,0 +1,99 @@
+/*	$OpenBSD: siopvar.h,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$NetBSD: siopvar.h,v 1.13 2000/10/23 23:18:11 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* structure and definitions for the siop driver */
+
+TAILQ_HEAD(cmd_list, siop_cmd);
+TAILQ_HEAD(cbd_list, siop_cbd);
+TAILQ_HEAD(lunsw_list, siop_lunsw);
+
+/* Driver internal state */
+struct siop_softc {
+	struct device sc_dev;
+	struct scsi_link sc_link;	/* link to upper level */
+	int features;			/* chip's features */
+	int ram_size;
+	int maxburst;
+	int maxoff;
+	int clock_div;			/* async. clock divider (scntl3) */
+	int clock_period;		/* clock period (ns * 10) */
+	int minsync;			/* min and max sync period, */
+	int maxsync;			/* as sent in SDTR message */
+	bus_space_tag_t sc_rt;		/* bus_space registers tag */
+	bus_space_handle_t sc_rh;	/* bus_space registers handle */
+	bus_addr_t sc_raddr;		/* register adresses */
+	bus_space_tag_t sc_ramt;	/* bus_space ram tag */
+	bus_space_handle_t sc_ramh;	/* bus_space ram handle */
+	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
+	void (*sc_reset) __P((struct siop_softc*)); /* reset callback */
+	bus_dmamap_t  sc_scriptdma;	/* DMA map for script */
+	bus_addr_t sc_scriptaddr;	/* on-board ram or physical adress */
+	u_int32_t *sc_script;		/* script location in memory */
+	int sc_currschedslot;		/* current scheduler slot */
+	struct cbd_list cmds;		/* list of command block descriptors */
+	struct cmd_list free_list;	/* cmd descr free list */
+	struct cmd_list urgent_list;	/* hitgh priority cmd descr list */
+	struct cmd_list ready_list;	/* cmd descr ready list */
+	struct lunsw_list lunsw_list;	/* lunsw free list */
+	u_int32_t script_free_lo;	/* free ram offset from sc_scriptaddr */
+	u_int32_t script_free_hi;	/* free ram offset from sc_scriptaddr */
+	struct siop_target *targets[16]; /* per-target states */
+	int sc_ntargets;		/* number of known targets */
+	u_int32_t sc_flags;
+};
+/* defs for sc_flags */
+/* none for now */
+
+/* features */
+#define SF_BUS_WIDE	0x00000001 /* wide bus */
+#define SF_BUS_ULTRA	0x00000002 /* Ultra (20Mhz) bus */
+#define SF_BUS_ULTRA2	0x00000004 /* Ultra2 (40Mhz) bus */
+#define SF_BUS_DIFF	0x00000008 /* differential bus */
+
+#define SF_CHIP_LED0	0x00000100 /* led on GPIO0 */
+#define SF_CHIP_DBLR	0x00000200 /* clock doubler */
+#define SF_CHIP_QUAD	0x00000400 /* clock quadrupler */
+#define SF_CHIP_FIFO	0x00000800 /* large fifo */
+#define SF_CHIP_PF	0x00001000 /* Intructions prefetch */
+#define SF_CHIP_RAM	0x00002000 /* on-board RAM */
+#define SF_CHIP_LS	0x00004000 /* load/store instruction */
+#define SF_CHIP_10REGS	0x00008000 /* 10 scratch registers */
+
+#define SF_PCI_RL	0x01000000 /* PCI read line */
+#define SF_PCI_RM	0x02000000 /* PCI read multiple */
+#define SF_PCI_BOF	0x04000000 /* PCI burst opcode fetch */
+#define SF_PCI_CLS	0x08000000 /* PCI cache line size */
+#define SF_PCI_WRI	0x10000000 /* PCI write and invalidate */
+
+void    siop_attach __P((struct siop_softc *));
+int	siop_intr __P((void *));
diff --git a/sys/dev/ic/siopvar_common.h b/sys/dev/ic/siopvar_common.h
new file mode 100644
index 00000000000..d4d30c3d0a1
--- /dev/null
+++ b/sys/dev/ic/siopvar_common.h
@@ -0,0 +1,200 @@
+/*	$OpenBSD: siopvar_common.h,v 1.1 2001/02/15 04:07:59 krw Exp $ */
+/*	$NetBSD: siopvar_common.h,v 1.10 2001/01/26 21:58:56 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/* common struct and routines used by siop and esiop */
+
+#ifndef SIOP_DEFAULT_TARGET
+#define SIOP_DEFAULT_TARGET 7
+#endif
+
+/* tables used by SCRIPT */
+typedef struct scr_table {
+	u_int32_t count;
+	u_int32_t addr;
+} scr_table_t ;
+
+/* Number of scatter/gather entries */
+#define SIOP_NSG	(MAXPHYS/NBPG + 1)	/* XXX NBPG */
+
+/* Number of tag */
+#define SIOP_NTAG 16
+
+/*
+ * This structure interfaces the SCRIPT with the driver; it describes a full
+ * transfer. 
+ */
+struct siop_xfer_common {
+	u_int8_t msg_out[8];	/* 0 */
+	u_int8_t msg_in[8];	/* 8 */
+	u_int32_t status;	/* 16 */
+	u_int32_t pad1;		/* 20 */
+	u_int32_t id;		/* 24 */
+	u_int32_t pad2;		/* 28 */
+	scr_table_t t_msgin;	/* 32 */
+	scr_table_t t_extmsgin;	/* 40 */
+	scr_table_t t_extmsgdata; /* 48 */
+	scr_table_t t_msgout;	/* 56 */
+	scr_table_t cmd;	/* 64 */
+	scr_table_t t_status;	/* 72 */
+	scr_table_t data[SIOP_NSG]; /* 80 */
+} __attribute__((__packed__));
+
+/* status can hold the SCSI_* status values, and 2 additionnal values: */
+#define SCSI_SIOP_NOCHECK	0xfe	/* don't check the scsi status */
+#define SCSI_SIOP_NOSTATUS	0xff	/* device didn't report status */
+
+/* xfer description of the script: tables and reselect script */
+struct siop_xfer {
+	struct siop_xfer_common tables;
+	/* u_int32_t resel[sizeof(load_dsa) / sizeof(load_dsa[0])]; */
+	u_int32_t resel[25];
+} __attribute__((__packed__));
+
+/*
+ * This decribes a command handled by the SCSI controller
+ * These are chained in either a free list or a active list
+ * We have one queue per target
+ */
+struct siop_cmd {
+	TAILQ_ENTRY (siop_cmd) next;
+	struct siop_softc *siop_sc; /* points back to our adapter */
+	struct siop_target *siop_target; /* pointer to our target def */
+	struct scsi_xfer *xs; /* xfer from the upper level */
+	struct siop_xfer *siop_xfer; /* tables dealing with this xfer */
+#define siop_tables siop_xfer->tables
+	struct siop_cbd *siop_cbdp; /* pointer to our siop_cbd */
+	bus_addr_t	dsa; /* DSA value to load */
+	bus_dmamap_t	dmamap_cmd;
+	bus_dmamap_t	dmamap_data;
+	struct scsi_sense rs_cmd; /* request sense command buffer */
+	int status;
+	int flags;
+	int reselslot; /* the reselect slot used */
+	int tag;	/* tag used for tagged command queuing */
+};
+
+/* command block descriptors: an array of siop_cmd + an array of siop_xfer */
+
+struct siop_cbd {
+	TAILQ_ENTRY (siop_cbd) next;
+	struct siop_cmd *cmds;
+	struct siop_xfer *xfers;
+	bus_dmamap_t xferdma; /* DMA map for this block of xfers */
+};
+
+/* status defs */
+#define CMDST_FREE		0 /* cmd slot is free */
+#define CMDST_READY		1 /* cmd slot is waiting for processing */
+#define CMDST_ACTIVE		2 /* cmd slot is being processed */
+#define CMDST_SENSE		3 /* cmd slot is being requesting sense */
+#define CMDST_SENSE_ACTIVE	4 /* request sense active */
+#define CMDST_SENSE_DONE 	5 /* request sense done */
+#define CMDST_DONE		6 /* cmd slot has been processed */
+/* flags defs */
+#define CMDFL_TIMEOUT	0x0001 /* cmd timed out */
+#define CMDFL_TAG	0x0002 /* tagged cmd */
+
+/* per-tag struct */
+struct siop_tag {
+	struct siop_cmd *active; /* active command */
+	u_int reseloff; /* XXX */
+};
+
+/* per lun struct */
+struct siop_lun {
+	struct siop_tag siop_tag[SIOP_NTAG]; /* tag array */
+	int lun_flags; /* per-lun flags, see below */
+	u_int reseloff; /* XXX */
+};
+
+#define SIOP_LUNF_FULL 0x01 /* queue full message */
+
+/* per-target struct */
+struct siop_target {
+	int status;	/* target status, see below */
+	int flags;	/* target flags, see below */
+	u_int32_t id;	/* for SELECT FROM */
+	struct siop_lun *siop_lun[8]; /* per-lun state */
+	u_int reseloff; /* XXX */
+	struct siop_lunsw *lunsw; /* XXX */
+};
+
+/* target status */
+#define TARST_PROBING	0 /* target is being probed */
+#define TARST_ASYNC	1 /* target needs sync/wide negotiation */
+#define TARST_WIDE_NEG	2 /* target is doing wide negotiation */
+#define TARST_SYNC_NEG	3 /* target is doing sync negotiation */
+#define TARST_OK	4 /* sync/wide agreement is valid */
+
+/* target flags */
+#define TARF_SYNC	0x01 /* target can do sync */
+#define TARF_WIDE	0x02 /* target can do wide */
+#define TARF_TAG	0x04 /* target can do tags */
+#define TARF_ISWIDE	0x08 /* target is wide */
+
+struct siop_lunsw {
+	TAILQ_ENTRY (siop_lunsw) next;
+	u_int32_t lunsw_off; /* offset of this lun sw, from sc_scriptaddr*/
+	u_int32_t lunsw_size; /* size of this lun sw */
+};
+
+static __inline__ void siop_table_sync __P((struct siop_cmd *, int));
+static __inline__ void
+siop_table_sync(siop_cmd, ops)
+	struct siop_cmd *siop_cmd;
+	int ops;
+{
+	struct siop_softc *sc  = siop_cmd->siop_sc;
+	bus_dmamap_sync(sc->sc_dmat, siop_cmd->siop_cbdp->xferdma, ops);
+}
+
+void	siop_common_reset __P((struct siop_softc *));
+void	siop_setuptables __P((struct siop_cmd *));
+int	siop_modechange __P((struct siop_softc *));
+
+int	siop_wdtr_neg __P((struct siop_cmd *));
+int	siop_sdtr_neg __P((struct siop_cmd *));
+void	siop_sdtr_msg __P((struct siop_cmd *, int, int, int));
+void	siop_wdtr_msg __P((struct siop_cmd *, int, int));
+/* actions to take at return of siop_wdtr_neg() and siop_sdtr_neg() */
+#define SIOP_NEG_NOP	0x0
+#define SIOP_NEG_MSGOUT	0x1
+#define SIOP_NEG_ACK	0x2
+
+void	siop_minphys __P((struct buf *));
+void 	siop_sdp __P((struct siop_cmd *));
+void	siop_clearfifo __P((struct siop_softc *));
+void	siop_resetbus __P((struct siop_softc *));
+/* XXXX should be  callbacks */
+void	siop_add_dev __P((struct siop_softc *, int, int));
+void	siop_del_dev __P((struct siop_softc *, int, int));
diff --git a/sys/dev/microcode/siop/Makefile b/sys/dev/microcode/siop/Makefile
new file mode 100644
index 00000000000..39dfe3d8df8
--- /dev/null
+++ b/sys/dev/microcode/siop/Makefile
@@ -0,0 +1,17 @@
+# $OpenBSD: Makefile,v 1.1 2001/02/15 04:07:59 krw Exp $
+# $NetBSD: Makefile,v 1.1 2000/04/21 17:57:01 bouyer Exp $
+
+all: siop.out
+
+PROG=	ncr53cxxx
+MKSHARE=no
+MAN=
+
+.include <bsd.prog.mk>
+
+regen: siop.out
+headers: siop.out
+
+siop.out: siop.ss ${PROG}
+	./${PROG} siop.ss -o siop.out
+
diff --git a/sys/dev/microcode/siop/ncr53cxxx.c b/sys/dev/microcode/siop/ncr53cxxx.c
new file mode 100644
index 00000000000..b736a00cd44
--- /dev/null
+++ b/sys/dev/microcode/siop/ncr53cxxx.c
@@ -0,0 +1,1395 @@
+/*	$OpenBSD: ncr53cxxx.c,v 1.1 2001/02/15 04:07:59 krw Exp $ */
+/*	$NetBSD: ncr53cxxx.c,v 1.5 2000/10/23 14:51:51 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 1995,1999 Michael L. Hitch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Michael L. Hitch.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*	ncr53cxxx.c	- SCSI SCRIPTS Assembler		*/
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+#ifndef AMIGA
+#define strcmpi	strcasecmp
+#endif
+
+#define	MAXTOKENS	16
+#define	MAXINST		1024
+#define	MAXSYMBOLS	128
+
+struct {
+	int	type;
+	char	*name;
+} tokens[MAXTOKENS];
+int	ntokens;
+int	tokenix;
+
+void	f_proc (void);
+void	f_pass (void);
+void	f_list (void);		/* ENTRY, EXTERNAL label list */
+void	f_define (void);	/* ABSOLUTE, RELATIVE label list */
+void	f_move (void);
+void	f_jump (void);
+void	f_call (void);
+void	f_return (void);
+void	f_int (void);
+void	f_select (void);
+void	f_reselect (void);
+void	f_wait (void);
+void	f_disconnect (void);
+void	f_set (void);
+void	f_clear (void);
+void	f_load (void);
+void	f_store (void);
+void	f_nop (void);
+void	f_arch (void);
+
+struct {
+	char	*name;
+	void	(*func)(void);
+} directives[] = {
+	{"PROC",	f_proc},
+	{"PASS",	f_pass},
+	{"ENTRY",	f_list},
+	{"ABSOLUTE",	f_define},
+	{"EXTERN",	f_list},
+	{"EXTERNAL",	f_list},
+	{"RELATIVE",	f_define},
+	{"MOVE",	f_move},
+	{"JUMP",	f_jump},
+	{"CALL",	f_call},
+	{"RETURN",	f_return},
+	{"INT",		f_int},
+	{"SELECT",	f_select},
+	{"RESELECT",	f_reselect},
+	{"WAIT",	f_wait},
+	{"DISCONNECT",	f_disconnect},
+	{"SET",		f_set},
+	{"CLEAR",	f_clear},
+	{"LOAD",	f_load},
+	{"STORE",	f_store},
+	{"NOP",		f_nop},
+	{"ARCH",	f_arch},
+	{NULL, NULL}};
+
+u_int32_t script[MAXINST];
+int	dsps;
+char	*script_name = "SCRIPT";
+u_int32_t inst0, inst1, inst2;
+unsigned int	ninsts;
+unsigned int	npatches;
+
+struct patchlist {
+	struct patchlist *next;
+	unsigned	offset;
+};
+
+#define	S_LABEL		0x0000
+#define	S_ABSOLUTE	0x0001
+#define	S_RELATIVE	0x0002
+#define	S_EXTERNAL	0x0003
+#define	F_DEFINED	0x0001
+#define	F_ENTRY		0x0002
+struct {
+	short	type;
+	short	flags;
+	u_int32_t value;
+	struct patchlist *patchlist;
+	char	*name;
+} symbols[MAXSYMBOLS];
+int nsymbols;
+
+char	*stypes[] = {"Label", "Absolute", "Relative", "External"};
+
+char	*phases[] = {
+	"data_out", "data_in", "cmd", "status",
+	"res4", "res5", "msg_out", "msg_in"
+};
+
+struct ncrregs {
+	char *name;
+	int addr[4];
+};
+#define ARCH710 1
+#define ARCH720 2
+#define ARCH810 3
+#define ARCH825 4
+
+struct ncrregs 	regs[] = {
+	{"scntl0",	{0x00, 0x00, 0x00, 0x00}},
+	{"scntl1",	{0x01, 0x01, 0x01, 0x01}},
+	{"scntl2",	{-1,   0x02, 0x02, 0x02}},
+	{"scntl3",	{-1,   0x03, 0x03, 0x03}},
+	{"scid", 	{-1,   0x04, 0x04, 0x04}},
+	{"sdid",	{0x02,   -1,   -1,   -1}},
+	{"sien",	{0x03,   -1,   -1,   -1}},
+	{"scid",	{0x04,   -1,   -1,   -1}},
+	{"sxfer",	{0x05, 0x05, 0x05, 0x05}},
+	{"sdid",	{-1,   0x06, 0x06, 0x06}},
+	{"gpreg",	{-1,   0x07, 0x07, 0x07}},
+	{"sodl",	{0x06,   -1,   -1,   -1}},
+	{"socl",	{0x07,   -1,   -1,   -1}},
+	{"sfbr",	{0x08, 0x08, 0x08, 0x08}},
+	{"socl",	{-1,   0x09, 0x09, 0x09}},
+	{"ssid", 	{-1,   0x0a, 0x0a, 0x0a}},
+	{"sidl",	{0x09,   -1,   -1,   -1}},
+	{"sbdl",	{0x0a,   -1,   -1,   -1}},
+	{"sbcl",	{0x0b, 0x0b, 0x0b, 0x0b}}, 
+	{"dstat",	{0x0c, 0x0c, 0x0c, 0x0c}},
+	{"sstat0",	{0x0d, 0x0d, 0x0d, 0x0d}},
+	{"sstat1",	{0x0e, 0x0e, 0x0e, 0x0e}},
+	{"sstat2",	{0x0f, 0x0f, 0x0f, 0x0f}},
+	{"dsa0",	{0x10, 0x10, 0x10, 0x10}},
+	{"dsa1",	{0x11, 0x11, 0x11, 0x11}},
+	{"dsa2",	{0x12, 0x12, 0x12, 0x12}},
+	{"dsa3",	{0x13, 0x13, 0x13, 0x13}},
+	{"istat", 	{-1,   0x14, 0x14, 0x14}},
+	{"ctest0",	{0x14, 0x18, 0x18, 0x18}},
+	{"ctest1",	{0x15, 0x19, 0x19, 0x19}},
+	{"ctest2",	{0x16, 0x1a, 0x1a, 0x1a}},
+	{"ctest3",	{0x17, 0x1b, 0x1b, 0x1b}},
+	{"temp0",	{-1,   0x1c, 0x1c, 0x1c}},
+	{"temp1",	{-1,   0x1d, 0x1d, 0x1d}},
+	{"temp2", 	{-1,   0x1e, 0x1e, 0x1e}},
+	{"temp3",	{-1,   0x1f, 0x1f, 0x1f}},
+	{"dfifo",	{-1,   0x20, 0x20, 0x20}},
+	{"ctest4",	{0x18, 0x21, 0x21, 0x21}},
+	{"ctest5",	{0x19, 0x22, 0x22, 0x22}},
+	{"ctest6",	{0x20, 0x23, 0x23, 0x23}},
+	{"ctest7",	{0x21,   -1,   -1,   -1}},
+	{"temp0",	{0x22,   -1,   -1,   -1}},
+	{"temp1",	{0x23,   -1,   -1,   -1}},
+	{"temp2",	{0x24,   -1,   -1,   -1}},
+	{"temp3",	{0x25,   -1,   -1,   -1}},
+	{"dfifo",	{0x26,   -1,   -1,   -1}},
+	{"istat",	{0x27,   -1,   -1,   -1}},
+	{"ctest8",	{0x28,   -1,   -1,   -1}},
+	{"lcrc",	{0x29,   -1,   -1,   -1}},
+	{"dbc0",	{0x2a, 0x24, 0x24, 0x24}},
+	{"dbc1",	{0x2b, 0x25, 0x25, 0x25}},
+	{"dbc2",	{0x2c, 0x26, 0x26, 0x26}},
+	{"dcmd",	{0x2d, 0x27, 0x27, 0x27}},
+	{"dnad0",	{0x2e, 0x28, 0x28, 0x28}},
+	{"dnad1",	{0x2f, 0x29, 0x29, 0x29}},
+	{"dnad2",	{0x30, 0x2a, 0x2a, 0x2a}},
+	{"dnad3",	{0x31, 0x2b, 0x2b, 0x2b}},
+	{"dsp0",	{0x32, 0x2c, 0x2c, 0x2c}},
+	{"dsp1",	{0x33, 0x2d, 0x2d, 0x2d}},
+	{"dsp2",	{0x34, 0x2e, 0x2e, 0x2e}},
+	{"dsp3",	{0x35, 0x2f, 0x2f, 0x2f}},
+	{"dsps0",	{0x36, 0x30, 0x30, 0x30}},
+	{"dsps1",	{0x37, 0x31, 0x31, 0x31}},
+	{"dsps2",	{0x38, 0x32, 0x32, 0x32}},
+	{"dsps3",	{0x39, 0x33, 0x33, 0x33}},
+	{"scratch0",	{0x40,   -1,   -1,   -1}},
+	{"scratch1",	{0x41,   -1,   -1,   -1}},
+	{"scratch2",	{0x42,   -1,   -1,   -1}},
+	{"scratch3",	{0x43,   -1,   -1,   -1}},
+	{"scratcha0",	{  -1, 0x34, 0x34, 0x34}},
+	{"scratcha1",	{  -1, 0x35, 0x35, 0x35}},
+	{"scratcha2",	{  -1, 0x36, 0x36, 0x36}},
+	{"scratcha3",	{  -1, 0x37, 0x37, 0x37}},
+	{"dmode",	{0x44, 0x38, 0x38, 0x38}},
+	{"dien",	{0x45, 0x39, 0x39, 0x39}},
+	{"dwt",		{0x46, 0x3a,   -1,   -1}},
+	{"sbr",		{  -1,   -1, 0x3a, 0x3a}},
+	{"dcntl",	{0x47, 0x3b, 0x3b, 0x3b}},
+	{"addr0",	{0x48, 0x3c, 0x3c, 0x3c}},
+	{"addr1",	{0x49, 0x3d, 0x3d, 0x3d}},
+	{"addr2",	{0x4A, 0x3e, 0x3e, 0x3e}},
+	{"addr3",	{0x4B, 0x3f, 0x3f, 0x3f}},
+	{"sien0",	{  -1, 0x40, 0x40, 0x40}},
+	{"sien1",	{  -1, 0x41, 0x41, 0x41}},
+	{"sist0",	{  -1, 0x42, 0x42, 0x42}},
+	{"sist1",	{  -1, 0x43, 0x43, 0x43}},
+	{"slpar",	{  -1, 0x44, 0x44, 0x44}},
+	{"swide",	{  -1, 0x45,   -1, 0x45}},
+	{"macntl",	{  -1, 0x46, 0x46, 0x46}},
+	{"gpcntl",	{  -1, 0x47, 0x47, 0x47}},
+	{"stime0",	{  -1, 0x48, 0x48, 0x48}},
+	{"stime1",	{  -1, 0x49, 0x49, 0x49}},
+	{"respid0",	{  -1, 0x4a, 0x4a, 0x4a}},
+	{"respid1",	{  -1, 0x4b,   -1, 0x4b}},
+	{"stest0",	{  -1, 0x4c, 0x4c, 0x4c}},
+	{"stest1",	{  -1, 0x4d, 0x4d, 0x4d}},
+	{"stest2",	{  -1, 0x4e, 0x4e, 0x4e}},
+	{"stest3",	{  -1, 0x4f, 0x4f, 0x4f}},
+	{"sidl0",	{  -1, 0x50, 0x50, 0x50}},
+	{"sidl1",	{  -1, 0x51,   -1, 0x51}},
+	{"sodl0",	{  -1, 0x54, 0x54, 0x54}},
+	{"sodl1",	{  -1, 0x55,   -1, 0x55}},
+	{"sbdl0",	{  -1, 0x58, 0x58, 0x58}},
+	{"sbdl1",	{  -1, 0x59,   -1, 0x59}},
+	{"scratchb0",	{  -1, 0x5c, 0x5c, 0x5c}},
+	{"scratchb1",	{  -1, 0x5d, 0x5d, 0x5d}},
+	{"scratchb2",	{  -1, 0x5e, 0x5e, 0x5e}},
+	{"scratchb3",	{  -1, 0x5f, 0x5f, 0x5f}},
+	{"scratchc0",	{  -1,   -1,   -1, 0x60}},
+	{"scratchc1",	{  -1,   -1,   -1, 0x61}},
+	{"scratchc2",	{  -1,   -1,   -1, 0x62}},
+	{"scratchc3",	{  -1,   -1,   -1, 0x63}},
+	{"scratchd0",	{  -1,   -1,   -1, 0x64}},
+	{"scratchd1",	{  -1,   -1,   -1, 0x65}},
+	{"scratchd2",	{  -1,   -1,   -1, 0x5e}},
+	{"scratchd3",	{  -1,   -1,   -1, 0x67}},
+	{"scratche0",	{  -1,   -1,   -1, 0x68}},
+	{"scratche1",	{  -1,   -1,   -1, 0x69}},
+	{"scratche2",	{  -1,   -1,   -1, 0x6a}},
+	{"scratche3",	{  -1,   -1,   -1, 0x6b}},
+	{"scratchf0",	{  -1,   -1,   -1, 0x6c}},
+	{"scratchf1",	{  -1,   -1,   -1, 0x6d}},
+	{"scratchf2",	{  -1,   -1,   -1, 0x6e}},
+	{"scratchf3",	{  -1,   -1,   -1, 0x6f}},
+	{"scratchg0",	{  -1,   -1,   -1, 0x70}},
+	{"scratchg1",	{  -1,   -1,   -1, 0x71}},
+	{"scratchg2",	{  -1,   -1,   -1, 0x72}},
+	{"scratchg3",	{  -1,   -1,   -1, 0x73}},
+	{"scratchh0",	{  -1,   -1,   -1, 0x74}},
+	{"scratchh1",	{  -1,   -1,   -1, 0x75}},
+	{"scratchh2",	{  -1,   -1,   -1, 0x7e}},
+	{"scratchh3",	{  -1,   -1,   -1, 0x77}},
+	{"scratchi0",	{  -1,   -1,   -1, 0x78}},
+	{"scratchi1",	{  -1,   -1,   -1, 0x79}},
+	{"scratchi2",	{  -1,   -1,   -1, 0x7a}},
+	{"scratchi3",	{  -1,   -1,   -1, 0x7b}},
+	{"scratchj0",	{  -1,   -1,   -1, 0x7c}},
+	{"scratchj1",	{  -1,   -1,   -1, 0x7d}},
+	{"scratchj2",	{  -1,   -1,   -1, 0x7e}},
+	{"scratchj3",	{  -1,   -1,   -1, 0x7f}},
+};
+
+int	lineno;
+int	err_listed;
+int	arch;
+int	partial_flag;
+
+char	inbuf[128];
+
+char	*sourcefile;
+char	*outputfile;
+char	*listfile;
+char	*errorfile;
+
+FILE	*infp;
+FILE	*outfp;
+FILE	*listfp;
+FILE	*errfp;
+
+void	setarch(char *);
+void	parse (void);
+void	process (void);
+void	emit_symbols (void);
+void	list_symbols (void);
+void	errout (char *);
+void	define_symbol (char *, u_int32_t, short, short);
+void	close_script (void);
+void	new_script (char *);
+void	store_inst (void);
+int	expression (int *);
+int	evaluate (int);
+int	number (char *);
+int	lookup (char *);
+int	reserved (char *, int);
+int	CheckPhase (int);
+int	CheckRegister (int);
+void	transfer (int, int);
+void	select_reselect (int);
+void	set_clear (u_int32_t);
+void	block_move (void);
+void	register_write (void);
+void	memory_to_memory (void);
+void	loadstore (int);
+void	error_line(void);
+char	*makefn(char *, char *);
+void	usage(void);
+
+int
+main (int argc, char *argv[])
+{
+	int	i;
+
+	if (argc < 2 || argv[1][0] == '-')
+		usage();
+	sourcefile = argv[1];
+	infp = fopen (sourcefile, "r");
+	if (infp == NULL) {
+		perror ("open source");
+		fprintf (stderr, "scc: error opening source file %s\n", argv[1]);
+		exit (1);
+	}
+	/*
+	 * process options
+	 * -l [listfile]
+	 * -o [outputfile]
+	 * -p [outputfile]
+	 * -z [debugfile]
+	 * -e [errorfile]
+	 * -a arch
+	 * -v
+	 * -u
+	 */
+	for (i = 2; i < argc; ++i) {
+		if (argv[i][0] != '-')
+			usage();
+		switch (argv[i][1]) {
+		case 'o':
+		case 'p':
+			partial_flag = argv[i][1] == 'p';
+			if (i + 1 >= argc || argv[i + 1][0] == '-')
+				outputfile = makefn (sourcefile, "out");
+			else {
+				outputfile = argv[i + 1];
+				++i;
+			}
+			break;
+		case 'l':
+			if (i + 1 >= argc || argv[i + 1][0] == '-')
+				listfile = makefn (sourcefile, "lis");
+			else {
+				listfile = argv[i + 1];
+				++i;
+			}
+			break;
+		case 'e':
+			if (i + 1 >= argc || argv[i + 1][0] == '-')
+				errorfile = makefn (sourcefile, "err");
+			else {
+				errorfile = argv[i + 1];
+				++i;
+			}
+			break;
+		case 'a':
+			if (i + 1 == argc)
+				usage();
+			setarch(argv[i +1]);
+			if (arch == 0) {
+				fprintf(stderr,"%s: bad arch '%s'\n",
+					argv[0], argv[i +1]);
+				exit(1);
+			}
+			++i;
+			break;
+		default:
+			fprintf (stderr, "scc: unrecognized option '%c'\n",
+			    argv[i][1]);
+			usage();
+		}
+	}
+	if (outputfile)
+		outfp = fopen (outputfile, "w");
+	if (listfile)
+		listfp = fopen (listfile, "w");
+	if (errorfile)
+		errfp = fopen (errorfile, "w");
+	else
+		errfp = stderr;
+
+	if (outfp) {
+		time_t cur_time;
+
+		fprintf(outfp, "/*\t$NetBSD: ncr53cxxx.c,v 1.5 2000/10/23 14:51:51 bouyer Exp $\t*/\n");
+		fprintf(outfp, "/*\n");
+		fprintf(outfp, " *\tDO NOT EDIT - this file is automatically generated.\n");
+		time(&cur_time);
+		fprintf(outfp, " *\tcreated from %s on %s", sourcefile, ctime(&cur_time));
+		fprintf(outfp, " */\n");
+	}
+
+	while (fgets (inbuf, sizeof (inbuf), infp)) {
+		++lineno;
+		if (listfp)
+			fprintf (listfp, "%3d:  %s", lineno, inbuf);
+		err_listed = 0;
+		parse ();
+		if (ntokens) {
+#ifdef DUMP_TOKENS
+			int	i;
+
+			fprintf (listfp, "      %d tokens\n", ntokens);
+			for (i = 0; i < ntokens; ++i) {
+				fprintf (listfp, "      %d: ", i);
+				if (tokens[i].type)
+					fprintf (listfp,"'%c'\n", tokens[i].type);
+				else
+					fprintf (listfp, "%s\n", tokens[i].name);
+			}
+#endif
+			if (ntokens >= 2 && tokens[0].type == 0 &&
+			    tokens[1].type == ':') {
+			    	define_symbol (tokens[0].name, dsps, S_LABEL, F_DEFINED);
+				tokenix += 2;
+			}
+			if (tokenix < ntokens)
+				process ();
+		}
+
+	}
+	close_script ();
+	emit_symbols ();
+	if (outfp && !partial_flag) {
+		fprintf (outfp, "\nu_int32_t INSTRUCTIONS = 0x%08x;\n", ninsts);
+		fprintf (outfp, "u_int32_t PATCHES = 0x%08x;\n", npatches);
+	}
+	list_symbols ();
+	exit(0);
+}
+
+void setarch(char *val)
+{
+	switch (atoi(val)) {
+	case 710:
+		arch = ARCH710;
+		break;
+	case 720:
+		arch = ARCH720;
+		break;
+	case 810:
+		arch = ARCH810;
+		break;
+	case 825:
+		arch = ARCH825;
+		break;
+	default:
+		arch = 0;
+	}
+}
+
+void emit_symbols ()
+{
+	int	i;
+	struct	patchlist *p;
+
+	if (nsymbols == 0 || outfp == NULL)
+		return;
+
+	for (i = 0; i < nsymbols; ++i) {
+		char	*code;
+		if ((symbols[i].flags & F_DEFINED) == 0 &&
+		    symbols[i].type != S_EXTERNAL) {
+			fprintf(stderr, "warning: symbol %s undefined\n",
+			    symbols[i].name);
+		}
+		if (symbols[i].type == S_ABSOLUTE)
+			code = "A_";
+		else if (symbols[i].type == S_RELATIVE)
+			code = "R_";
+		else if (symbols[i].type == S_EXTERNAL)
+			code = "E_";
+		else if (symbols[i].flags & F_ENTRY)
+			code = "Ent_";
+		else
+			continue;
+		fprintf (outfp, "#define\t%s%s\t0x%08x\n", code, symbols[i].name,
+			symbols[i].value);
+		if (symbols[i].flags & F_ENTRY || symbols[i].patchlist == NULL)
+			continue;
+		fprintf (outfp, "u_int32_t %s%s_Used[] = {\n", code, symbols[i].name);
+#if 1
+		p = symbols[i].patchlist;
+		while (p) {
+			fprintf (outfp, "\t0x%08x,\n", p->offset / 4);
+			p = p->next;
+		}
+#endif
+		fprintf (outfp, "};\n\n");
+	}
+	/* patches ? */
+}
+
+void list_symbols ()
+{
+	int	i;
+
+	if (nsymbols == 0 || listfp == NULL)
+		return;
+	fprintf (listfp, "\n\nValue     Type     Symbol\n");
+	for (i = 0; i < nsymbols; ++i) {
+		fprintf (listfp, "%08x: %-8s %s\n", symbols[i].value,
+			stypes[symbols[i].type], symbols[i].name);
+	}
+}
+
+void errout (char *text)
+{
+	error_line();
+	fprintf (errfp, "*** %s ***\n", text);
+}
+
+void parse ()
+{
+	char *p = inbuf;
+	char c;
+	char string[64];
+	char *s;
+
+	ntokens = tokenix = 0;
+	while (1) {
+		while ((c = *p++) && c != '\n' && (c <= ' ' || c == '\t'))
+			;
+		if (c == '\n' || c == 0 || c == ';')
+			break;
+		if (ntokens >= MAXTOKENS) {
+			errout ("Token table full");
+			break;
+		}
+		if ((c >= '0' && c <= '9') || (c >= 'a' && c <= 'z') ||
+		    (c >= 'A' && c <= 'Z') || c == '$' || c == '_') {
+		    	s = string;
+		    	*s++ = c;
+		    	while (((c = *p) >= '0' && c <= '9') ||
+		    	    (c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') ||
+		    	    c == '_' || c == '$') {
+		    	    	*s++ = *p++;
+		    	}
+		    	*s = 0;
+		    	tokens[ntokens].name = malloc (strlen (string) + 1);
+		    	strcpy (tokens[ntokens].name, string);
+		    	tokens[ntokens].type = 0;
+		}
+		else {
+			tokens[ntokens].type = c;
+		}
+		++ntokens;
+	}
+	return;
+}
+
+void	process ()
+{
+	int	i;
+
+	if (tokens[tokenix].type) {
+		error_line();
+		fprintf (errfp, "Error: expected directive, found '%c'\n",
+			tokens[tokenix].type);
+		return;
+	}
+	for (i = 0; directives[i].name; ++i) {
+		if (strcmpi (directives[i].name, tokens[tokenix].name) == 0)
+			break;
+	}
+	if (directives[i].name == NULL) {
+		error_line();
+		fprintf (errfp, "Error: expected directive, found \"%s\"\n",
+			tokens[tokenix].name);
+		return;
+	}
+	if (directives[i].func == NULL) {
+		error_line();
+		fprintf (errfp, "No function for directive \"%s\"\n", tokens[tokenix].name);
+	} else {
+#if 0
+		fprintf (listfp, "Processing directive \"%s\"\n", directives[i].name);
+#endif
+		++tokenix;
+		(*directives[i].func) ();
+	}
+}
+
+void define_symbol (char *name, u_int32_t value, short type, short flags)
+{
+	int	i;
+	struct patchlist *p;
+
+	for (i = 0; i < nsymbols; ++i) {
+		if (symbols[i].type == type && strcmp (symbols[i].name, name) == 0) {
+			if (symbols[i].flags & F_DEFINED) {
+				error_line();
+				fprintf (errfp, "*** Symbol \"%s\" multiply defined\n",
+					name);
+			} else {
+				symbols[i].flags |= flags;
+				symbols[i].value = value;
+				p = symbols[i].patchlist;
+				while (p) {
+					if (p->offset > dsps)
+						errout ("Whoops\007");
+					else
+						script[p->offset / 4] = dsps - p->offset - 4;
+					p = p->next;
+				}
+			}
+			return;
+		}
+	}
+	if (nsymbols >= MAXSYMBOLS) {
+		errout ("Symbol table full");
+		return;
+	}
+	symbols[nsymbols].type = type;
+	symbols[nsymbols].flags = flags;
+	symbols[nsymbols].value = value;
+	symbols[nsymbols].patchlist = NULL;
+	symbols[nsymbols].name = malloc (strlen (name) + 1);
+	strcpy (symbols[nsymbols].name, name);
+	++nsymbols;
+}
+
+void close_script ()
+{
+	int	i;
+
+	if (dsps == 0)
+		return;
+	if (outfp) {
+		fprintf (outfp, "const u_int32_t %s[] = {\n", script_name);
+		for (i = 0; i < dsps / 4; i += 2) {
+			fprintf (outfp, "\t0x%08x, 0x%08x", script[i],
+				script[i + 1]);
+			/* check for memory move instruction */
+			if ((script[i] & 0xe0000000) == 0xc0000000)
+				fprintf (outfp, ", 0x%08x,", script[i + 2]);
+			else
+				if ((i + 2) <= dsps / 4) fprintf (outfp, ",\t\t");
+			fprintf (outfp, "\t/* %03x - %3d */\n", i * 4, i * 4);
+			if ((script[i] & 0xe0000000) == 0xc0000000)
+				++i;
+		}
+		fprintf (outfp, "};\n\n");
+	}
+	dsps = 0;
+}
+
+void new_script (char *name)
+{
+	close_script ();
+	script_name = malloc (strlen (name) + 1);
+	strcpy (script_name, name);
+}
+
+int	reserved (char *string, int t)
+{
+	if (tokens[t].type == 0 && strcmpi (tokens[t].name, string) == 0)
+		return (1);
+	return (0);
+}
+
+int	CheckPhase (int t)
+{
+	int	i;
+
+	for (i = 0; i < 8; ++i) {
+		if (reserved (phases[i], t)) {
+			inst0 |= i << 24;
+			return (1);
+		}
+	}
+	return (0);
+}
+
+int	CheckRegister (int t)
+{
+	int	i;
+
+	if (arch <= 0) {
+		errout("'ARCH' statement missing");
+		return -1;
+	}
+	for (i = 0; i < (sizeof(regs) / sizeof(regs[0])); i++) {
+		if (regs[i].addr[arch - 1] >= 0 && reserved(regs[i].name, t))
+			return regs[i].addr[arch-1];
+	}
+	return (-1);
+}
+
+int	expression (int *t)
+{
+	int	value;
+	int	i = *t;
+
+	value = evaluate (i++);
+	while (i < ntokens) {
+		if (tokens[i].type == '+')
+			value += evaluate (i + 1);
+		else if (tokens[i].type == '-')
+			value -= evaluate (i + 1);
+		else
+			errout ("Unknown identifier");
+		i += 2;
+	}
+	*t = i;
+	return (value);
+}
+
+int	evaluate (t)
+{
+	int	value;
+	char	*name;
+
+	if (tokens[t].type) {
+		errout ("Expected an identifier");
+		return (0);
+	}
+	name = tokens[t].name;
+	if (*name >= '0' && *name <= '9')
+		value = number (name);
+	else
+		value = lookup (name);
+	return (value);
+}
+
+int	number (char *s)
+{
+	int	value;
+	int	n;
+	int	radix;
+
+	radix = 10;
+	if (*s == '0') {
+		++s;
+		radix = 8;
+		switch (*s) {
+		case 'x':
+		case 'X':
+			radix = 16;
+			break;
+		case 'b':
+		case 'B':
+			radix = 2;
+		}
+		if (radix != 8)
+			++s;
+	}
+	value = 0;
+	while (*s) {
+		n = *s++;
+		if (n >= '0' && n <= '9')
+			n -= '0';
+		else if (n >= 'a' && n <= 'f')
+			n -= 'a' - 10;
+		else if (n >= 'A' && n <= 'F')
+			n -= 'A' - 10;
+		else {
+			error_line();
+			fprintf (errfp, "*** Expected digit\n");
+			n = 0;
+		}
+		if (n >= radix)
+			errout ("Expected digit");
+		else
+			value = value * radix + n;
+	}
+	return (value);
+}
+
+int	lookup (char *name)
+{
+	int	i;
+	struct patchlist *p;
+
+	for (i = 0; i < nsymbols; ++i) {
+		if (strcmp (name, symbols[i].name) == 0) {
+			if ((symbols[i].flags & F_DEFINED) == 0) {
+				p = (struct patchlist *) &symbols[i].patchlist;
+				while (p->next)
+					p = p->next;
+				p->next = (struct patchlist *) malloc (sizeof (struct patchlist));
+				p = p->next;
+				p->next = NULL;
+				p->offset = dsps + 4;
+			}
+			return ((int) symbols[i].value);
+		}
+	}
+	if (nsymbols >= MAXSYMBOLS) {
+		errout ("Symbol table full");
+		return (0);
+	}
+	symbols[nsymbols].type = S_LABEL;	/* assume forward reference */
+	symbols[nsymbols].flags = 0;
+	symbols[nsymbols].value = 0;
+	p = (struct patchlist *) malloc (sizeof (struct patchlist));
+	symbols[nsymbols].patchlist = p;
+	p->next = NULL;
+	p->offset = dsps + 4;
+	symbols[nsymbols].name = malloc (strlen (name) + 1);
+	strcpy (symbols[nsymbols].name, name);
+	++nsymbols;
+	return (0);
+}
+
+void	f_arch (void)
+{
+	int i, archsave;
+
+	i = tokenix;
+
+	archsave = arch;
+	setarch(tokens[i].name);
+	if( arch == 0) {
+		errout("Unrecognized ARCH");
+		arch = archsave;
+	}
+}
+
+void	f_proc (void)
+{
+	if (tokens[tokenix].type != 0 || tokens[tokenix + 1].type != ':')
+		errout ("Invalid PROC statement");
+	else
+		new_script (tokens[tokenix].name);
+}
+
+void	f_pass (void)
+{
+	errout ("PASS option not implemented");
+}
+
+/*
+ *	f_list:  process list of symbols for the ENTRY and EXTERNAL directive
+ */
+
+void	f_list (void)
+{
+	int	i;
+	short	type;
+	short	flags;
+
+	type = strcmpi (tokens[tokenix-1].name, "ENTRY") ? S_EXTERNAL : S_LABEL;
+	flags = type == S_LABEL ? F_ENTRY : 0;
+	for (i = tokenix; i < ntokens; ++i) {
+		if (tokens[i].type != 0) {
+			errout ("Expected an identifier");
+			return;
+		}
+		define_symbol (tokens[i].name, 0, type, flags);
+		if (i + 1 < ntokens) {
+			if (tokens[++i].type == ',')
+				continue;
+			errout ("Expected a separator");
+			return;
+		}
+	}
+}
+
+/*
+ *	f_define:	process list of definitions for ABSOLUTE and RELATIVE directive
+ */
+
+void	f_define (void)
+{
+	int	i;
+	char	*name;
+	u_int32_t value;
+	int	type;
+
+	type = strcmpi (tokens[tokenix-1].name, "ABSOLUTE") ? S_RELATIVE : S_ABSOLUTE;
+	i = tokenix;
+	while (i < ntokens) {
+		if (tokens[i].type) {
+			errout ("Expected an identifier");
+			return;
+		}
+		if (tokens[i + 1].type != '=') {
+			errout ("Expected a separator");
+			return;
+		}
+		name = tokens[i].name;
+		i += 2;
+		value = expression (&i);
+		define_symbol (name, value, type, F_DEFINED);
+	}
+}
+
+void	store_inst ()
+{
+	int	i = dsps / 4;
+	int	l = 8;
+
+	if ((inst0 & 0xe0000000) == 0xc0000000)
+		l = 12;			/* Memory to memory move is 12 bytes */
+	if ((dsps + l) / 4 > MAXINST) {
+		errout ("Instruction table overflow");
+		return;
+	}
+	script[i++] = inst0;
+	script[i++] = inst1;
+	if (l == 12)
+		script[i++] = inst2;
+	if (listfp) {
+		fprintf (listfp, "\t%04x: %08x %08x", dsps, inst0, inst1);
+		if (l == 12)
+			fprintf (listfp, " %08x", inst2);
+		fprintf (listfp, "\n");
+	}
+	dsps += l;
+	inst0 = inst1 = inst2 = 0;
+	++ninsts;
+}
+
+void	f_move (void)
+{
+	if (reserved ("memory", tokenix))
+		memory_to_memory ();
+	else if (reserved ("from", tokenix) || tokens[tokenix+1].type == ',')
+		block_move ();
+	else
+		register_write ();
+	store_inst ();
+}
+
+void	f_jump (void)
+{
+	transfer (0x80000000, 0);
+}
+
+void	f_call (void)
+{
+	transfer (0x88000000, 0);
+}
+
+void	f_return (void)
+{
+	transfer (0x90000000, 1);
+}
+
+void	f_int (void)
+{
+	transfer (0x98000000, 2);
+}
+
+void	f_select (void)
+{
+	int	t = tokenix;
+
+	if (reserved ("atn", t)) {
+		inst0 = 0x01000000;
+		++t;
+	}
+	select_reselect (t);
+}
+
+void	f_reselect (void)
+{
+	select_reselect (tokenix);
+}
+
+void	f_wait (void)
+{
+	int	i = tokenix;
+
+	inst1 = 0;
+	if (reserved ("disconnect", i)) {
+		inst0 = 0x48000000;
+	}
+	else {
+		if (reserved ("reselect", i))
+			inst0 = 0x50000000;
+		else if (reserved ("select", i))
+			inst0 = 0x50000000;
+		else
+			errout ("Expected SELECT or RESELECT");
+		++i;
+		if (reserved ("rel", i)) {
+			i += 2;
+			inst1 = evaluate (i) - dsps - 8;
+			inst0 |= 0x04000000;
+		}
+		else
+			inst1 = evaluate (i);
+	}
+	store_inst ();
+}
+
+void	f_disconnect (void)
+{
+	inst0 = 0x48000000;
+	store_inst ();
+}
+
+void	f_set (void)
+{
+	set_clear (0x58000000);
+}
+
+void	f_clear (void)
+{
+	set_clear (0x60000000);
+}
+
+void	f_load (void)
+{
+	inst0 = 0xe1000000;
+	if (arch < ARCH810) {
+		errout ("Wrong arch for load/store");
+		return;
+	}
+	loadstore(tokenix);
+}
+
+void	f_store (void)
+{
+	int i;
+	inst0 = 0xe0000000;
+	if (arch < ARCH810) {
+		errout ("Wrong arch for load/store");
+		return;
+	}
+	i = tokenix;
+	if (reserved("noflush", i)) {
+		inst0 |= 0x2000000;
+		i++;
+	}
+	loadstore(i);
+}
+
+void	f_nop (void)
+{
+	inst0 = 0x10000000;
+	inst1 = 0x00000000;
+	store_inst ();
+}
+
+void loadstore(int i)
+{
+	int reg, size;
+
+	reg = CheckRegister(i);
+	if (reg < 0)	
+		errout ("Expected register");
+	else
+		inst0 |= reg <<  16;
+	if (reg == 8)
+		errout ("Register can't be SFBR");
+	i++;
+	if (tokens[i].type == ',')
+		i++;
+	else
+		errout ("expected ','");
+	size = evaluate(i);
+	if (i < 1 || i > 4)
+		errout("wrong size");
+	if ((reg & 0x3) + size > 4)
+		errout("size too big for register");
+	inst0 |= size;
+	i++;
+	if (tokens[i].type == ',')
+		i++;
+	else
+		errout ("expected ','");
+	if (reserved("from", i) || reserved("dsarel", i)) {
+		i++;
+		inst0 |= 0x10000000;
+	}
+	inst1 = evaluate(i);
+	store_inst ();
+}
+
+void	transfer (int word0, int type)
+{
+	int	i;
+
+	i = tokenix;
+	inst0 = word0;
+	if (type == 0 && reserved ("rel", i)) {
+		inst1 = evaluate (i + 2) - dsps - 8;
+		i += 4;
+		inst0 |= 0x00800000;
+	}
+	else if (type != 1) {
+		inst1 = evaluate (i);
+		++i;
+	}
+	if (i >= ntokens) {
+		inst0 |= 0x00080000;
+		store_inst ();
+		return;
+	}
+	if (tokens[i].type != ',')
+		errout ("Expected a separator, ',' assumed");
+	else
+		++i;
+	if (reserved("when", i))
+		inst0 |= 0x00010000;
+	else if (reserved ("if", i) == 0) {
+		errout ("Expected a reserved word");
+		store_inst ();
+		return;
+	}
+	i++;
+	if (reserved("false", i)) {
+		store_inst ();
+		return;
+	}
+	if (reserved ("not", i))
+		++i;
+	else
+		inst0 |= 0x00080000;
+	if (reserved ("atn", i)) {
+		inst0 |= 0x00020000;
+		++i;
+	} else if (CheckPhase (i)) {
+		inst0 |= 0x00020000;
+		++i;
+	}
+	if (i < ntokens && tokens[i].type != ',') {
+		if (inst0 & 0x00020000) {
+			if (inst0 & 0x00080000 && reserved ("and", i)) {
+				++i;
+			}
+			else if ((inst0 & 0x00080000) == 0 && reserved ("or", i)) {
+				++i;
+			}
+			else
+				errout ("Expected a reserved word");
+		}
+		inst0 |= 0x00040000 + (evaluate (i++) & 0xff);
+	}
+	if (i < ntokens) {
+		if (tokens[i].type == ',')
+			++i;
+		else
+			errout ("Expected a separator, ',' assumed");
+		if (reserved ("and", i) && reserved ("mask", i + 1))
+			inst0 |= ((evaluate (i + 2) & 0xff) << 8);
+		else
+			errout ("Expected , AND MASK");
+	}
+	store_inst ();
+}
+
+void 	select_reselect (int t)
+{
+	inst0 |= 0x40000000;		/* ATN may be set from SELECT */
+	if (reserved ("from", t)) {
+		++t;
+		inst0 |= 0x02000000 | evaluate (t++);
+	}
+	else
+		inst0 |= (evaluate (t++) & 0xff) << 16;
+	if (tokens[t++].type == ',') {
+		if (reserved ("rel", t)) {
+			inst0 |= 0x04000000;
+			inst1 = evaluate (t + 2) - dsps - 8;
+		}
+		else
+			inst1 = evaluate (t);
+	}
+	else
+		errout ("Expected separator");
+	store_inst ();
+}
+
+void	set_clear (u_int32_t code)
+{
+	int	i = tokenix;
+	short	need_and = 0;
+
+	inst0 = code;
+	while (i < ntokens) {
+		if (need_and) {
+			if (reserved ("and", i))
+				++i;
+			else
+				errout ("Expected AND");
+		}
+		if (reserved ("atn", i)) {
+			inst0 |= 0x0008;
+			++i;
+		}
+		else if (reserved ("ack", i)) {
+			inst0 |= 0x0040;
+			++i;
+		}
+		else if (reserved ("target", i)) {
+			inst0 |= 0x0200;
+			++i;
+		}
+		else
+			errout ("Expected ATN, ACK, or TARGET");
+		need_and = 1;
+	}
+	store_inst ();
+}
+
+void	block_move ()
+{
+	if (reserved ("from", tokenix)) {
+		inst1 = evaluate (tokenix+1);
+		inst0 |= 0x10000000 | inst1;	/*** ??? to match Zeus script */
+		tokenix += 2;
+	}
+	else {
+		inst0 |= evaluate (tokenix++);	/* count */
+		tokenix++;			/* skip ',' */
+		if (reserved ("ptr", tokenix)) {
+			++ tokenix;
+			inst0 |= 0x20000000;
+		}
+		inst1 = evaluate (tokenix++);	/* address */
+	}
+	if (tokens[tokenix].type != ',')
+		errout ("Expected separator");
+	if (reserved ("when", tokenix + 1)) {
+		inst0 |= 0x08000000;
+		CheckPhase (tokenix + 2);
+	}
+	else if (reserved ("with", tokenix + 1)) {
+		CheckPhase (tokenix + 2);
+	}
+	else
+		errout ("Expected WITH or WHEN");
+}
+
+void	register_write ()
+{
+	/*
+	 * MOVE reg/data8 TO reg			register write
+	 * MOVE reg <op> data8 TO reg			register write
+	 * MOVE reg + data8 TO reg WITH CARRY		register write
+	 */
+	int	op;
+	int	reg;
+	int	data;
+
+	if (reserved ("to", tokenix+1))
+		op = 0;
+	else if (tokens[tokenix+1].type == '|')
+		op = 2;
+	else if (tokens[tokenix+1].type == '&')
+		op = 4;
+	else if (tokens[tokenix+1].type == '+')
+		op = 6;
+	else if (tokens[tokenix+1].type == '-')
+		op = 8;
+	else
+		errout ("Unknown register operator");
+	if (op && reserved ("to", tokenix+3) == 0)
+		errout ("Register command expected TO");
+	reg = CheckRegister (tokenix);
+	if (reg < 0) {			/* Not register, must be data */
+		data = evaluate (tokenix);
+		if (op)
+			errout ("Register operator not move");
+		reg = CheckRegister (tokenix+2);
+		if (reg < 0)
+			errout ("Expected register");
+		inst0 = 0x78000000 | (data << 8) | reg << 16;
+#if 0
+fprintf (listfp, "Move data to register: %02x %d\n", data, reg);
+#endif
+	}
+	else if (op) {			/* A register read/write operator */
+		data = evaluate (tokenix+2);
+		if (tokenix+5 < ntokens) {
+			if (!reserved("with", tokenix+5) ||
+			    !reserved("carry", tokenix+6)) {
+				errout("Expected 'WITH CARRY'");
+			} else if (op != 6) {
+				errout("'WITH CARRY' only valide with '+'");
+			}
+			op = 7;
+		}
+		if (op == 8) {
+			data = -data;
+			op = 6;
+		}
+		inst0 = (data & 0xff) << 8;
+		data = CheckRegister (tokenix+4);
+		if (data < 0)
+			errout ("Expected register");
+		if (reg != data && reg != 8 && data != 8)
+			errout ("One register MUST be SBFR");
+		if (reg == data) {	/* A register read/modify/write */
+#if 0
+fprintf (listfp, "Read/modify register: %02x %d %d\n", inst0 >> 8, op, reg);
+#endif
+			inst0 |= 0x78000000 | (op << 24) | (reg << 16);
+		}
+		else {			/* A move to/from SFBR */
+			if (reg == 8) {	/* MOVE SFBR <> TO reg */
+#if 0
+fprintf (listfp, "Move SFBR to register: %02x %d %d\n", inst0 >> 8, op, data);
+#endif
+				inst0 |= 0x68000000 | (op << 24) | (data << 16);
+			}
+			else {
+#if 0
+fprintf (listfp, "Move register to SFBR: %02x %d %d\n", inst0 >> 8, op, reg);
+#endif
+				inst0 |= 0x70000000 | (op << 24) | (reg << 16);
+			}
+		}
+	}
+	else {				/* register to register */
+		data = CheckRegister (tokenix+2);
+		if (reg == 8)		/* move SFBR to reg */
+			inst0 = 0x6a000000 | (data << 16);
+		else if (data == 8)	/* move reg to SFBR */
+			inst0 = 0x72000000 | (reg << 16);
+		else
+			errout ("One register must be SFBR");
+	}
+}
+
+void	memory_to_memory ()
+{
+	inst0 = 0xc0000000 + evaluate (tokenix+1);
+	inst1 = evaluate (tokenix+3);
+	/*
+	 * need to hack dsps, otherwise patch offset will be wrong for
+	 * second pointer
+	 */
+	dsps += 4;
+	inst2 = evaluate (tokenix+5);
+	dsps -= 4;
+}
+
+void	error_line()
+{
+	if (errfp != listfp && errfp && err_listed == 0) {
+		fprintf (errfp, "%3d:  %s", lineno, inbuf);
+		err_listed = 1;
+	}
+}
+
+char *	makefn (base, sub)
+	char *base;
+	char *sub;
+{
+	char *fn;
+
+	fn = malloc (strlen (base) + strlen (sub) + 2);
+	strcpy (fn, base);
+	base = strrchr(fn, '.');
+	if (base)
+		*base = 0;
+	strcat (fn, ".");
+	strcat (fn, sub);
+	return (fn);
+}
+
+void	usage()
+{
+	fprintf (stderr, "usage: scc sourcfile [options]\n");
+	exit(1);
+}
diff --git a/sys/dev/microcode/siop/siop.out b/sys/dev/microcode/siop/siop.out
new file mode 100644
index 00000000000..04f97fd382d
--- /dev/null
+++ b/sys/dev/microcode/siop/siop.out
@@ -0,0 +1,407 @@
+/*	$OpenBSD: siop.out,v 1.1 2001/02/15 04:07:59 krw Exp $ */
+/*	$NetBSD: siop.out,v 1.11 2000/10/23 14:54:50 bouyer Exp $	*/
+/*
+ *	DO NOT EDIT - this file is automatically generated.
+ *	created from siop.ss on Mon Oct 23 16:54:27 2000
+ */
+const u_int32_t siop_script[] = {
+	0x78340000, 0x00000000,			/* 000 -   0 */
+	0x78350000, 0x00000000,			/* 008 -   8 */
+	0x72370000, 0x00000000,			/* 010 -  16 */
+	0x80840020, 0x00000300,			/* 018 -  24 */
+	0x868b0000, 0x00000368,			/* 020 -  32 */
+	0x878b0000, 0x000002e0,			/* 028 -  40 */
+	0x808b0000, 0x000003f0,			/* 030 -  48 */
+	0x818b0000, 0x00000388,			/* 038 -  56 */
+	0x828b0000, 0x00000360,			/* 040 -  64 */
+	0x838b0000, 0x00000368,			/* 048 -  72 */
+	0x98080000, 0x0000ffff,			/* 050 -  80 */
+	0x741a4000, 0x00000000,			/* 058 -  88 */
+	0x980c0000, 0x0000ff83,			/* 060 -  96 */
+	0x7810ff00, 0x00000000,			/* 068 - 104 */
+	0x7811ff00, 0x00000000,			/* 070 - 112 */
+	0x7812ff00, 0x00000000,			/* 078 - 120 */
+	0x7813ff00, 0x00000000,			/* 080 - 128 */
+	0x78340000, 0x00000000,			/* 088 - 136 */
+	0x78350000, 0x00000000,			/* 090 - 144 */
+	0x80000000, 0x00000000,			/* 098 - 152 */
+	0x80000000, 0x00000000,			/* 0a0 - 160 */
+	0x80000000, 0x00000000,			/* 0a8 - 168 */
+	0x80000000, 0x00000000,			/* 0b0 - 176 */
+	0x80000000, 0x00000000,			/* 0b8 - 184 */
+	0x80000000, 0x00000000,			/* 0c0 - 192 */
+	0x80000000, 0x00000000,			/* 0c8 - 200 */
+	0x80000000, 0x00000000,			/* 0d0 - 208 */
+	0x80000000, 0x00000000,			/* 0d8 - 216 */
+	0x80000000, 0x00000000,			/* 0e0 - 224 */
+	0x80000000, 0x00000000,			/* 0e8 - 232 */
+	0x80000000, 0x00000000,			/* 0f0 - 240 */
+	0x80000000, 0x00000000,			/* 0f8 - 248 */
+	0x80000000, 0x00000000,			/* 100 - 256 */
+	0x80000000, 0x00000000,			/* 108 - 264 */
+	0x80000000, 0x00000000,			/* 110 - 272 */
+	0x80000000, 0x00000000,			/* 118 - 280 */
+	0x80000000, 0x00000000,			/* 120 - 288 */
+	0x80000000, 0x00000000,			/* 128 - 296 */
+	0x80000000, 0x00000000,			/* 130 - 304 */
+	0x80000000, 0x00000000,			/* 138 - 312 */
+	0x80000000, 0x00000000,			/* 140 - 320 */
+	0x80000000, 0x00000000,			/* 148 - 328 */
+	0x80000000, 0x00000000,			/* 150 - 336 */
+	0x80000000, 0x00000000,			/* 158 - 344 */
+	0x80000000, 0x00000000,			/* 160 - 352 */
+	0x80000000, 0x00000000,			/* 168 - 360 */
+	0x80000000, 0x00000000,			/* 170 - 368 */
+	0x80000000, 0x00000000,			/* 178 - 376 */
+	0x80000000, 0x00000000,			/* 180 - 384 */
+	0x80000000, 0x00000000,			/* 188 - 392 */
+	0x80000000, 0x00000000,			/* 190 - 400 */
+	0x80000000, 0x00000000,			/* 198 - 408 */
+	0x80000000, 0x00000000,			/* 1a0 - 416 */
+	0x80000000, 0x00000000,			/* 1a8 - 424 */
+	0x80000000, 0x00000000,			/* 1b0 - 432 */
+	0x80000000, 0x00000000,			/* 1b8 - 440 */
+	0x80000000, 0x00000000,			/* 1c0 - 448 */
+	0x80000000, 0x00000000,			/* 1c8 - 456 */
+	0x80000000, 0x00000000,			/* 1d0 - 464 */
+	0x7810ff00, 0x00000000,			/* 1d8 - 472 */
+	0x7811ff00, 0x00000000,			/* 1e0 - 480 */
+	0x7812ff00, 0x00000000,			/* 1e8 - 488 */
+	0x7813ff00, 0x00000000,			/* 1f0 - 496 */
+	0x78360000, 0x00000000,			/* 1f8 - 504 */
+	0x78372000, 0x00000000,			/* 200 - 512 */
+	0x54000000, 0xfffffe48,			/* 208 - 520 */
+	0x740a8f00, 0x00000000,			/* 210 - 528 */
+	0x6a340000, 0x00000000,			/* 218 - 536 */
+	0x800c00ff, 0x00000000,			/* 220 - 544 */
+	0x800c00ff, 0x00000000,			/* 228 - 552 */
+	0x800c00ff, 0x00000000,			/* 230 - 560 */
+	0x800c00ff, 0x00000000,			/* 238 - 568 */
+	0x800c00ff, 0x00000000,			/* 240 - 576 */
+	0x800c00ff, 0x00000000,			/* 248 - 584 */
+	0x800c00ff, 0x00000000,			/* 250 - 592 */
+	0x800c00ff, 0x00000000,			/* 258 - 600 */
+	0x800c00ff, 0x00000000,			/* 260 - 608 */
+	0x800c00ff, 0x00000000,			/* 268 - 616 */
+	0x800c00ff, 0x00000000,			/* 270 - 624 */
+	0x800c00ff, 0x00000000,			/* 278 - 632 */
+	0x800c00ff, 0x00000000,			/* 280 - 640 */
+	0x800c00ff, 0x00000000,			/* 288 - 648 */
+	0x800c00ff, 0x00000000,			/* 290 - 656 */
+	0x98080000, 0x0000ff80,			/* 298 - 664 */
+	0x0f000001, 0x00000000,			/* 2a0 - 672 */
+	0x6c350700, 0x00000000,			/* 2a8 - 680 */
+	0x60000040, 0x00000000,			/* 2b0 - 688 */
+	0x97030000, 0x00000000,			/* 2b8 - 696 */
+	0x0f000001, 0x00000000,			/* 2c0 - 704 */
+	0x60000040, 0x00000000,			/* 2c8 - 712 */
+	0x6a370000, 0x00000000,			/* 2d0 - 720 */
+	0x90040020, 0x00000000,			/* 2d8 - 728 */
+	0x0f000001, 0x00000000,			/* 2e0 - 736 */
+	0x60000040, 0x00000000,			/* 2e8 - 744 */
+	0x6a360000, 0x00000000,			/* 2f0 - 752 */
+	0x90080000, 0x00000000,			/* 2f8 - 760 */
+	0x60000040, 0x00000000,			/* 300 - 768 */
+	0x7a340100, 0x00000000,			/* 308 - 776 */
+	0x60000008, 0x00000000,			/* 310 - 784 */
+	0x1f000020, 0x00000020,			/* 318 - 792 */
+	0x808c0000, 0x00000218,			/* 320 - 800 */
+	0x808c0002, 0xffffffd0,			/* 328 - 808 */
+	0x808c0001, 0x00000218,			/* 330 - 816 */
+	0x98040004, 0x0000ff01,			/* 338 - 824 */
+	0x88880000, 0x000001d0,			/* 340 - 832 */
+	0x74340100, 0x00000000,			/* 348 - 840 */
+	0x808c0000, 0xfffffd10,			/* 350 - 848 */
+	0x72350000, 0x00000000,			/* 358 - 856 */
+	0x808c0000, 0xfffffd00,			/* 360 - 864 */
+	0x98080000, 0x0000ff04,			/* 368 - 872 */
+	0x60000040, 0x00000000,			/* 370 - 880 */
+	0x80880000, 0xfffffca0,			/* 378 - 888 */
+	0x58000008, 0x00000000,			/* 380 - 896 */
+	0x60000040, 0x00000000,			/* 388 - 904 */
+	0x1e000038, 0x00000038,			/* 390 - 912 */
+	0x60000008, 0x00000000,			/* 398 - 920 */
+	0x80880000, 0xfffffc78,			/* 3a0 - 928 */
+	0x1a000040, 0x00000040,			/* 3a8 - 936 */
+	0x80880000, 0xfffffc68,			/* 3b0 - 944 */
+	0x1b000048, 0x00000048,			/* 3b8 - 952 */
+	0x80880000, 0xfffffc58,			/* 3c0 - 960 */
+	0x88880000, 0x000000b8,			/* 3c8 - 968 */
+	0x7a340200, 0x00000000,			/* 3d0 - 976 */
+	0x19000050, 0x00000050,			/* 3d8 - 984 */
+	0x7e350100, 0x00000000,			/* 3e0 - 992 */
+	0x7e100800, 0x00000000,			/* 3e8 - 1000 */
+	0x7f110000, 0x00000000,			/* 3f0 - 1008 */
+	0x7f120000, 0x00000000,			/* 3f8 - 1016 */
+	0x7f130000, 0x00000000,			/* 400 - 1024 */
+	0x818b0000, 0xffffffc8,			/* 408 - 1032 */
+	0x88880000, 0x000000b8,			/* 410 - 1040 */
+	0x7c34fd00, 0x00000000,			/* 418 - 1048 */
+	0x80880000, 0xfffffbf8,			/* 420 - 1056 */
+	0x88880000, 0x00000058,			/* 428 - 1064 */
+	0x7a340200, 0x00000000,			/* 430 - 1072 */
+	0x18000050, 0x00000050,			/* 438 - 1080 */
+	0x7e350100, 0x00000000,			/* 440 - 1088 */
+	0x7e100800, 0x00000000,			/* 448 - 1096 */
+	0x7f110000, 0x00000000,			/* 450 - 1104 */
+	0x7f120000, 0x00000000,			/* 458 - 1112 */
+	0x7f130000, 0x00000000,			/* 460 - 1120 */
+	0x808b0000, 0xffffffc8,			/* 468 - 1128 */
+	0x88880000, 0x00000058,			/* 470 - 1136 */
+	0x7c34fd00, 0x00000000,			/* 478 - 1144 */
+	0x80880000, 0xfffffb98,			/* 480 - 1152 */
+	0x72100000, 0x00000000,			/* 488 - 1160 */
+	0x6a5c0000, 0x00000000,			/* 490 - 1168 */
+	0x72110000, 0x00000000,			/* 498 - 1176 */
+	0x6a5d0000, 0x00000000,			/* 4a0 - 1184 */
+	0x72120000, 0x00000000,			/* 4a8 - 1192 */
+	0x6a5e0000, 0x00000000,			/* 4b0 - 1200 */
+	0x72130000, 0x00000000,			/* 4b8 - 1208 */
+	0x6a5f0000, 0x00000000,			/* 4c0 - 1216 */
+	0x90080000, 0x00000000,			/* 4c8 - 1224 */
+	0x725c0000, 0x00000000,			/* 4d0 - 1232 */
+	0x6a100000, 0x00000000,			/* 4d8 - 1240 */
+	0x725d0000, 0x00000000,			/* 4e0 - 1248 */
+	0x6a110000, 0x00000000,			/* 4e8 - 1256 */
+	0x725e0000, 0x00000000,			/* 4f0 - 1264 */
+	0x6a120000, 0x00000000,			/* 4f8 - 1272 */
+	0x725f0000, 0x00000000,			/* 500 - 1280 */
+	0x6a130000, 0x00000000,			/* 508 - 1288 */
+	0x90080000, 0x00000000,			/* 510 - 1296 */
+	0x7c027f00, 0x00000000,			/* 518 - 1304 */
+	0x60000008, 0x00000000,			/* 520 - 1312 */
+	0x60000040, 0x00000000,			/* 528 - 1320 */
+	0x48000000, 0x00000000,			/* 530 - 1328 */
+	0x90080000, 0x00000000,			/* 538 - 1336 */
+	0x88880000, 0xffffffd0,			/* 540 - 1344 */
+	0x98080000, 0x0000ff00,			/* 548 - 1352 */
+	0x60000040, 0x00000000,			/* 550 - 1360 */
+	0x1f000028, 0x00000028,			/* 558 - 1368 */
+	0x98080000, 0x0000ff02,			/* 560 - 1376 */
+	0x60000040, 0x00000000,			/* 568 - 1384 */
+	0x1f000030, 0x00000030,			/* 570 - 1392 */
+	0x98080000, 0x0000ff03,			/* 578 - 1400 */
+	0x10000000, 0x00000000,			/* 580 - 1408 */
+};
+
+const u_int32_t lun_switch[] = {
+	0x7803ff00, 0x00000000,			/* 000 -   0 */
+	0x7805ff00, 0x00000000,			/* 008 -   8 */
+	0x80080000, 0x00000000,			/* 010 -  16 */
+	0x88880000, 0xffffffe0,			/* 018 -  24 */
+	0x72350000, 0x00000000,			/* 020 -  32 */
+	0x98080000, 0x0000ff81,			/* 028 -  40 */
+};
+
+const u_int32_t tag_switch[] = {
+	0x72360000, 0x00000000,			/* 000 -   0 */
+	0x800c0000, 0x00000000,			/* 008 -   8 */
+	0x800c0001, 0x00000000,			/* 010 -  16 */
+	0x800c0002, 0x00000000,			/* 018 -  24 */
+	0x800c0003, 0x00000000,			/* 020 -  32 */
+	0x800c0004, 0x00000000,			/* 028 -  40 */
+	0x800c0005, 0x00000000,			/* 030 -  48 */
+	0x800c0006, 0x00000000,			/* 038 -  56 */
+	0x800c0007, 0x00000000,			/* 040 -  64 */
+	0x800c0008, 0x00000000,			/* 048 -  72 */
+	0x800c0009, 0x00000000,			/* 050 -  80 */
+	0x800c000a, 0x00000000,			/* 058 -  88 */
+	0x800c000b, 0x00000000,			/* 060 -  96 */
+	0x800c000c, 0x00000000,			/* 068 - 104 */
+	0x800c000d, 0x00000000,			/* 070 - 112 */
+	0x800c000e, 0x00000000,			/* 078 - 120 */
+	0x800c000f, 0x00000000,			/* 080 - 128 */
+	0x98080000, 0x0000ff82,			/* 088 - 136 */
+};
+
+const u_int32_t load_dsa[] = {
+	0x7810f000, 0x00000000,			/* 000 -   0 */
+	0x7811f100, 0x00000000,			/* 008 -   8 */
+	0x7812f200, 0x00000000,			/* 010 -  16 */
+	0x7813f300, 0x00000000,			/* 018 -  24 */
+	0x90080000, 0x00000000,			/* 020 -  32 */
+	0x88880000, 0xffffffd0,			/* 028 -  40 */
+	0x80080000, 0x00000000,			/* 030 -  48 */
+	0x88880000, 0xffffffc0,			/* 038 -  56 */
+	0x43000018, 0x00000000,			/* 040 -  64 */
+	0xc0000004, 0x00000000, 0x00000000,	/* 048 -  72 */
+	0x80080000, 0x00000000,			/* 054 -  84 */
+	0x10000000, 0x00000000,			/* 05c -  92 */
+};
+
+#define	A_t_id	0x00000018
+#define	A_t_msg_in	0x00000020
+#define	A_t_ext_msg_in	0x00000028
+#define	A_t_ext_msg_data	0x00000030
+#define	A_t_msg_out	0x00000038
+#define	A_t_cmd	0x00000040
+#define	A_t_status	0x00000048
+#define	A_t_data	0x00000050
+#define	A_int_done	0x0000ff00
+#define	A_int_msgin	0x0000ff01
+#define	A_int_extmsgin	0x0000ff02
+#define	A_int_extmsgdata	0x0000ff03
+#define	A_int_disc	0x0000ff04
+#define	A_int_reseltarg	0x0000ff80
+#define	A_int_resellun	0x0000ff81
+#define	A_int_reseltag	0x0000ff82
+#define	A_int_resfail	0x0000ff83
+#define	A_int_err	0x0000ffff
+#define	A_flag_sdp	0x00000001
+#define	A_flag_data	0x00000002
+#define	A_flag_data_mask	0x000000fd
+#define	Ent_waitphase	0x00000020
+#define	Ent_send_msgout	0x00000380
+#define	Ent_msgout	0x00000390
+#define	Ent_msgin	0x00000310
+#define	Ent_handle_msgin	0x00000320
+#define	Ent_msgin_ack	0x00000370
+#define	Ent_dataout	0x00000428
+#define	Ent_datain	0x000003c8
+#define	Ent_cmdout	0x000003a8
+#define	Ent_status	0x000003b8
+#define	Ent_disconnect	0x00000518
+#define	Ent_reselect	0x000001d8
+#define	Ent_reselected	0x00000000
+#define	Ent_selected	0x00000370
+#define	Ent_script_sched	0x00000068
+#define	Ent_script_sched_slot0	0x00000098
+#define	Ent_get_extmsgdata	0x00000568
+#define	Ent_resel_targ0	0x00000220
+#define	Ent_msgin_space	0x00000580
+#define	Ent_lunsw_return	0x000002a0
+#define	E_abs_script_sched_slot0	0x00000000
+u_int32_t E_abs_script_sched_slot0_Used[] = {
+	0x00000027,
+	0x00000029,
+	0x0000002b,
+	0x0000002d,
+	0x0000002f,
+	0x00000031,
+	0x00000033,
+	0x00000035,
+	0x00000037,
+	0x00000039,
+	0x0000003b,
+	0x0000003d,
+	0x0000003f,
+	0x00000041,
+	0x00000043,
+	0x00000045,
+	0x00000047,
+	0x00000049,
+	0x0000004b,
+	0x0000004d,
+	0x0000004f,
+	0x00000051,
+	0x00000053,
+	0x00000055,
+	0x00000057,
+	0x00000059,
+	0x0000005b,
+	0x0000005d,
+	0x0000005f,
+	0x00000061,
+	0x00000063,
+	0x00000065,
+	0x00000067,
+	0x00000069,
+	0x0000006b,
+	0x0000006d,
+	0x0000006f,
+	0x00000071,
+	0x00000073,
+	0x00000075,
+};
+
+#define	E_abs_targ0	0x00000000
+u_int32_t E_abs_targ0_Used[] = {
+	0x00000089,
+	0x0000008b,
+	0x0000008d,
+	0x0000008f,
+	0x00000091,
+	0x00000093,
+	0x00000095,
+	0x00000097,
+	0x00000099,
+	0x0000009b,
+	0x0000009d,
+	0x0000009f,
+	0x000000a1,
+	0x000000a3,
+	0x000000a5,
+};
+
+#define	E_abs_msgin	0x00000000
+u_int32_t E_abs_msgin_Used[] = {
+	0x000000a9,
+	0x000000b1,
+	0x000000b9,
+};
+
+#define	Ent_lun_switch_entry	0x00000018
+#define	Ent_resel_lun0	0x00000028
+#define	Ent_restore_scntl3	0x00000000
+#define	E_abs_lunsw_return	0x00000000
+u_int32_t E_abs_lunsw_return_Used[] = {
+	0x00000005,
+};
+
+#define	Ent_tag_switch_entry	0x00000000
+#define	Ent_resel_tag0	0x00000008
+#define	E_abs_tag0	0x00000000
+u_int32_t E_abs_tag0_Used[] = {
+	0x00000003,
+	0x00000005,
+	0x00000007,
+	0x00000009,
+	0x0000000b,
+	0x0000000d,
+	0x0000000f,
+	0x00000011,
+	0x00000013,
+	0x00000015,
+	0x00000017,
+	0x00000019,
+	0x0000001b,
+	0x0000001d,
+	0x0000001f,
+	0x00000021,
+};
+
+#define	Ent_rdsa0	0x00000000
+#define	Ent_rdsa1	0x00000008
+#define	Ent_rdsa2	0x00000010
+#define	Ent_rdsa3	0x00000018
+#define	Ent_ldsa_reload_dsa	0x00000028
+#define	Ent_ldsa_select	0x00000038
+#define	Ent_ldsa_data	0x0000005c
+#define	E_ldsa_abs_reselected	0x00000000
+u_int32_t E_ldsa_abs_reselected_Used[] = {
+	0x0000000d,
+};
+
+#define	E_ldsa_abs_reselect	0x00000000
+u_int32_t E_ldsa_abs_reselect_Used[] = {
+	0x00000011,
+};
+
+#define	E_ldsa_abs_selected	0x00000000
+u_int32_t E_ldsa_abs_selected_Used[] = {
+	0x00000016,
+};
+
+#define	E_ldsa_abs_data	0x00000000
+u_int32_t E_ldsa_abs_data_Used[] = {
+	0x00000013,
+};
+
+#define	E_ldsa_abs_slot	0x00000000
+u_int32_t E_ldsa_abs_slot_Used[] = {
+	0x00000014,
+};
+
+
+u_int32_t INSTRUCTIONS = 0x000000d5;
+u_int32_t PATCHES = 0x00000000;
diff --git a/sys/dev/microcode/siop/siop.ss b/sys/dev/microcode/siop/siop.ss
new file mode 100644
index 00000000000..d272e73f7fa
--- /dev/null
+++ b/sys/dev/microcode/siop/siop.ss
@@ -0,0 +1,409 @@
+;	$OpenBSD: siop.ss,v 1.1 2001/02/15 04:07:59 krw Exp $
+;	$NetBSD: siop.ss,v 1.12 2000/10/23 14:53:53 bouyer Exp $
+
+;
+;  Copyright (c) 2000 Manuel Bouyer.
+; 
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions
+;  are met:
+;  1. Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;  2. Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;  3. All advertising materials mentioning features or use of this software
+;     must display the following acknowledgement:
+; 	This product includes software developed by Manuel Bouyer
+;  4. The name of the author may not be used to endorse or promote products
+;     derived from this software without specific prior written permission.
+; 
+;  THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+;  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+;  OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+;  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+;  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+;  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ARCH 720
+
+; offsets in sym_xfer
+ABSOLUTE t_id = 24;
+ABSOLUTE t_msg_in = 32;
+ABSOLUTE t_ext_msg_in = 40;
+ABSOLUTE t_ext_msg_data = 48;
+ABSOLUTE t_msg_out = 56;
+ABSOLUTE t_cmd = 64;
+ABSOLUTE t_status = 72;
+ABSOLUTE t_data = 80;
+
+;; interrupt codes
+; interrupts that need a valid DSA
+ABSOLUTE int_done	= 0xff00;
+ABSOLUTE int_msgin	= 0xff01;
+ABSOLUTE int_extmsgin	= 0xff02;
+ABSOLUTE int_extmsgdata	= 0xff03;
+ABSOLUTE int_disc	= 0xff04;
+; interrupts that don't have a valid DSA
+ABSOLUTE int_reseltarg	= 0xff80;
+ABSOLUTE int_resellun	= 0xff81;
+ABSOLUTE int_reseltag	= 0xff82;
+ABSOLUTE int_resfail	= 0xff83;
+ABSOLUTE int_err 	= 0xffff;
+
+; flags for scratcha0
+ABSOLUTE flag_sdp 	= 0x01 ; got save data pointer
+ABSOLUTE flag_data 	= 0x02 ; we're in data phase
+ABSOLUTE flag_data_mask	= 0xfd ; ~flag_data
+
+; main script symbols
+
+ENTRY waitphase;
+ENTRY send_msgout;
+ENTRY msgout;
+ENTRY msgin;
+ENTRY handle_msgin;
+ENTRY msgin_ack;
+ENTRY dataout;
+ENTRY datain;
+ENTRY cmdout;
+ENTRY status;
+ENTRY disconnect;
+ENTRY reselect;
+ENTRY reselected;
+ENTRY selected;
+ENTRY script_sched;
+ENTRY script_sched_slot0;
+ENTRY get_extmsgdata;
+ENTRY resel_targ0;
+ENTRY msgin_space;
+ENTRY lunsw_return;
+EXTERN abs_script_sched_slot0;
+EXTERN abs_targ0;
+EXTERN abs_msgin;
+
+; lun switch symbols
+ENTRY lun_switch_entry;
+ENTRY resel_lun0;
+ENTRY restore_scntl3;
+EXTERN abs_lunsw_return;
+
+; tag switch symbols
+ENTRY tag_switch_entry;
+ENTRY resel_tag0;
+EXTERN abs_tag0;
+
+; command reselect script symbols
+ENTRY rdsa0;
+ENTRY rdsa1;
+ENTRY rdsa2;
+ENTRY rdsa3;
+ENTRY ldsa_reload_dsa;
+ENTRY ldsa_select;
+ENTRY ldsa_data;
+
+EXTERN ldsa_abs_reselected;
+EXTERN ldsa_abs_reselect;
+EXTERN ldsa_abs_selected;
+EXTERN ldsa_abs_data;
+EXTERN ldsa_abs_slot;
+
+; main script
+
+PROC  siop_script:
+
+reselected:
+; starting a new session, init 'local variables'
+	MOVE 0 to SCRATCHA0	; flags
+	MOVE 0 to SCRATCHA1	; DSA offset (for S/G save data pointer)
+	MOVE SCRATCHA3 to SFBR  ; pending message ?
+	JUMP REL(handle_msgin), IF not 0x20;
+waitphase:
+	JUMP REL(msgout), WHEN MSG_OUT;
+	JUMP REL(msgin), WHEN MSG_IN;
+	JUMP REL(dataout), WHEN DATA_OUT;
+	JUMP REL(datain), WHEN DATA_IN;
+	JUMP REL(cmdout), WHEN CMD;
+	JUMP REL(status), WHEN STATUS;
+	INT int_err;
+
+reselect_fail:
+	; check that host asserted SIGP, this'll clear SIGP in ISTAT
+	MOVE CTEST2 & 0x40 TO SFBR;
+	INT int_resfail,  IF 0x00;
+script_sched:
+	; Clear DSA and init status
+	MOVE 0xff to DSA0;
+	MOVE 0xff to DSA1;
+	MOVE 0xff to DSA2;
+	MOVE 0xff to DSA3;
+	MOVE 0 to SCRATCHA0	; flags
+	MOVE 0 to SCRATCHA1	; DSA offset (for S/G save data pointer)
+; the script scheduler: siop_start() we set the absolute jump addr, and then 
+; changes the FALSE to TRUE. The select script will change it back to false
+; once the target is selected.
+; The RAM could hold 370 slot entry, we limit it to 40. Should be more than
+; enouth.
+script_sched_slot0:
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+	JUMP abs_script_sched_slot0, IF FALSE;
+; Nothing to do, wait for reselect
+reselect:
+	; Clear DSA and init status
+	MOVE 0xff to DSA0;
+	MOVE 0xff to DSA1;
+	MOVE 0xff to DSA2;
+	MOVE 0xff to DSA3;
+	MOVE 0x00 to SCRATCHA2; no tag
+	MOVE 0x20 to SCRATCHA3; simple tag msg, ignored by reselected:
+	WAIT RESELECT REL(reselect_fail)
+	MOVE SSID & 0x8f to SFBR
+	MOVE SFBR to SCRATCHA0 ; save reselect ID
+; find the rigth param for this target
+resel_targ0:
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	JUMP abs_targ0, IF 0xff;
+	INT int_reseltarg;
+lunsw_return:
+	MOVE 1, abs_msgin, WHEN MSG_IN;
+	MOVE SFBR & 0x07 to SCRATCHA1; save LUN
+	CLEAR ACK;
+	RETURN, WHEN NOT MSG_IN; If no more message, jump to lun sw
+	MOVE 1, abs_msgin, WHEN MSG_IN;
+	CLEAR ACK;
+	MOVE SFBR  to SCRATCHA3; save message
+	RETURN, IF NOT 0x20; jump to lun sw if not simple tag msg
+	MOVE 1, abs_msgin, WHEN MSG_IN; get tag
+	CLEAR ACK;
+	MOVE SFBR  to SCRATCHA2; save tag
+	RETURN; jump to lun sw
+
+handle_sdp:
+	CLEAR ACK;
+	MOVE SCRATCHA0 | flag_sdp TO SCRATCHA0;
+	; should get a disconnect message now
+msgin:
+	CLEAR ATN
+	MOVE FROM t_msg_in, WHEN MSG_IN;
+handle_msgin:
+	JUMP REL(handle_cmpl), IF 0x00        ; command complete message
+	JUMP REL(handle_sdp), IF 0x02	      ; save data pointer message
+	JUMP REL(handle_extin), IF 0x01	      ; extended message
+	INT int_msgin, IF not 0x04;
+	CALL REL(disconnect)                  ; disconnect message;
+; if we didn't get sdp, or if offset is 0, no need to interrupt
+	MOVE SCRATCHA0 & flag_sdp TO SFBR;
+	JUMP REL(script_sched), if 0x00; 
+	MOVE SCRATCHA1 TO SFBR;
+	JUMP REL(script_sched), if 0x00; 
+; Ok, we need to save data pointers
+	INT int_disc;
+msgin_ack:
+selected:
+	CLEAR ACK;
+	JUMP REL(waitphase);
+
+; entry point for msgout after a msgin or status phase
+send_msgout:
+	SET ATN;
+	CLEAR ACK;
+msgout:
+	MOVE FROM t_msg_out, WHEN MSG_OUT;
+	CLEAR ATN;
+	JUMP REL(waitphase);
+cmdout:
+	MOVE FROM t_cmd, WHEN CMD;
+	JUMP REL(waitphase);
+status:
+	MOVE FROM t_status, WHEN STATUS;
+	JUMP REL(waitphase);
+datain:
+	CALL REL(savedsa);
+	MOVE SCRATCHA0 | flag_data TO SCRATCHA0;
+datain_loop:
+	MOVE FROM t_data, WHEN DATA_IN;
+	MOVE SCRATCHA1 + 1 TO SCRATCHA1	; adjust offset
+	MOVE DSA0 + 8 to DSA0;
+	MOVE DSA1 + 0 to DSA1 WITH CARRY;
+	MOVE DSA2 + 0 to DSA2 WITH CARRY;
+	MOVE DSA3 + 0 to DSA3 WITH CARRY;
+	JUMP REL(datain_loop), WHEN DATA_IN;
+	CALL REL(restoredsa);
+	MOVE SCRATCHA0 & flag_data_mask TO SCRATCHA0;
+	JUMP REL(waitphase);
+
+dataout:
+	CALL REL(savedsa);
+	MOVE SCRATCHA0 | flag_data TO SCRATCHA0;
+dataout_loop:
+	MOVE FROM t_data, WHEN DATA_OUT;
+	MOVE SCRATCHA1 + 1 TO SCRATCHA1	; adjust offset
+	MOVE DSA0 + 8 to DSA0;
+	MOVE DSA1 + 0 to DSA1 WITH CARRY;
+	MOVE DSA2 + 0 to DSA2 WITH CARRY;
+	MOVE DSA3 + 0 to DSA3 WITH CARRY;
+	JUMP REL(dataout_loop), WHEN DATA_OUT;
+	CALL REL(restoredsa);
+	MOVE SCRATCHA0 & flag_data_mask TO SCRATCHA0;
+	JUMP REL(waitphase);
+
+savedsa:
+	MOVE DSA0 to SFBR;
+	MOVE SFBR to SCRATCHB0;
+	MOVE DSA1 to SFBR;
+	MOVE SFBR to SCRATCHB1;
+	MOVE DSA2 to SFBR;
+	MOVE SFBR to SCRATCHB2;
+	MOVE DSA3 to SFBR;
+	MOVE SFBR to SCRATCHB3;
+	RETURN;
+
+restoredsa:
+	MOVE SCRATCHB0 TO SFBR;
+	MOVE SFBR TO DSA0;
+	MOVE SCRATCHB1 TO SFBR;
+	MOVE SFBR TO DSA1;
+	MOVE SCRATCHB2 TO SFBR;
+	MOVE SFBR TO DSA2;
+	MOVE SCRATCHB3 TO SFBR;
+	MOVE SFBR TO DSA3;
+	RETURN;
+
+disconnect:
+	MOVE SCNTL2 & 0x7f TO SCNTL2;
+	CLEAR ATN;
+	CLEAR ACK;
+	WAIT DISCONNECT;
+	RETURN;
+
+handle_cmpl:
+	CALL REL(disconnect);
+	INT int_done;
+
+handle_extin:
+	CLEAR ACK;
+	MOVE FROM t_ext_msg_in, WHEN MSG_IN;
+	INT int_extmsgin; /* let host fill in t_ext_msg_data */
+get_extmsgdata:
+	CLEAR ACK;
+	MOVE FROM t_ext_msg_data, WHEN MSG_IN;
+	INT int_extmsgdata;
+msgin_space:
+	NOP; space to store msgin when reselect
+
+
+;; per-target switch script for LUNs
+; hack: we first do a call to the target-specific code, so that a return
+; in the main switch will jump to the lun switch.
+PROC lun_switch:
+restore_scntl3:
+	MOVE 0xff TO SCNTL3;
+	MOVE 0xff TO SXFER;
+	JUMP abs_lunsw_return;
+lun_switch_entry:
+	CALL REL(restore_scntl3);
+	MOVE SCRATCHA1 TO SFBR;
+resel_lun0:
+	INT int_resellun;
+
+;; Per-device switch script for tag
+PROC tag_switch:
+tag_switch_entry:
+	MOVE SCRATCHA2 TO SFBR; restore tag
+resel_tag0:
+	JUMP abs_tag0, IF 0x00;
+	JUMP abs_tag0, IF 0x01;
+	JUMP abs_tag0, IF 0x02;
+	JUMP abs_tag0, IF 0x03;
+	JUMP abs_tag0, IF 0x04;
+	JUMP abs_tag0, IF 0x05;
+	JUMP abs_tag0, IF 0x06;
+	JUMP abs_tag0, IF 0x07;
+	JUMP abs_tag0, IF 0x08;
+	JUMP abs_tag0, IF 0x09;
+	JUMP abs_tag0, IF 0x0a;
+	JUMP abs_tag0, IF 0x0b;
+	JUMP abs_tag0, IF 0x0c;
+	JUMP abs_tag0, IF 0x0d;
+	JUMP abs_tag0, IF 0x0e;
+	JUMP abs_tag0, IF 0x0f;
+	INT int_reseltag;
+
+;; per-command script: select, and called after a reselect to load DSA
+
+PROC load_dsa:
+; Can't use MOVE MEMORY to load DSA, doesn't work I/O mapped
+rdsa0:
+	MOVE 0xf0 to DSA0;
+rdsa1:
+	MOVE 0xf1 to DSA1;
+rdsa2:
+	MOVE 0xf2 to DSA2;
+rdsa3:
+	MOVE 0xf3 to DSA3;
+	RETURN;
+ldsa_reload_dsa:
+	CALL REL(rdsa0);
+	JUMP ldsa_abs_reselected;
+ldsa_select:
+	CALL REL(rdsa0);
+	SELECT ATN FROM t_id, ldsa_abs_reselect;
+	MOVE MEMORY 4, ldsa_abs_data, ldsa_abs_slot;
+	JUMP ldsa_abs_selected;
+ldsa_data:
+	NOP; contains data used by the MOVE MEMORY
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index b57dac99aaf..38f424b1182 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pci,v 1.93 2001/02/14 05:10:17 fgsch Exp $
+#	$OpenBSD: files.pci,v 1.94 2001/02/15 04:07:57 krw Exp $
 #	$NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
 #
 # Config file and device description for machine-independent PCI code.
@@ -161,6 +161,15 @@ device	ncr: scsi
 attach	ncr at pci
 file	dev/pci/ncr.c			ncr
 
+# common code for siop/esiop pci front end
+define siop_pci_common
+file	dev/pci/siop_pci_common.c	siop_pci_common
+
+# Symbios 53c8xx SCSI chips
+# device declaration in sys/conf/files
+attach	siop at pci with siop_pci: siop_pci_common
+file	dev/pci/siop_pci.c	siop_pci
+
 # NeoMagic 256AV and 256ZX
 device	neo: audio, auconv, mulaw, ac97
 attach	neo at pci
diff --git a/sys/dev/pci/siop_pci.c b/sys/dev/pci/siop_pci.c
new file mode 100644
index 00000000000..c57749cb05a
--- /dev/null
+++ b/sys/dev/pci/siop_pci.c
@@ -0,0 +1,84 @@
+/*	$OpenBSD: siop_pci.c,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$NetBSD: siop_pci.c,v 1.8 2000/05/15 07:53:17 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/ic/siopvar.h>
+#include <dev/pci/siop_pci_common.h>
+
+int     siop_pci_match __P((struct device *, void *, void *));
+void    siop_pci_attach __P((struct device *, struct device *, void *));
+
+struct cfattach siop_pci_ca = {
+	sizeof(struct siop_pci_softc), siop_pci_match, siop_pci_attach
+};
+
+int
+siop_pci_match(parent, match, aux)
+	struct device *parent;
+	void *match;
+	void *aux;
+{
+	struct pci_attach_args *pa = aux;
+	const struct siop_product_desc *pp;
+
+	/* look if it's a known product */
+	pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
+	if (pp)
+		return 1;
+	return 0;
+}
+
+void
+siop_pci_attach(parent, self, aux)
+	struct device *parent, *self;
+	void *aux;
+{
+	struct pci_attach_args *pa = aux;
+	struct siop_pci_softc *sc = (struct siop_pci_softc *)self;
+
+	if (siop_pci_attach_common(sc, pa) == 0)
+		return;
+
+	siop_attach(&sc->siop);
+}
diff --git a/sys/dev/pci/siop_pci_common.c b/sys/dev/pci/siop_pci_common.c
new file mode 100644
index 00000000000..11b85509fe9
--- /dev/null
+++ b/sys/dev/pci/siop_pci_common.c
@@ -0,0 +1,347 @@
+/*	$OpenBSD: siop_pci_common.c,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$NetBSD: siop_pci_common.c,v 1.6 2001/01/10 15:50:20 thorpej Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/buf.h>
+#include <sys/kernel.h>
+
+#include <machine/endian.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <scsi/scsi_all.h>
+#include <scsi/scsiconf.h>
+
+#include <dev/ic/siopreg.h>
+#include <dev/ic/siopvar.h>
+#include <dev/pci/siop_pci_common.h>
+
+/* List (array, really :) of chips we know how to handle */
+const struct siop_product_desc siop_products[] = {
+	{ PCI_PRODUCT_SYMBIOS_810,
+	0x00,
+	"Symbios Logic 53c810 (fast scsi)",
+	SF_PCI_RL | SF_CHIP_LS,
+	4, 8, 3, 250, 0
+	},
+	{ PCI_PRODUCT_SYMBIOS_810,
+	0x10,
+	"Symbios Logic 53c810a (fast scsi)",
+	SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
+	4, 8, 3, 250, 0
+	},
+	{ PCI_PRODUCT_SYMBIOS_815,
+	0x00,
+	"Symbios Logic 53c815 (fast scsi)",
+	SF_PCI_RL | SF_PCI_BOF,
+	4, 8, 3, 250, 0
+	},
+	{ PCI_PRODUCT_SYMBIOS_820,
+	0x00,
+	"Symbios Logic 53c820 (fast wide scsi)",
+	SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
+	4, 8, 3, 250, 0
+	},
+	{ PCI_PRODUCT_SYMBIOS_825,
+	0x00,
+	"Symbios Logic 53c825 (fast wide scsi)",
+	SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
+	4, 8, 3, 250, 0
+	},
+	{ PCI_PRODUCT_SYMBIOS_825,
+	0x10,
+	"Symbios Logic 53c825a (fast wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_WIDE,
+	7, 8, 3, 250, 4096
+	},
+	{ PCI_PRODUCT_SYMBIOS_860,
+	0x00,
+	"Symbios Logic 53c860 (ultra scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_PF | SF_CHIP_LS |
+	SF_BUS_ULTRA,
+	4, 8, 5, 125, 0
+	},
+	{ PCI_PRODUCT_SYMBIOS_875,
+	0x00,
+	"Symbios Logic 53c875 (ultra-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA | SF_BUS_WIDE,
+	7, 16, 5, 125, 4096
+	},
+	{ PCI_PRODUCT_SYMBIOS_875,
+	0x02,
+	"Symbios Logic 53c875 (ultra-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
+	SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA | SF_BUS_WIDE,
+	7, 16, 5, 125, 4096
+	},
+	{ PCI_PRODUCT_SYMBIOS_875J,
+	0x00,
+	"Symbios Logic 53c875j (ultra-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
+	SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA | SF_BUS_WIDE,
+	7, 16, 5, 125, 4096
+	},
+	{ PCI_PRODUCT_SYMBIOS_885,
+	0x00,
+	"Symbios Logic 53c885 (ultra-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
+	SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA | SF_BUS_WIDE,
+	7, 16, 5, 125, 4096
+	},
+	{ PCI_PRODUCT_SYMBIOS_895,
+	0x00,
+	"Symbios Logic 53c895 (ultra2-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
+	SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA2 | SF_BUS_WIDE,
+	7, 31, 7, 62, 4096
+	},
+	{ PCI_PRODUCT_SYMBIOS_896,
+	0x00,
+	"Symbios Logic 53c896 (ultra2-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
+	SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA2 | SF_BUS_WIDE,
+	7, 31, 7, 62, 8192
+	},
+	{ PCI_PRODUCT_SYMBIOS_895A,
+	0x00,
+	"Symbios Logic 53c895a (ultra2-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
+	SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA2 | SF_BUS_WIDE,
+	7, 31, 7, 62, 8192
+	},
+	{ PCI_PRODUCT_SYMBIOS_1510D,
+	0x00,
+	"Symbios Logic 53c1510d (ultra2-wide scsi)",
+	SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
+	SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
+	SF_CHIP_LS | SF_CHIP_10REGS |
+	SF_BUS_ULTRA2 | SF_BUS_WIDE,
+	7, 31, 7, 62, 4096
+	},
+	{ 0,
+	0x00,
+	NULL,
+	0x00,
+	0, 0, 0, 0, 0
+	},
+};
+
+const struct siop_product_desc *
+siop_lookup_product(id, rev)
+	u_int32_t id;
+	int rev;
+{
+	const struct siop_product_desc *pp;
+	const struct siop_product_desc *rp = NULL;
+
+	if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS)
+		return NULL;
+
+	for (pp = siop_products; pp->name != NULL; pp++) {
+		if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev)
+			if (rp == NULL || pp->revision > rp->revision)
+				rp = pp;
+	}
+	return rp;
+}
+
+int
+siop_pci_attach_common(sc, pa)
+	struct siop_pci_softc *sc;
+	struct pci_attach_args *pa;
+{
+	pci_chipset_tag_t pc = pa->pa_pc;
+	pcitag_t tag = pa->pa_tag;    
+	const char *intrstr;
+	pci_intr_handle_t intrhandle;
+	bus_space_tag_t iot, memt;
+	bus_space_handle_t ioh, memh;
+	pcireg_t memtype;
+	int memh_valid, ioh_valid;
+	bus_addr_t ioaddr, memaddr;
+
+	sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
+	if (sc->sc_pp == NULL) {
+		printf("sym: broken match/attach!!\n");
+		return 0;
+	}
+	/* copy interesting infos about the chip */
+	sc->siop.features = sc->sc_pp->features;
+	sc->siop.maxburst = sc->sc_pp->maxburst;
+	sc->siop.maxoff = sc->sc_pp->maxoff;
+	sc->siop.clock_div = sc->sc_pp->clock_div;
+	sc->siop.clock_period = sc->sc_pp->clock_period;
+	sc->siop.ram_size = sc->sc_pp->ram_size;
+
+	sc->siop.sc_reset = siop_pci_reset;
+	printf(": %s\n", sc->sc_pp->name);
+	sc->sc_pc = pc;
+	sc->sc_tag = tag;
+	sc->siop.sc_dmat = pa->pa_dmat;
+
+	memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14);
+	switch (memtype) {
+	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
+	case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
+		memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0,
+		    &memt, &memh, &memaddr, NULL) == 0);
+		break;
+	default:
+		memh_valid = 0;
+	}
+
+	ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
+	    &iot, &ioh, &ioaddr, NULL) == 0);
+
+	if (memh_valid) {
+		sc->siop.sc_rt = memt;
+		sc->siop.sc_rh = memh;
+		sc->siop.sc_raddr = memaddr;
+	} else if (ioh_valid) {
+		sc->siop.sc_rt = iot;
+		sc->siop.sc_rh = ioh;
+		sc->siop.sc_raddr = ioaddr;
+	} else {
+		printf("%s: unable to map device registers\n",
+		    sc->siop.sc_dev.dv_xname);
+		return 0;
+	}
+
+	if (sc->siop.features & SF_CHIP_RAM) {
+		int bar;
+		switch (memtype) {
+		case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
+			bar = 0x18;
+			break;
+		case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
+			bar = 0x1c;
+			break;
+		}
+		if (pci_mapreg_map(pa, bar, memtype, 0,
+                    &sc->siop.sc_ramt, &sc->siop.sc_ramh,
+		    &sc->siop.sc_scriptaddr, NULL) == 0) {
+			printf("%s: using on-board RAM\n",
+			    sc->siop.sc_dev.dv_xname);
+		} else {
+			printf("%s: can't map on-board RAM\n",
+			    sc->siop.sc_dev.dv_xname);
+			sc->siop.features &= ~SF_CHIP_RAM;
+		}
+	}
+
+	if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
+			 pa->pa_intrline, &intrhandle)) {
+		printf("%s: couldn't map interrupt\n",
+		    sc->siop.sc_dev.dv_xname);
+		return 0;
+	}
+	intrstr = pci_intr_string(pa->pa_pc, intrhandle);
+	sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
+	    siop_intr, &sc->siop, sc->siop.sc_dev.dv_xname);
+	if (sc->sc_ih != NULL) {
+		printf("%s: interrupting at %s\n",
+		    sc->siop.sc_dev.dv_xname,
+		    intrstr ? intrstr : "unknown interrupt");
+	} else {
+		printf("%s: couldn't establish interrupt",
+		    sc->siop.sc_dev.dv_xname);
+		if (intrstr != NULL)
+			printf(" at %s", intrstr);
+		printf("\n");
+		return 0;
+	}
+	return 1;
+}
+
+void
+siop_pci_reset(sc)
+	struct siop_softc *sc;
+{
+	int dmode;
+
+	dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE);
+	if (sc->features & SF_PCI_RL)
+		dmode |= DMODE_ERL;
+	if (sc->features & SF_PCI_RM)
+		dmode |= DMODE_ERMP;
+	if (sc->features & SF_PCI_BOF)
+		dmode |= DMODE_BOF;
+	if (sc->features & SF_PCI_CLS)
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) |
+		    DCNTL_CLSE);
+	if (sc->features & SF_PCI_WRI)
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
+		    CTEST3_WRIE);
+	if (sc->maxburst) {
+		int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh,
+		    SIOP_CTEST5);
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) &
+		    ~CTEST4_BDIS);
+		dmode &= ~DMODE_BL_MASK;
+		dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK;
+		ctest5 &= ~CTEST5_BBCK;
+		ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);
+	} else {
+		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
+		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |
+		    CTEST4_BDIS);
+	}
+	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode);
+}
diff --git a/sys/dev/pci/siop_pci_common.h b/sys/dev/pci/siop_pci_common.h
new file mode 100644
index 00000000000..cc53d21bf53
--- /dev/null
+++ b/sys/dev/pci/siop_pci_common.h
@@ -0,0 +1,61 @@
+/*	$OpenBSD: siop_pci_common.h,v 1.1 2001/02/15 04:07:58 krw Exp $ */
+/*	$NetBSD: siop_pci_common.h,v 1.2 2000/10/23 14:57:23 bouyer Exp $	*/
+
+/*
+ * Copyright (c) 2000 Manuel Bouyer.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Manuel Bouyer
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,     
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* common functions for the siop and esiop pci front ends */
+
+/* structure describing each chip */
+struct siop_product_desc {
+	u_int32_t product;
+	int	revision;
+	const char *name;
+	int	features; /* features are defined in siopvar.h */
+	u_int8_t maxburst;
+	u_int8_t maxoff;  /* maximum supported offset */
+	u_int8_t clock_div; /* clock divider to use for async. logic */
+	u_int8_t clock_period; /* clock period (ns * 10) */
+	int 	ram_size; /* size of RAM, if appropriate */
+};
+
+const struct siop_product_desc * siop_lookup_product __P((u_int32_t, int));
+
+/* Driver internal state */
+struct siop_pci_softc {
+	struct siop_softc siop;
+	pci_chipset_tag_t	sc_pc;	/* PCI registers info */
+	pcitag_t		sc_tag;
+	void			*sc_ih;	/* PCI interrupt handle */
+	const struct siop_product_desc *sc_pp; /* Adapter description */
+};
+
+int siop_pci_attach_common __P((struct siop_pci_softc *,
+	struct pci_attach_args *));
+void siop_pci_reset __P((struct siop_softc *));