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authorPatrick Wildt <patrick@cvs.openbsd.org>2020-10-12 17:38:29 +0000
committerPatrick Wildt <patrick@cvs.openbsd.org>2020-10-12 17:38:29 +0000
commitdfc60b52a9f6d5d90a1a2633ec4739ed5b7ac1ec (patch)
tree56a7a8fdc3b398bec9ca61d160ec9b2e692964b8
parentf09c1f3dd3c5149bd5743eb2eda537b4c2dda85c (diff)
Add support for the i.MX8M AHB clocks. These behave just like all the
other composite clocks. With this we can get the frequency for the OCOTP.
-rw-r--r--sys/dev/fdt/imxccm.c68
1 files changed, 67 insertions, 1 deletions
diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index beb246ea022..91301606e86 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.21 2020/04/28 19:26:45 patrick Exp $ */
+/* $OpenBSD: imxccm.c,v 1.22 2020/10/12 17:38:28 patrick Exp $ */
/*
* Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
*
@@ -244,11 +244,13 @@ uint32_t imxccm_get_ipgclk(struct imxccm_softc *);
uint32_t imxccm_get_ipg_perclk(struct imxccm_softc *);
uint32_t imxccm_get_uartclk(struct imxccm_softc *);
uint32_t imxccm_imx8mm_enet(struct imxccm_softc *sc, uint32_t);
+uint32_t imxccm_imx8mm_ahb(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mm_i2c(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mm_uart(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mm_usdhc(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t);
+uint32_t imxccm_imx8mq_ahb(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mq_i2c(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mq_pwm(struct imxccm_softc *sc, uint32_t);
uint32_t imxccm_imx8mq_uart(struct imxccm_softc *sc, uint32_t);
@@ -775,6 +777,35 @@ imxccm_imx8mm_enet(struct imxccm_softc *sc, uint32_t idx)
}
uint32_t
+imxccm_imx8mm_ahb(struct imxccm_softc *sc, uint32_t idx)
+{
+ uint32_t mux;
+
+ if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+ return 0;
+
+ mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+ mux >>= sc->sc_muxs[idx].shift;
+ mux &= sc->sc_muxs[idx].mask;
+
+ switch (mux) {
+ case 0:
+ return clock_get_frequency(sc->sc_node, "osc_24m");
+ case 1:
+ return 133 * 1000 * 1000; /* sys_pll1_133m */
+ case 2:
+ return 800 * 1000 * 1000; /* sys_pll1_800m */
+ case 3:
+ return 400 * 1000 * 1000; /* sys_pll1_400m */
+ case 4:
+ return 125 * 1000 * 1000; /* sys_pll2_125m */
+ default:
+ printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+ return 0;
+ }
+}
+
+uint32_t
imxccm_imx8mm_i2c(struct imxccm_softc *sc, uint32_t idx)
{
uint32_t mux;
@@ -886,6 +917,35 @@ imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t idx)
}
uint32_t
+imxccm_imx8mq_ahb(struct imxccm_softc *sc, uint32_t idx)
+{
+ uint32_t mux;
+
+ if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+ return 0;
+
+ mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+ mux >>= sc->sc_muxs[idx].shift;
+ mux &= sc->sc_muxs[idx].mask;
+
+ switch (mux) {
+ case 0:
+ return clock_get_frequency(sc->sc_node, "osc_25m");
+ case 1:
+ return 133 * 1000 * 1000; /* sys1_pll_133m */
+ case 2:
+ return 800 * 1000 * 1000; /* sys1_pll_800m */
+ case 3:
+ return 400 * 1000 * 1000; /* sys1_pll_400m */
+ case 4:
+ return 125 * 1000 * 1000; /* sys2_pll_125m */
+ default:
+ printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+ return 0;
+ }
+}
+
+uint32_t
imxccm_imx8mq_i2c(struct imxccm_softc *sc, uint32_t idx)
{
uint32_t mux;
@@ -1387,6 +1447,9 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
case IMX8MM_CLK_ENET_AXI:
freq = imxccm_imx8mm_enet(sc, idx);
break;
+ case IMX8MM_CLK_AHB:
+ freq = imxccm_imx8mm_ahb(sc, idx);
+ break;
case IMX8MM_CLK_I2C1:
case IMX8MM_CLK_I2C2:
case IMX8MM_CLK_I2C3:
@@ -1433,6 +1496,9 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
case IMX8MQ_CLK_ENET_AXI:
freq = imxccm_imx8mq_enet(sc, idx);
break;
+ case IMX8MQ_CLK_AHB:
+ freq = imxccm_imx8mq_ahb(sc, idx);
+ break;
case IMX8MQ_CLK_I2C1:
case IMX8MQ_CLK_I2C2:
case IMX8MQ_CLK_I2C3: