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authorJonathan Gray <jsg@cvs.openbsd.org>2024-02-06 03:21:46 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2024-02-06 03:21:46 +0000
commite149a971c2673bffc0fa12bfbc103352211f6f9e (patch)
treed6546191fe7c66605e27b2a00f5c917ce76fd3c1
parentd5307b141fcfae519f18c28285c24712c997aeda (diff)
drm/amd/display: For prefetch mode > 0, extend prefetch if possible
From Alvin Lee 6750d1de747f4d2db0046a25b069e15341f6a9ba in linux-6.6.y/6.6.16 dd4e4bb28843393065eed279e869fac248d03f0f in mainline linux
-rw-r--r--sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c3
-rw-r--r--sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c33
-rw-r--r--sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h1
3 files changed, 31 insertions, 6 deletions
diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index cbdfb762c10..6c84b0fa40f 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -813,6 +813,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||
v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?
mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+ mode_lib->vba.PrefetchModePerState[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false,
+
/* Output */
&v->DSTXAfterScaler[k],
&v->DSTYAfterScaler[k],
@@ -3317,6 +3319,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
v->SwathHeightCThisState[k], v->TWait,
(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?
mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
+ mode_lib->vba.PrefetchModePerState[i][j] > 0 || mode_lib->vba.DRAMClockChangeRequirementFinal == false,
/* Output */
&v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.DSTXAfterScaler[k],
diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index ecea008f19d..208b89d13d3 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -3423,6 +3423,7 @@ bool dml32_CalculatePrefetchSchedule(
unsigned int SwathHeightC,
double TWait,
double TPreReq,
+ bool ExtendPrefetchIfPossible,
/* Output */
double *DSTXAfterScaler,
double *DSTYAfterScaler,
@@ -3892,12 +3893,32 @@ bool dml32_CalculatePrefetchSchedule(
/* Clamp to oto for bandwidth calculation */
LinesForPrefetchBandwidth = dst_y_prefetch_oto;
} else {
- *DestinationLinesForPrefetch = dst_y_prefetch_equ;
- TimeForFetchingMetaPTE = Tvm_equ;
- TimeForFetchingRowInVBlank = Tr0_equ;
- *PrefetchBandwidth = prefetch_bw_equ;
- /* Clamp to equ for bandwidth calculation */
- LinesForPrefetchBandwidth = dst_y_prefetch_equ;
+ /* For mode programming we want to extend the prefetch as much as possible
+ * (up to oto, or as long as we can for equ) if we're not already applying
+ * the 60us prefetch requirement. This is to avoid intermittent underflow
+ * issues during prefetch.
+ *
+ * The prefetch extension is applied under the following scenarios:
+ * 1. We're in prefetch mode > 0 (i.e. we don't support MCLK switch in blank)
+ * 2. We're using subvp or drr methods of p-state switch, in which case we
+ * we don't care if prefetch takes up more of the blanking time
+ *
+ * Mode programming typically chooses the smallest prefetch time possible
+ * (i.e. highest bandwidth during prefetch) presumably to create margin between
+ * p-states / c-states that happen in vblank and prefetch. Therefore we only
+ * apply this prefetch extension when p-state in vblank is not required (UCLK
+ * p-states take up the most vblank time).
+ */
+ if (ExtendPrefetchIfPossible && TPreReq == 0 && VStartup < MaxVStartup) {
+ MyError = true;
+ } else {
+ *DestinationLinesForPrefetch = dst_y_prefetch_equ;
+ TimeForFetchingMetaPTE = Tvm_equ;
+ TimeForFetchingRowInVBlank = Tr0_equ;
+ *PrefetchBandwidth = prefetch_bw_equ;
+ /* Clamp to equ for bandwidth calculation */
+ LinesForPrefetchBandwidth = dst_y_prefetch_equ;
+ }
}
*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
diff --git a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
index 592d174df6c..5d34735df83 100644
--- a/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
+++ b/sys/dev/pci/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h
@@ -747,6 +747,7 @@ bool dml32_CalculatePrefetchSchedule(
unsigned int SwathHeightC,
double TWait,
double TPreReq,
+ bool ExtendPrefetchIfPossible,
/* Output */
double *DSTXAfterScaler,
double *DSTYAfterScaler,