6 files changed, 5444 insertions, 0 deletions

diff --git a/gnu/usr.bin/gcc/config/m32r/initfini.c b/gnu/usr.bin/gcc/config/m32r/initfini.c
new file mode 100644
index 00000000000..34ef5da962f
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/m32r/initfini.c
@@ -0,0 +1,169 @@
+/* .init/.fini section handling + C++ global constructor/destructor handling.
+   This file is based on crtstuff.c, sol2-crti.asm, sol2-crtn.asm.
+
+Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this file with files
+   compiled with GCC to produce an executable, this does not cause
+   the resulting executable to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.  */
+
+/*  Declare a pointer to void function type.  */
+typedef void (*func_ptr) (void);
+
+#ifdef CRT_INIT
+
+/* NOTE:  In order to be able to support SVR4 shared libraries, we arrange
+   to have one set of symbols { __CTOR_LIST__, __DTOR_LIST__, __CTOR_END__,
+   __DTOR_END__ } per root executable and also one set of these symbols
+   per shared library.  So in any given whole process image, we may have
+   multiple definitions of each of these symbols.  In order to prevent
+   these definitions from conflicting with one another, and in order to
+   ensure that the proper lists are used for the initialization/finalization
+   of each individual shared library (respectively), we give these symbols
+   only internal (i.e. `static') linkage, and we also make it a point to
+   refer to only the __CTOR_END__ symbol in crtfini.o and the __DTOR_LIST__
+   symbol in crtinit.o, where they are defined.  */
+
+static func_ptr __CTOR_LIST__[1]
+  __attribute__ ((section (".ctors")))
+     = { (func_ptr) (-1) };
+
+static func_ptr __DTOR_LIST__[1]
+  __attribute__ ((section (".dtors")))
+     = { (func_ptr) (-1) };
+
+/* Run all the global destructors on exit from the program.  */
+ 
+/* Some systems place the number of pointers in the first word of the
+   table.  On SVR4 however, that word is -1.  In all cases, the table is
+   null-terminated.  On SVR4, we start from the beginning of the list and
+   invoke each per-compilation-unit destructor routine in order
+   until we find that null.
+
+   Note that this function MUST be static.  There will be one of these
+   functions in each root executable and one in each shared library, but
+   although they all have the same code, each one is unique in that it
+   refers to one particular associated `__DTOR_LIST__' which belongs to the
+   same particular root executable or shared library file.  */
+
+static void __do_global_dtors ()
+asm ("__do_global_dtors") __attribute__ ((section (".text")));
+
+static void
+__do_global_dtors ()
+{
+  func_ptr *p;
+
+  for (p = __DTOR_LIST__ + 1; *p; p++)
+    (*p) ();
+}
+
+/* .init section start.
+   This must appear at the start of the .init section.  */
+
+asm ("
+	.section .init,\"ax\",@progbits
+	.balign 4
+	.global __init
+__init:
+	push fp
+	push lr
+	mv fp,sp
+	ld24 r0,#__fini
+	bl atexit
+	.fillinsn
+");
+
+/* .fini section start.
+   This must appear at the start of the .init section.  */
+
+asm ("
+	.section .fini,\"ax\",@progbits
+	.balign 4
+	.global __fini
+__fini:
+	push fp
+	push lr
+	mv fp,sp
+	bl __do_global_dtors
+	.fillinsn
+");
+
+#endif /* CRT_INIT */
+
+#ifdef CRT_FINI
+
+/* Put a word containing zero at the end of each of our two lists of function
+   addresses.  Note that the words defined here go into the .ctors and .dtors
+   sections of the crtend.o file, and since that file is always linked in
+   last, these words naturally end up at the very ends of the two lists
+   contained in these two sections.  */
+
+static func_ptr __CTOR_END__[1]
+  __attribute__ ((section (".ctors")))
+     = { (func_ptr) 0 };
+
+static func_ptr __DTOR_END__[1]
+  __attribute__ ((section (".dtors")))
+     = { (func_ptr) 0 };
+
+/* Run all global constructors for the program.
+   Note that they are run in reverse order.  */
+
+static void __do_global_ctors ()
+asm ("__do_global_ctors") __attribute__ ((section (".text")));
+
+static void
+__do_global_ctors ()
+{
+  func_ptr *p;
+
+  for (p = __CTOR_END__ - 1; *p != (func_ptr) -1; p--)
+    (*p) ();
+}
+
+/* .init section end.
+   This must live at the end of the .init section.  */
+
+asm ("
+	.section .init,\"ax\",@progbits
+	bl __do_global_ctors
+	mv sp,fp
+	pop lr
+	pop fp
+	jmp lr
+	.fillinsn
+");
+
+/* .fini section end.
+   This must live at the end of the .fini section.  */
+
+asm ("
+	.section .fini,\"ax\",@progbits
+	mv sp,fp
+	pop lr
+	pop fp
+	jmp lr
+	.fillinsn
+");
+
+#endif /* CRT_FINI */
diff --git a/gnu/usr.bin/gcc/config/m32r/m32r.c b/gnu/usr.bin/gcc/config/m32r/m32r.c
new file mode 100644
index 00000000000..48504a06e14
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/m32r/m32r.c
@@ -0,0 +1,1835 @@
+/* Subroutines used for code generation on the Mitsubishi M32R cpu.
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include "config.h"
+#include <stdio.h>
+#include "tree.h"
+#include "rtl.h"
+#include "regs.h"
+#include "hard-reg-set.h"
+#include "real.h"
+#include "insn-config.h"
+#include "conditions.h"
+#include "insn-flags.h"
+#include "output.h"
+#include "insn-attr.h"
+#include "flags.h"
+#include "expr.h"
+#include "recog.h"
+
+/* Save the operands last given to a compare for use when we
+   generate a scc or bcc insn.  */
+rtx m32r_compare_op0, m32r_compare_op1;
+
+/* Array of valid operand punctuation characters.  */
+char m32r_punct_chars[256];
+
+static void init_reg_tables ();
+
+/* Selected code model.  */
+char *m32r_model_string = M32R_MODEL_DEFAULT;
+enum m32r_model m32r_model;
+
+/* Selected SDA support.  */
+char *m32r_sdata_string = M32R_SDATA_DEFAULT;
+enum m32r_sdata m32r_sdata;
+
+/* Called by OVERRIDE_OPTIONS to initialize various things.  */
+
+void
+m32r_init ()
+{
+  init_reg_tables ();
+
+  /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P.  */
+  memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
+  m32r_punct_chars['#'] = 1;
+  m32r_punct_chars['@'] = 1; /* ??? no longer used */
+
+  /* Provide default value if not specified.  */
+  if (!g_switch_set)
+    g_switch_value = SDATA_DEFAULT_SIZE;
+
+  if (strcmp (m32r_model_string, "small") == 0)
+    m32r_model = M32R_MODEL_SMALL;
+  else if (strcmp (m32r_model_string, "medium") == 0)
+    m32r_model = M32R_MODEL_MEDIUM;
+  else if (strcmp (m32r_model_string, "large") == 0)
+    m32r_model = M32R_MODEL_LARGE;
+  else
+    error ("bad value (%s) for -mmodel switch", m32r_model_string);
+
+  if (strcmp (m32r_sdata_string, "none") == 0)
+    m32r_sdata = M32R_SDATA_NONE;
+  else if (strcmp (m32r_sdata_string, "sdata") == 0)
+    m32r_sdata = M32R_SDATA_SDATA;
+  else if (strcmp (m32r_sdata_string, "use") == 0)
+    m32r_sdata = M32R_SDATA_USE;
+  else
+    error ("bad value (%s) for -msdata switch", m32r_sdata_string);
+}
+
+/* Vectors to keep interesting information about registers where it can easily
+   be got.  We use to use the actual mode value as the bit number, but there
+   is (or may be) more than 32 modes now.  Instead we use two tables: one
+   indexed by hard register number, and one indexed by mode.  */
+
+/* The purpose of m32r_mode_class is to shrink the range of modes so that
+   they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
+   mapped into one m32r_mode_class mode.  */
+
+enum m32r_mode_class {
+  C_MODE,
+  S_MODE, D_MODE, T_MODE, O_MODE,
+  SF_MODE, DF_MODE, TF_MODE, OF_MODE
+};
+
+/* Modes for condition codes.  */
+#define C_MODES (1 << (int) C_MODE)
+
+/* Modes for single-word and smaller quantities.  */
+#define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
+
+/* Modes for double-word and smaller quantities.  */
+#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
+
+/* Modes for quad-word and smaller quantities.  */
+#define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
+
+/* Value is 1 if register/mode pair is acceptable on arc.  */
+
+unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
+  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
+  T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
+  S_MODES, C_MODES
+};
+
+unsigned int m32r_mode_class [NUM_MACHINE_MODES];
+
+enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
+
+static void
+init_reg_tables ()
+{
+  int i;
+
+  for (i = 0; i < NUM_MACHINE_MODES; i++)
+    {
+      switch (GET_MODE_CLASS (i))
+	{
+	case MODE_INT:
+	case MODE_PARTIAL_INT:
+	case MODE_COMPLEX_INT:
+	  if (GET_MODE_SIZE (i) <= 4)
+	    m32r_mode_class[i] = 1 << (int) S_MODE;
+	  else if (GET_MODE_SIZE (i) == 8)
+	    m32r_mode_class[i] = 1 << (int) D_MODE;
+	  else if (GET_MODE_SIZE (i) == 16)
+	    m32r_mode_class[i] = 1 << (int) T_MODE;
+	  else if (GET_MODE_SIZE (i) == 32)
+	    m32r_mode_class[i] = 1 << (int) O_MODE;
+	  else 
+	    m32r_mode_class[i] = 0;
+	  break;
+	case MODE_FLOAT:
+	case MODE_COMPLEX_FLOAT:
+	  if (GET_MODE_SIZE (i) <= 4)
+	    m32r_mode_class[i] = 1 << (int) SF_MODE;
+	  else if (GET_MODE_SIZE (i) == 8)
+	    m32r_mode_class[i] = 1 << (int) DF_MODE;
+	  else if (GET_MODE_SIZE (i) == 16)
+	    m32r_mode_class[i] = 1 << (int) TF_MODE;
+	  else if (GET_MODE_SIZE (i) == 32)
+	    m32r_mode_class[i] = 1 << (int) OF_MODE;
+	  else 
+	    m32r_mode_class[i] = 0;
+	  break;
+	case MODE_CC:
+	default:
+	  /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
+	     we must explicitly check for them here.  */
+	  if (i == (int) CCmode)
+	    m32r_mode_class[i] = 1 << (int) C_MODE;
+	  else
+	    m32r_mode_class[i] = 0;
+	  break;
+	}
+    }
+
+  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+    {
+      if (GPR_P (i))
+	m32r_regno_reg_class[i] = GENERAL_REGS;
+      else if (i == ARG_POINTER_REGNUM)
+	m32r_regno_reg_class[i] = GENERAL_REGS;
+      else
+	m32r_regno_reg_class[i] = NO_REGS;
+    }
+}
+
+/* M32R specific attribute support.
+
+   interrupt - for interrupt functions
+
+   model - select code model used to access object
+
+	small: addresses use 24 bits, use bl to make calls
+	medium: addresses use 32 bits, use bl to make calls
+	large: addresses use 32 bits, use seth/add3/jl to make calls
+
+	Grep for MODEL in m32r.h for more info.
+*/
+
+/* Return nonzero if IDENTIFIER is a valid decl attribute.  */
+
+int
+m32r_valid_machine_decl_attribute (type, attributes, identifier, args)
+     tree type;
+     tree attributes;
+     tree identifier;
+     tree args;
+{
+  static tree interrupt_ident, model_ident;
+  static tree small_ident, medium_ident, large_ident;
+
+  if (interrupt_ident == 0)
+    {
+      interrupt_ident = get_identifier ("__interrupt__");
+      model_ident = get_identifier ("__model__");
+      small_ident = get_identifier ("__small__");
+      medium_ident = get_identifier ("__medium__");
+      large_ident = get_identifier ("__large__");
+    }
+
+  if (identifier == interrupt_ident
+      && list_length (args) == 0)
+    return 1;
+
+  if (identifier == model_ident
+      && list_length (args) == 1
+      && (TREE_VALUE (args) == small_ident
+	  || TREE_VALUE (args) == medium_ident
+	  || TREE_VALUE (args) == large_ident))
+    return 1;
+
+  return 0;
+}
+
+/* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
+   and two if they are nearly compatible (which causes a warning to be
+   generated).  */
+
+int
+m32r_comp_type_attributes (type1, type2)
+     tree type1, type2;
+{
+  return 1;
+}
+
+/* Set the default attributes for TYPE.  */
+
+void
+m32r_set_default_type_attributes (type)
+     tree type;
+{
+}
+
+/* A C statement or statements to switch to the appropriate
+   section for output of DECL.  DECL is either a `VAR_DECL' node
+   or a constant of some sort.  RELOC indicates whether forming
+   the initial value of DECL requires link-time relocations.  */
+
+void
+m32r_select_section (decl, reloc)
+     tree decl;
+     int reloc;
+{
+  if (TREE_CODE (decl) == STRING_CST)
+    {
+      if (! flag_writable_strings)
+	const_section ();
+      else
+	data_section ();
+    }
+  else if (TREE_CODE (decl) == VAR_DECL)
+    {
+      if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
+	sdata_section ();
+      else if ((flag_pic && reloc)
+	       || !TREE_READONLY (decl)
+	       || TREE_SIDE_EFFECTS (decl)
+	       || !DECL_INITIAL (decl)
+	       || (DECL_INITIAL (decl) != error_mark_node
+		   && !TREE_CONSTANT (DECL_INITIAL (decl))))
+	data_section ();
+      else
+	const_section ();
+    }
+  else
+    const_section ();
+}
+
+/* Encode section information of DECL, which is either a VAR_DECL,
+   FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
+
+   For the M32R we want to record:
+
+   - whether the object lives in .sdata/.sbss.
+     objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
+
+   - what code model should be used to access the object
+     small: recorded with no flag - for space efficiency since they'll
+            be the most common
+     medium: prefixed with MEDIUM_FLAG_CHAR
+     large: prefixed with LARGE_FLAG_CHAR
+*/
+
+void
+m32r_encode_section_info (decl)
+     tree decl;
+{
+  char prefix = 0;
+  tree model = 0;
+
+  switch (TREE_CODE (decl))
+    {
+    case VAR_DECL :
+    case FUNCTION_DECL :
+      model = lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl));
+      break;
+    case STRING_CST :
+    case CONSTRUCTOR :
+      /* ??? document all others that can appear here */
+    default :
+      return;
+    }
+
+  /* Only mark the object as being small data area addressable if
+     it hasn't been explicitly marked with a code model.
+
+     The user can explicitly put an object in the small data area with the
+     section attribute.  If the object is in sdata/sbss and marked with a
+     code model do both [put the object in .sdata and mark it as being
+     addressed with a specific code model - don't mark it as being addressed
+     with an SDA reloc though].  This is ok and might be useful at times.  If
+     the object doesn't fit the linker will give an error.  */
+
+  if (! model)
+    {
+      if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
+	  && DECL_SECTION_NAME (decl) != NULL_TREE)
+	{
+	  char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
+	  if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
+	    {
+#if 0 /* ??? There's no reason to disallow this, is there?  */
+	      if (TREE_READONLY (decl))
+		error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
+#endif
+	      prefix = SDATA_FLAG_CHAR;
+	    }
+	}
+      else
+	{
+	  if (TREE_CODE (decl) == VAR_DECL
+	      && ! TREE_READONLY (decl)
+	      && ! TARGET_SDATA_NONE)
+	    {
+	      int size = int_size_in_bytes (TREE_TYPE (decl));
+
+	      if (size > 0 && size <= g_switch_value)
+		prefix = SDATA_FLAG_CHAR;
+	    }
+	}
+    }
+
+  /* If data area not decided yet, check for a code model.  */
+  if (prefix == 0)
+    {
+      if (model)
+	{
+	  if (TREE_VALUE (TREE_VALUE (model)) == get_identifier ("__small__"))
+	    ; /* don't mark the symbol specially */
+	  else if (TREE_VALUE (TREE_VALUE (model)) == get_identifier ("__medium__"))
+	    prefix = MEDIUM_FLAG_CHAR;
+	  else if (TREE_VALUE (TREE_VALUE (model)) == get_identifier ("__large__"))
+	    prefix = LARGE_FLAG_CHAR;
+	  else
+	    abort (); /* shouldn't happen */
+	}
+      else
+	{
+	  if (TARGET_MODEL_SMALL)
+	    ; /* don't mark the symbol specially */
+	  else if (TARGET_MODEL_MEDIUM)
+	    prefix = MEDIUM_FLAG_CHAR;
+	  else if (TARGET_MODEL_LARGE)
+	    prefix = LARGE_FLAG_CHAR;
+	  else
+	    abort (); /* shouldn't happen */
+	}
+    }
+
+  if (prefix != 0)
+    {
+      rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
+                 ? TREE_CST_RTL (decl) : DECL_RTL (decl));
+      char *str = XSTR (XEXP (rtl, 0), 0);
+      int len = strlen (str);
+      char *newstr = savealloc (len + 2);
+      strcpy (newstr + 1, str);
+      *newstr = prefix;
+      XSTR (XEXP (rtl, 0), 0) = newstr;
+    }
+}
+
+/* Do anything needed before RTL is emitted for each function.  */
+
+void
+m32r_init_expanders ()
+{
+  /* ??? At one point there was code here.  The function is left in
+     to make it easy to experiment.  */
+}
+
+/* Acceptable arguments to the call insn.  */
+
+int
+call_address_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return (symbolic_operand (op, mode)
+	  || (GET_CODE (op) == CONST_INT && LEGITIMATE_CONSTANT_P (op))
+	  || (GET_CODE (op) == REG));
+}
+
+int
+call_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != MEM)
+    return 0;
+  op = XEXP (op, 0);
+  return call_address_operand (op, mode);
+}
+
+/* Returns 1 if OP is a symbol reference.  */
+
+int
+symbolic_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case SYMBOL_REF:
+    case LABEL_REF:
+    case CONST :
+      return 1;
+    default:
+      return 0;
+    }
+}
+
+/* Return truth value of statement that OP is a symbolic memory
+   operand of mode MODE.  */
+
+int
+symbolic_memory_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == SUBREG)
+    op = SUBREG_REG (op);
+  if (GET_CODE (op) != MEM)
+    return 0;
+  op = XEXP (op, 0);
+  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
+	  || GET_CODE (op) == LABEL_REF);
+}
+
+/* Return 1 if OP is a reference to an object in .sdata/.sbss.  */
+
+int
+small_data_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (! TARGET_SDATA_USE)
+    return 0;
+
+  if (GET_CODE (op) == SYMBOL_REF)
+    return SDATA_NAME_P (XSTR (op, 0));
+
+  if (GET_CODE (op) == CONST
+      && GET_CODE (XEXP (op, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
+      && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
+    return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
+
+  return 0;
+}
+
+/* Return 1 if OP is a symbol that can use 24 bit addressing.  */
+
+int
+addr24_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == LABEL_REF)
+    return TARGET_ADDR24;
+
+  if (GET_CODE (op) == SYMBOL_REF)
+    return (SMALL_NAME_P (XSTR (op, 0))
+	    || (TARGET_ADDR24
+		&& (CONSTANT_POOL_ADDRESS_P (op)
+		    || LIT_NAME_P (XSTR (op, 0)))));
+
+  if (GET_CODE (op) == CONST
+      && GET_CODE (XEXP (op, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
+      && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
+    {
+      rtx sym = XEXP (XEXP (op, 0), 0);
+      return (SMALL_NAME_P (XSTR (sym, 0))
+	      || (TARGET_ADDR24
+		  && (CONSTANT_POOL_ADDRESS_P (op)
+		      || LIT_NAME_P (XSTR (op, 0)))));
+    }
+
+  return 0;
+}
+
+/* Return 1 if OP is a symbol that needs 32 bit addressing.  */
+
+int
+addr32_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == LABEL_REF)
+    return TARGET_ADDR32;
+
+  if (GET_CODE (op) == SYMBOL_REF)
+    return (! addr24_operand (op)
+	    && ! small_data_operand (op));
+
+  if (GET_CODE (op) == CONST
+      && GET_CODE (XEXP (op, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+    {
+      return (! addr24_operand (op)
+	      && ! small_data_operand (op));
+    }
+
+  return 0;
+}
+
+/* Return 1 if OP is a function that can be called with the `bl' insn.  */
+
+int
+call26_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == SYMBOL_REF)
+    return ! LARGE_NAME_P (XSTR (op, 0));
+
+  return TARGET_CALL26;
+}
+
+/* Return 1 if OP is a function that must be called with 32 bit addressing.  */
+
+int
+call32_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return ! call26_operand (op, mode);
+}
+
+/* Returns 1 if OP is an acceptable operand for seth/add3.  */
+
+int
+seth_add3_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == SYMBOL_REF
+      || GET_CODE (op) == LABEL_REF)
+    return 1;
+
+  if (GET_CODE (op) == CONST
+      && GET_CODE (XEXP (op, 0)) == PLUS
+      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
+      && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
+    return 1;
+
+  return 0;
+}
+
+/* Return true if OP is a signed 8 bit immediate value.  */
+
+int
+int8_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return INT8_P (INTVAL (op));
+}
+
+/* Return true if OP is a signed 16 bit immediate value.  */
+
+int
+int16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return INT16_P (INTVAL (op));
+}
+
+/* Return true if OP is a signed 16 bit immediate value
+   useful in comparisons.  */
+
+int
+cmp_int16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return CMP_INT16_P (INTVAL (op));
+}
+
+/* Return true if OP is an unsigned 16 bit immediate value.  */
+
+int
+uint16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return UINT16_P (INTVAL (op));
+}
+
+/* Return true if OP is an unsigned 24 bit immediate value.  */
+
+int
+uint24_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return UINT24_P (INTVAL (op));
+}
+
+/* Return true if OP is a register or signed 8 bit value.  */
+
+int
+reg_or_int8_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+    return register_operand (op, mode);
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return INT8_P (INTVAL (op));
+}
+
+/* Return true if OP is a register or signed 8 bit value.  */
+
+int
+reg_or_int16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+    return register_operand (op, mode);
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return INT16_P (INTVAL (op));
+}
+
+/* Return true if OP is a register or signed 8 bit value.  */
+
+int
+reg_or_uint16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+    return register_operand (op, mode);
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return UINT16_P (INTVAL (op));
+}
+
+/* Return true if OP is a register or signed 16 bit value for compares.  */
+
+int
+reg_or_cmp_int16_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+    return register_operand (op, mode);
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  return CMP_INT16_P (INTVAL (op));
+}
+
+/* Return true if OP is a const_int requiring two instructions to load.  */
+
+int
+two_insn_const_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  if (GET_CODE (op) != CONST_INT)
+    return 0;
+  if (INT16_P (INTVAL (op))
+      || UINT24_P (INTVAL (op))
+      || UPPER16_P (INTVAL (op)))
+    return 0;
+  return 1;
+}
+
+/* Return true if OP is an acceptable argument for a single word
+   move source.  */
+
+int
+move_src_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case SYMBOL_REF :
+    case CONST :
+      return addr24_operand (op, mode);
+    case CONST_INT :
+      /* ??? We allow more cse opportunities if we only allow constants
+	 loadable with one insn, and split the rest into two.  The instances
+	 where this would help should be rare and the current way is
+	 simpler.  */
+      return INT32_P (INTVAL (op));
+    case LABEL_REF :
+      return TARGET_ADDR24;
+    case CONST_DOUBLE :
+      if (mode == SFmode)
+	return 1;
+      else if (mode == SImode)
+	{
+	  /* Large unsigned constants are represented as const_double's.  */
+	  unsigned HOST_WIDE_INT low, high;
+
+	  low = CONST_DOUBLE_LOW (op);
+	  high = CONST_DOUBLE_HIGH (op);
+	  return high == 0 && low <= 0xffffffff;
+	}
+      else
+	return 0;
+    case REG :
+      return register_operand (op, mode);
+    case SUBREG :
+      /* (subreg (mem ...) ...) can occur here if the inner part was once a
+	 pseudo-reg and is now a stack slot.  */
+      if (GET_CODE (SUBREG_REG (op)) == MEM)
+	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
+      else
+	return register_operand (op, mode);
+    case MEM :
+      return address_operand (XEXP (op, 0), mode);
+    default :
+      return 0;
+    }
+}
+
+/* Return true if OP is an acceptable argument for a double word
+   move source.  */
+
+int
+move_double_src_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case CONST_INT :
+    case CONST_DOUBLE :
+      if (mode == DFmode)
+	return easy_df_const (op);
+      else
+	return easy_di_const (op);
+    case REG :
+      return register_operand (op, mode);
+    case SUBREG :
+      /* (subreg (mem ...) ...) can occur here if the inner part was once a
+	 pseudo-reg and is now a stack slot.  */
+      if (GET_CODE (SUBREG_REG (op)) == MEM)
+	return move_double_src_operand (SUBREG_REG (op), mode);
+      else
+	return register_operand (op, mode);
+    case MEM :
+      /* Disallow auto inc/dec for now.  */
+      if (GET_CODE (XEXP (op, 0)) == PRE_DEC
+	  || GET_CODE (XEXP (op, 0)) == PRE_INC)
+	return 0;
+      return address_operand (XEXP (op, 0), mode);
+    default :
+      return 0;
+    }
+}
+
+/* Return true if OP is an acceptable argument for a move destination.  */
+
+int
+move_dest_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  switch (GET_CODE (op))
+    {
+    case REG :
+      return register_operand (op, mode);
+    case SUBREG :
+      /* (subreg (mem ...) ...) can occur here if the inner part was once a
+	 pseudo-reg and is now a stack slot.  */
+      if (GET_CODE (SUBREG_REG (op)) == MEM)
+	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
+      else
+	return register_operand (op, mode);
+    case MEM :
+      return address_operand (XEXP (op, 0), mode);
+    default :
+      return 0;
+    }
+}
+
+/* Return 1 if OP is a DImode const we want to handle inline.
+   This must match the code in the movdi pattern.
+   It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER.  */
+
+int
+easy_di_const (op)
+     rtx op;
+{
+  rtx high_rtx, low_rtx;
+  HOST_WIDE_INT high, low;
+
+  split_double (op, &high_rtx, &low_rtx);
+  high = INTVAL (high_rtx);
+  low = INTVAL (low_rtx);
+  /* Pick constants loadable with 2 16 bit `ldi' insns.  */
+  if (high >= -128 && high <= 127
+      && low >= -128 && low <= 127)
+    return 1;
+  return 0;
+}
+
+/* Return 1 if OP is a DFmode const we want to handle inline.
+   This must match the code in the movdf pattern.
+   It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER.  */
+
+int
+easy_df_const (op)
+     rtx op;
+{
+  REAL_VALUE_TYPE r;
+  long l[2];
+
+  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
+  REAL_VALUE_TO_TARGET_DOUBLE (r, l);
+  if (l[0] == 0 && l[1] == 0)
+    return 1;
+  if ((l[0] & 0xffff) == 0 && l[1] == 0)
+    return 1;
+  return 0;
+}
+
+/* Return 1 if OP is an EQ or NE comparison operator.  */
+
+int
+eqne_comparison_operator (op, mode)
+    rtx op;
+    enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (op);
+
+  if (GET_RTX_CLASS (code) != '<')
+    return 0;
+  return (code == EQ || code == NE);
+}
+
+/* Return 1 if OP is a signed comparison operator.  */
+
+int
+signed_comparison_operator (op, mode)
+    rtx op;
+    enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (op);
+
+  if (GET_RTX_CLASS (code) != '<')
+    return 0;
+  return (code == EQ || code == NE
+	  || code == LT || code == LE || code == GT || code == GE);
+}
+
+/* Return 1 if OP is (mem (reg ...)).
+   This is used in insn length calcs.  */
+
+int
+memreg_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
+}
+
+/* Comparisons.  */
+
+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
+   return the mode to be used for the comparison.  */
+
+enum machine_mode
+m32r_select_cc_mode (op, x, y)
+     enum rtx_code op;
+     rtx x, y;
+{
+  return CCmode;
+}
+
+/* X and Y are two things to compare using CODE.  Emit the compare insn and
+   return the rtx for compare [arg0 of the if_then_else].  */
+
+rtx
+gen_compare (code, x, y)
+     enum rtx_code code;
+     rtx x, y;
+{
+  enum machine_mode mode = SELECT_CC_MODE (code, x, y);
+  enum rtx_code compare_code, branch_code;
+  rtx cc_reg = gen_rtx (REG, mode, CARRY_REGNUM);
+  int swap_p = 0;
+
+  switch (code)
+    {
+    case EQ: compare_code = EQ; branch_code = NE; break;
+    case NE: compare_code = EQ; branch_code = EQ; break;
+    case LT: compare_code = LT; branch_code = NE; break;
+    case LE: compare_code = LT; branch_code = EQ; swap_p = 1; break;
+    case GT: compare_code = LT; branch_code = NE; swap_p = 1; break;
+    case GE: compare_code = LT; branch_code = EQ; break;
+    case LTU: compare_code = LTU; branch_code = NE; break;
+    case LEU: compare_code = LTU; branch_code = EQ; swap_p = 1; break;
+    case GTU: compare_code = LTU; branch_code = NE; swap_p = 1; break;
+    case GEU: compare_code = LTU; branch_code = EQ; break;
+    }
+
+  if (! TARGET_OLD_COMPARE)
+    {
+      /* reg/reg equal comparison */
+      if (compare_code == EQ
+	  && register_operand (y, SImode))
+	return gen_rtx (code, mode, x, y);
+      /* reg/zero signed comparison */
+      if ((compare_code == EQ || compare_code == LT)
+	  && y == const0_rtx)
+	return gen_rtx (code, mode, x, y);
+      /* reg/smallconst equal comparison */
+      if (compare_code == EQ
+	  && GET_CODE (y) == CONST_INT
+	  && CMP_INT16_P (INTVAL (y)))
+	{
+	  rtx tmp = gen_reg_rtx (SImode);
+	  emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
+	  return gen_rtx (code, mode, tmp, const0_rtx);
+	}
+      /* reg/const equal comparison */
+      if (compare_code == EQ
+	  && CONSTANT_P (y))
+	{
+	  rtx tmp = force_reg (GET_MODE (x), y);
+	  return gen_rtx (code, mode, x, tmp);
+	}
+    }
+
+  if (swap_p && CONSTANT_P (y))
+    y = force_reg (GET_MODE (x), y);
+  else if (CONSTANT_P (y))
+    {
+      int ok_const_p =
+	(code == LTU || code == LEU || code == GTU || code == GEU)
+	  ? uint16_operand (y, GET_MODE (y))
+	  : reg_or_cmp_int16_operand (y, GET_MODE (y));
+      if (! ok_const_p)
+	y = force_reg (GET_MODE (x), y);
+    }
+
+  switch (compare_code)
+    {
+    case EQ :
+      emit_insn (gen_cmp_eqsi_insn (swap_p ? y : x, swap_p ? x : y));
+      break;
+    case LT :
+      emit_insn (gen_cmp_ltsi_insn (swap_p ? y : x, swap_p ? x : y));
+      break;
+    case LTU :
+      emit_insn (gen_cmp_ltusi_insn (swap_p ? y : x, swap_p ? x : y));
+      break;
+    }
+
+  return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
+}
+
+/* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.  */
+
+int
+function_arg_partial_nregs (cum, mode, type, named)
+     CUMULATIVE_ARGS *cum;
+     enum machine_mode mode;
+     tree type;
+     int named;
+{
+  int ret;
+  int size = (((mode == BLKmode && type)
+	       ? int_size_in_bytes (type)
+	       : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
+
+  if (*cum >= M32R_MAX_PARM_REGS)
+    ret = 0;
+  else if (*cum + size > M32R_MAX_PARM_REGS)
+    ret = (*cum + size) - M32R_MAX_PARM_REGS;
+  else
+    ret = 0;
+
+  return ret;
+}
+
+/* Do any needed setup for a variadic function.  For the M32R, we must
+   create a register parameter block, and then copy any anonymous arguments
+   in registers to memory.
+
+   CUM has not been updated for the last named argument which has type TYPE
+   and mode MODE, and we rely on this fact.  */
+
+void
+m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
+     CUMULATIVE_ARGS *cum;
+     enum machine_mode mode;
+     tree type;
+     int *pretend_size;
+     int no_rtl;
+{
+  int first_anon_arg;
+
+  if (no_rtl)
+    return;
+
+  /* All BLKmode values are passed by reference.  */
+  if (mode == BLKmode)
+    abort ();
+
+  /* We must treat `__builtin_va_alist' as an anonymous arg.  */
+  if (current_function_varargs)
+    first_anon_arg = *cum;
+  else
+    first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
+		      + ROUND_ADVANCE_ARG (mode, type));
+
+  if (first_anon_arg < M32R_MAX_PARM_REGS)
+    {
+      /* Note that first_reg_offset < M32R_MAX_PARM_REGS.  */
+      int first_reg_offset = first_anon_arg;
+      /* Size in words to "pretend" allocate.  */
+      int size = M32R_MAX_PARM_REGS - first_reg_offset;
+      rtx regblock;
+
+      regblock = gen_rtx (MEM, BLKmode,
+			  plus_constant (arg_pointer_rtx,
+					 FIRST_PARM_OFFSET (0)));
+      move_block_from_reg (first_reg_offset, regblock,
+			   size, size * UNITS_PER_WORD);
+
+      *pretend_size = (size * UNITS_PER_WORD);
+    }
+}
+
+/* Cost functions.  */
+
+/* Provide the costs of an addressing mode that contains ADDR.
+   If ADDR is not a valid address, its cost is irrelevant.
+
+   This function is trivial at the moment.  This code doesn't live
+   in m32r.h so it's easy to experiment.  */
+
+int
+m32r_address_cost (addr)
+     rtx addr;
+{
+  return 1;
+}
+
+/* Type of function DECL.
+
+   The result is cached.  To reset the cache at the end of a function,
+   call with DECL = NULL_TREE.  */
+
+enum m32r_function_type
+m32r_compute_function_type (decl)
+     tree decl;
+{
+  /* Cached value.  */
+  static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
+  /* Last function we were called for.  */
+  static tree last_fn = NULL_TREE;
+
+  /* Resetting the cached value?  */
+  if (decl == NULL_TREE)
+    {
+      fn_type = M32R_FUNCTION_UNKNOWN;
+      last_fn = NULL_TREE;
+      return fn_type;
+    }
+
+  if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
+    return fn_type;
+
+  /* Compute function type.  */
+  fn_type = (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl)) != NULL_TREE
+	     ? M32R_FUNCTION_INTERRUPT
+	     : M32R_FUNCTION_NORMAL);
+
+  last_fn = decl;
+  return fn_type;
+}
+/* Function prologue/epilogue handlers.  */
+
+/* M32R stack frames look like:
+
+             Before call                       After call
+        +-----------------------+       +-----------------------+
+        |                       |       |                       |
+   high |  local variables,     |       |  local variables,     |
+   mem  |  reg save area, etc.  |       |  reg save area, etc.  |
+        |                       |       |                       |
+        +-----------------------+       +-----------------------+
+        |                       |       |                       |
+        |  arguments on stack.  |       |  arguments on stack.  |
+        |                       |       |                       |
+  SP+0->+-----------------------+       +-----------------------+
+                                        |  reg parm save area,  |
+                                        |  only created for     |    
+                                        |  variable argument    |    
+                                        |  functions            |    
+					+-----------------------+
+                                        |   previous frame ptr  |
+                                        +-----------------------+    
+                                        |                       |    
+                                        |  register save area   |    
+                                        |                       |    
+					+-----------------------+
+                                        |    return address     |    
+                                        +-----------------------+    
+                                        |                       |    
+                                        |  local variables      |    
+                                        |                       |    
+                                        +-----------------------+    
+                                        |                       |    
+                                        |  alloca allocations   |    
+                                        |                       |    
+                                        +-----------------------+    
+                                        |                       |    
+   low                                  |  arguments on stack   |    
+   memory                               |                       |    
+                                  SP+0->+-----------------------+    
+
+Notes:
+1) The "reg parm save area" does not exist for non variable argument fns.
+2) The "reg parm save area" can be eliminated completely if we saved regs
+   containing anonymous args separately but that complicates things too
+   much (so it's not done).
+3) The return address is saved after the register save area so as to have as
+   many insns as possible between the restoration of `lr' and the `jmp lr'.
+*/
+
+/* Structure to be filled in by m32r_compute_frame_size with register
+   save masks, and offsets for the current function.  */
+struct m32r_frame_info
+{
+  unsigned int total_size;	/* # bytes that the entire frame takes up */
+  unsigned int extra_size;	/* # bytes of extra stuff */
+  unsigned int pretend_size;	/* # bytes we push and pretend caller did */
+  unsigned int args_size;	/* # bytes that outgoing arguments take up */
+  unsigned int reg_size;	/* # bytes needed to store regs */
+  unsigned int var_size;	/* # bytes that variables take up */
+  unsigned int gmask;		/* mask of saved gp registers */
+  unsigned int save_fp;		/* nonzero if fp must be saved */
+  unsigned int save_lr;		/* nonzero if lr (return addr) must be saved */
+  int          initialized;	/* nonzero if frame size already calculated */
+};
+
+/* Current frame information calculated by m32r_compute_frame_size.  */
+static struct m32r_frame_info current_frame_info;
+
+/* Zero structure to initialize current_frame_info.  */
+static struct m32r_frame_info zero_frame_info;
+
+#define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
+#define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
+
+/* Tell prologue and epilogue if register REGNO should be saved / restored.
+   The return address and frame pointer are treated separately.
+   Don't consider them here.  */
+#define MUST_SAVE_REGISTER(regno, interrupt_p) \
+((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
+ && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
+
+#define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
+#define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM])
+
+/* Return the bytes needed to compute the frame pointer from the current
+   stack pointer.
+
+   SIZE is the size needed for local variables.  */
+
+unsigned int
+m32r_compute_frame_size (size)
+     int size;			/* # of var. bytes allocated.  */
+{
+  int regno;
+  unsigned int total_size, var_size, args_size, pretend_size, extra_size;
+  unsigned int reg_size;
+  unsigned int gmask;
+  enum m32r_function_type fn_type;
+  int interrupt_p;
+
+  var_size	= M32R_STACK_ALIGN (size);
+  args_size	= M32R_STACK_ALIGN (current_function_outgoing_args_size);
+  pretend_size	= current_function_pretend_args_size;
+  extra_size	= FIRST_PARM_OFFSET (0);
+  total_size	= extra_size + pretend_size + args_size + var_size;
+  reg_size	= 0;
+  gmask		= 0;
+
+  /* See if this is an interrupt handler.  Call used registers must be saved
+     for them too.  */
+  fn_type = m32r_compute_function_type (current_function_decl);
+  interrupt_p = M32R_INTERRUPT_P (fn_type);
+
+  /* Calculate space needed for registers.  */
+
+  for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
+    {
+      if (MUST_SAVE_REGISTER (regno, interrupt_p))
+	{
+	  reg_size += UNITS_PER_WORD;
+	  gmask |= 1 << regno;
+	}
+    }
+
+  current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
+  current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
+
+  reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
+	       * UNITS_PER_WORD);
+  total_size += reg_size;
+
+  /* ??? Not sure this is necessary, and I don't think the epilogue
+     handler will do the right thing if this changes total_size.  */
+  total_size = M32R_STACK_ALIGN (total_size);
+
+  /* Save computed information.  */
+  current_frame_info.total_size   = total_size;
+  current_frame_info.extra_size   = extra_size;
+  current_frame_info.pretend_size = pretend_size;
+  current_frame_info.var_size     = var_size;
+  current_frame_info.args_size    = args_size;
+  current_frame_info.reg_size	  = reg_size;
+  current_frame_info.gmask	  = gmask;
+  current_frame_info.initialized  = reload_completed;
+
+  /* Ok, we're done.  */
+  return total_size;
+}
+
+/* Set up the stack and frame pointer (if desired) for the function.  */
+
+void
+m32r_output_function_prologue (file, size)
+     FILE *file;
+     int size;
+{
+  int regno;
+  int total_size, frame_size;
+  char *sp_str = reg_names[STACK_POINTER_REGNUM];
+  char *fp_str = reg_names[FRAME_POINTER_REGNUM];
+  unsigned int gmask = current_frame_info.gmask;
+  enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
+
+  /* If this is an interrupt handler, mark it as such.  */
+  if (M32R_INTERRUPT_P (fn_type))
+    {
+      fprintf (file, "\t%s interrupt handler\n",
+	       ASM_COMMENT_START);
+    }
+
+  /* This is only for the human reader.  */
+  fprintf (file, "\t%s BEGIN PROLOGUE %s vars= %d, regs= %d, args= %d, extra= %d\n",
+	   ASM_COMMENT_START, ASM_COMMENT_START,
+	   current_frame_info.var_size,
+	   current_frame_info.reg_size / 4,
+	   current_frame_info.args_size,
+	   current_frame_info.extra_size);
+
+  total_size = (! current_frame_info.initialized
+		? m32r_compute_frame_size (size)
+		: current_frame_info.total_size);
+
+  /* These cases shouldn't happen.  Catch them now.  */
+  if (total_size == 0 && gmask)
+    abort ();
+
+#if 1
+  /* Allocate space for register arguments if this is a variadic function.  */
+  if (current_frame_info.pretend_size != 0)
+    fprintf (file, "\taddi %s,%s%d\n",
+	     sp_str, IMMEDIATE_PREFIX,
+	     -current_frame_info.pretend_size);
+#else
+  /* If there are unnamed args in registers, save them.  */
+  if (current_function_stdarg || current_function_varargs)
+    {
+      int i;
+      fprintf (file, "\taddi %s,%s%d\n",
+	       sp_str, IMMEDIATE_PREFIX,
+	       - M32R_MAX_PARM_REGS * UNITS_PER_WORD);
+      for (i = 0; i < M32R_MAX_PARM_REGS; ++i)
+	fprintf (file, "\tst %s,@(sp,%d)\n",
+		 reg_names[i], i * UNITS_PER_WORD);
+    }
+#endif
+
+  /* Save any registers we need to and set up fp.  */
+
+  if (current_frame_info.save_fp)
+    fprintf (file, "\tpush %s\n", fp_str);
+
+  gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
+
+  /* Save any needed call-saved regs (and call-used if this is an
+     interrupt handler).  */
+  for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
+    {
+      if ((gmask & (1 << regno)) != 0)
+	fprintf (file, "\tpush %s\n", reg_names[regno]);
+    }
+
+  if (current_frame_info.save_lr)
+    fprintf (file, "\tpush %s\n", reg_names[RETURN_ADDR_REGNUM]);
+
+  /* Allocate the stack frame.  */
+  frame_size = total_size - (current_frame_info.pretend_size
+			     + current_frame_info.reg_size);
+  if (frame_size == 0)
+    ; /* nothing to do */
+  else if (frame_size <= 128)
+    fprintf (file, "\taddi %s,%s%d\n",
+	     sp_str, IMMEDIATE_PREFIX, -frame_size);
+  else if (frame_size <= 32768)
+    fprintf (file, "\tadd3 %s,%s,%s%d\n",
+	     sp_str, sp_str, IMMEDIATE_PREFIX, -frame_size);
+  else
+    fprintf (file, "\tld24 %s,%s%d\n\tsub %s,%s\n",
+	     reg_names[PROLOGUE_TMP_REGNUM],
+	     IMMEDIATE_PREFIX, frame_size,
+	     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
+
+  if (frame_pointer_needed)
+    fprintf (file, "\tmv %s,%s\n", fp_str, sp_str);
+
+  fprintf (file, "\t%s END PROLOGUE\n", ASM_COMMENT_START);
+}
+
+/* Do any necessary cleanup after a function to restore stack, frame,
+   and regs. */
+
+void
+m32r_output_function_epilogue (file, size)
+     FILE *file;
+     int size;
+{
+  int regno;
+  int noepilogue = FALSE;
+  int total_size;
+  enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
+
+  /* This is only for the human reader.  */
+  fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
+
+  if (!current_frame_info.initialized)
+    abort ();
+  total_size = current_frame_info.total_size;
+
+  if (total_size == 0)
+    {
+      rtx insn = get_last_insn ();
+
+      /* If the last insn was a BARRIER, we don't have to write any code
+	 because a jump (aka return) was put there.  */
+      if (GET_CODE (insn) == NOTE)
+	insn = prev_nonnote_insn (insn);
+      if (insn && GET_CODE (insn) == BARRIER)
+	noepilogue = TRUE;
+    }
+
+  if (!noepilogue)
+    {
+      unsigned int pretend_size = current_frame_info.pretend_size;
+      unsigned int frame_size = total_size - pretend_size;
+      unsigned int var_size = current_frame_info.var_size;
+      unsigned int args_size = current_frame_info.args_size;
+      unsigned int gmask = current_frame_info.gmask;
+      int can_trust_sp_p = !current_function_calls_alloca;
+      char *sp_str = reg_names[STACK_POINTER_REGNUM];
+      char *fp_str = reg_names[FRAME_POINTER_REGNUM];
+
+      /* The first thing to do is point the sp at the bottom of the register
+	 save area.  */
+      if (can_trust_sp_p)
+	{
+	  unsigned int reg_offset = var_size + args_size;
+	  if (reg_offset == 0)
+	    ; /* nothing to do */
+	  else if (reg_offset < 128)
+	    fprintf (file, "\taddi %s,%s%d\n",
+		     sp_str, IMMEDIATE_PREFIX, reg_offset);
+	  else if (reg_offset < 32768)
+	    fprintf (file, "\tadd3 %s,%s,%s%d\n",
+		     sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
+	  else
+	    fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
+		     reg_names[PROLOGUE_TMP_REGNUM],
+		     IMMEDIATE_PREFIX, reg_offset,
+		     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
+	}
+      else if (frame_pointer_needed)
+	{
+	  unsigned int reg_offset = var_size + args_size;
+	  if (reg_offset == 0)
+	    fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
+	  else if (reg_offset < 32768)
+	    fprintf (file, "\tadd3 %s,%s,%s%d\n",
+		     sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
+	  else
+	    fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
+		     reg_names[PROLOGUE_TMP_REGNUM],
+		     IMMEDIATE_PREFIX, reg_offset,
+		     sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
+	}
+      else
+	abort ();
+
+      if (current_frame_info.save_lr)
+	fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
+
+      /* Restore any saved registers, in reverse order of course.  */
+      gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
+      for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
+	{
+	  if ((gmask & (1L << regno)) != 0)
+	    fprintf (file, "\tpop %s\n", reg_names[regno]);
+	}
+
+      if (current_frame_info.save_fp)
+	fprintf (file, "\tpop %s\n", fp_str);
+
+      /* Remove varargs area if present.  */
+      if (current_frame_info.pretend_size != 0)
+	fprintf (file, "\taddi %s,%s%d\n",
+		 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
+	
+      /* Emit the return instruction.  */
+      if (M32R_INTERRUPT_P (fn_type))
+	fprintf (file, "\trte\n");
+      else
+	fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
+    }
+
+#if 0 /* no longer needed */
+  /* Ensure the function cleanly ends on a 32 bit boundary.  */
+  fprintf (file, "\t.fillinsn\n");
+#endif
+
+  /* Reset state info for each function.  */
+  current_frame_info = zero_frame_info;
+  m32r_compute_function_type (NULL_TREE);
+}
+
+/* PIC */
+
+/* Emit special PIC prologues and epilogues.  */
+
+void
+m32r_finalize_pic ()
+{
+  /* nothing to do */
+}
+
+/* Nested function support.  */
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.  */
+
+void
+m32r_initialize_trampoline (tramp, fnaddr, cxt)
+     rtx tramp, fnaddr, cxt;
+{
+}
+
+/* Set the cpu type and print out other fancy things,
+   at the top of the file.  */
+
+void
+m32r_asm_file_start (file)
+     FILE *file;
+{
+  if (flag_verbose_asm)
+    fprintf (file, "%s M32R/D special options: -G %d\n",
+	     ASM_COMMENT_START, g_switch_value);
+}
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
+
+void
+m32r_print_operand (file, x, code)
+     FILE *file;
+     rtx x;
+     int code;
+{
+  switch (code)
+    {
+    case 'R' :
+      /* Write second word of DImode or DFmode reference,
+	 register or memory.  */
+      if (GET_CODE (x) == REG)
+	fputs (reg_names[REGNO (x)+1], file);
+      else if (GET_CODE (x) == MEM)
+	{
+	  fprintf (file, "@(");
+	  /* Handle possible auto-increment.  Since it is pre-increment and
+	     we have already done it, we can just use an offset of four.  */
+	  /* ??? This is taken from rs6000.c I think.  I don't think it is
+	     currently necessary, but keep it around.  */
+	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
+	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
+	    output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
+	  else
+	    output_address (plus_constant (XEXP (x, 0), 4));
+	  fputc (')', file);
+	}
+      else
+	output_operand_lossage ("invalid operand to %R code");
+      return;
+
+    case 'H' : /* High word */
+    case 'L' : /* Low word */
+      if (GET_CODE (x) == REG)
+	{
+	  /* L = least significant word, H = most significant word */
+	  if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
+	    fputs (reg_names[REGNO (x)], file);
+	  else
+	    fputs (reg_names[REGNO (x)+1], file);
+	}
+      else if (GET_CODE (x) == CONST_INT
+	       || GET_CODE (x) == CONST_DOUBLE)
+	{
+	  rtx first, second;
+
+	  split_double (x, &first, &second);
+	  fprintf (file, "0x%08lx",
+		   code == 'L' ? INTVAL (first) : INTVAL (second));
+	}
+      else
+	output_operand_lossage ("invalid operand to %H/%L code");
+      return;
+
+    case 'A' :
+      {
+	REAL_VALUE_TYPE d;
+	char str[30];
+
+	if (GET_CODE (x) != CONST_DOUBLE
+	    || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
+	  abort ();
+	REAL_VALUE_FROM_CONST_DOUBLE (d, x);
+	REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
+	fprintf (file, "%s", str);
+	return;
+      }
+
+    case 'B' : /* Bottom half */
+    case 'T' : /* Top half */
+      /* Output the argument to a `seth' insn (sets the Top half-word).
+	 For constants output arguments to a seth/or3 pair to set Top and
+	 Bottom halves.  For symbols output arguments to a seth/add3 pair to
+	 set Top and Bottom halves.  The difference exists because for
+	 constants seth/or3 is more readable but for symbols we need to use
+	 the same scheme as `ld' and `st' insns (16 bit addend is signed).  */
+      switch (GET_CODE (x))
+	{
+	case CONST_INT :
+	case CONST_DOUBLE :
+	  {
+	    rtx first, second;
+
+	    split_double (x, &first, &second);
+	    x = WORDS_BIG_ENDIAN ? second : first;
+	    fprintf (file,
+#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
+		     "0x%x",
+#else
+		     "0x%lx",
+#endif
+		     (code == 'B'
+		      ? INTVAL (x) & 0xffff
+		      : (INTVAL (x) >> 16) & 0xffff));
+	  }
+	  return;
+	case CONST :
+	case SYMBOL_REF :
+	  if (code == 'B'
+	      && small_data_operand (x, VOIDmode))
+	    {
+	      fputs ("sda(", file);
+	      output_addr_const (file, x);
+	      fputc (')', file);
+	      return;
+	    }
+	  /* fall through */
+	case LABEL_REF :
+	  fputs (code == 'T' ? "shigh(" : "low(", file);
+	  output_addr_const (file, x);
+	  fputc (')', file);
+	  return;
+	default :
+	  output_operand_lossage ("invalid operand to %T/%B code");
+	  return;
+	}
+      break;
+
+    case 'U' :
+      /* ??? wip */
+      /* Output a load/store with update indicator if appropriate.  */
+      if (GET_CODE (x) == MEM)
+	{
+	  if (GET_CODE (XEXP (x, 0)) == PRE_INC
+	      || GET_CODE (XEXP (x, 0)) == PRE_DEC)
+	    fputs (".a", file);
+	}
+      else
+	output_operand_lossage ("invalid operand to %U code");
+      return;
+
+    case 'N' :
+      /* Print a constant value negated.  */
+      if (GET_CODE (x) == CONST_INT)
+	output_addr_const (file, GEN_INT (- INTVAL (x)));
+      else
+	output_operand_lossage ("invalid operand to %N code");
+      return;
+
+    case 'X' :
+      /* Print a const_int in hex.  Used in comments.  */
+      if (GET_CODE (x) == CONST_INT)
+	fprintf (file,
+#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
+		 "0x%x",
+#else
+		 "0x%lx",
+#endif
+		 INTVAL (x));
+      return;
+
+    case '#' :
+      fputs (IMMEDIATE_PREFIX, file);
+      return;
+
+#if 0 /* ??? no longer used */
+    case '@' :
+      fputs (reg_names[SDA_REGNUM], file);
+      return;
+#endif
+
+    case 0 :
+      /* Do nothing special.  */
+      break;
+
+    default :
+      /* Unknown flag.  */
+      output_operand_lossage ("invalid operand output code");
+    }
+
+  switch (GET_CODE (x))
+    {
+    case REG :
+      fputs (reg_names[REGNO (x)], file);
+      break;
+
+    case MEM :
+      fprintf (file, "@(");
+      if (GET_CODE (XEXP (x, 0)) == PRE_INC)
+	output_address (plus_constant (XEXP (XEXP (x, 0), 0),
+				       GET_MODE_SIZE (GET_MODE (x))));
+      else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
+	output_address (plus_constant (XEXP (XEXP (x, 0), 0),
+				       - GET_MODE_SIZE (GET_MODE (x))));
+      else
+	output_address (XEXP (x, 0));
+      fputc (')', file);
+      break;
+
+    case CONST_DOUBLE :
+      /* We handle SFmode constants here as output_addr_const doesn't.  */
+      if (GET_MODE (x) == SFmode)
+	{
+	  REAL_VALUE_TYPE d;
+	  long l;
+
+	  REAL_VALUE_FROM_CONST_DOUBLE (d, x);
+	  REAL_VALUE_TO_TARGET_SINGLE (d, l);
+	  fprintf (file, "0x%08lx", l);
+	  break;
+	}
+
+      /* Fall through.  Let output_addr_const deal with it.  */
+
+    default :
+      output_addr_const (file, x);
+      break;
+    }
+}
+
+/* Print a memory address as an operand to reference that memory location.  */
+
+void
+m32r_print_operand_address (file, addr)
+     FILE *file;
+     rtx addr;
+{
+  register rtx base, index = 0;
+  int offset = 0;
+
+  switch (GET_CODE (addr))
+    {
+    case REG :
+      fputs (reg_names[REGNO (addr)], file);
+      break;
+
+    case PLUS :
+      if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
+	offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
+      else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+	offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
+      else
+	base = XEXP (addr, 0), index = XEXP (addr, 1);
+      if (GET_CODE (base) == REG)
+	{
+	  /* Print the offset first (if present) to conform to the manual.  */
+	  if (index == 0)
+	    {
+	      if (offset != 0)
+		fprintf (file, "%d,", offset);
+	      fputs (reg_names[REGNO (base)], file);
+	    }
+	  /* The chip doesn't support this, but left in for generality.  */
+	  else if (GET_CODE (index) == REG)
+	    fprintf (file, "%s,%s",
+		     reg_names[REGNO (base)], reg_names[REGNO (index)]);
+	  /* Not sure this can happen, but leave in for now.  */
+	  else if (GET_CODE (index) == SYMBOL_REF)
+	    {
+	      output_addr_const (file, index);
+	      fputc (',', file);
+	      fputs (reg_names[REGNO (base)], file);
+	    }
+	  else
+	    abort ();
+	}
+      else if (GET_CODE (base) == LO_SUM)
+	{
+	  if (index != 0
+	      || GET_CODE (XEXP (base, 0)) != REG)
+	    abort ();
+	  if (small_data_operand (XEXP (base, 1), VOIDmode))
+	    fputs ("sda(", file);
+	  else
+	    fputs ("low(", file);
+	  output_addr_const (file, plus_constant (XEXP (base, 1), offset));
+	  fputs ("),", file);
+	  fputs (reg_names[REGNO (XEXP (base, 0))], file);
+	}
+      else
+	abort ();
+      break;
+
+    case LO_SUM :
+      if (GET_CODE (XEXP (addr, 0)) != REG)
+	abort ();
+      if (small_data_operand (XEXP (addr, 1), VOIDmode))
+	fputs ("sda(", file);
+      else
+	fputs ("low(", file);
+      output_addr_const (file, XEXP (addr, 1));
+      fputs ("),", file);
+      fputs (reg_names[REGNO (XEXP (addr, 0))], file);
+      break;
+
+    case PRE_INC :
+    case PRE_DEC :
+      /* We shouldn't get here as we've lost the mode of the memory object
+	 (which says how much to inc/dec by).  */
+      abort ();
+      break;
+
+    default :
+      output_addr_const (file, addr);
+      break;
+    }
+}
diff --git a/gnu/usr.bin/gcc/config/m32r/m32r.h b/gnu/usr.bin/gcc/config/m32r/m32r.h
new file mode 100644
index 00000000000..99ab9c2281c
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/m32r/m32r.h
@@ -0,0 +1,1867 @@
+/* Definitions of target machine for GNU compiler, Mitsubishi M32R cpu.
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Things to do:
+- longlong.h?
+*/
+
+/* ??? Create elf.h and have svr4.h include it.  */
+#include "svr4.h"
+
+#undef SWITCH_TAKES_ARG
+#undef WORD_SWITCH_TAKES_ARG
+#undef HANDLE_SYSV_PRAGMA
+#undef SIZE_TYPE
+#undef PTRDIFF_TYPE
+#undef WCHAR_TYPE
+#undef WCHAR_TYPE_SIZE
+#undef ASM_FILE_START
+#undef ASM_OUTPUT_EXTERNAL_LIBCALL
+
+/* Print subsidiary information on the compiler version in use.  */
+#define TARGET_VERSION fprintf (stderr, " (m32r)")
+
+/* Switch  Recognition by gcc.c.  Add -G xx support */
+
+#undef SWITCH_TAKES_ARG
+#define SWITCH_TAKES_ARG(CHAR) \
+(DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
+
+/* Names to predefine in the preprocessor for this target machine.  */
+/* __M32R__ is defined by the existing compiler so we use that.  */
+#define CPP_PREDEFINES "-Acpu(m32r) -Amachine(m32r) -D__M32R__"
+
+/* Additional flags for the preprocessor.  */
+#define CPP_SPEC ""
+
+#define CC1_SPEC "%{G*}"
+
+#undef ASM_SPEC
+#if 0 /* not supported yet */
+#define ASM_SPEC "%{v} %{mrelax:-relax}"
+#else
+#define ASM_SPEC "%{v}"
+#endif
+
+#undef ASM_FINAL_SPEC
+
+#undef LINK_SPEC
+#if 0 /* not supported yet */
+#define LINK_SPEC "%{v} %{mrelax:-relax}"
+#else
+#define LINK_SPEC "%{v}"
+#endif
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "%{!shared:crt0.o%s crtsysc.o%s} crtinit.o%s"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC "crtfini.o%s"
+
+#undef LIB_SPEC
+
+/* Run-time compilation parameters selecting different hardware subsets.  */
+
+extern int target_flags;
+
+/* If non-zero, tell the linker to do relaxing.
+   We don't do anything with the option, other than recognize it.
+   LINK_SPEC handles passing -relax to the linker.
+   This can cause incorrect debugging information as line numbers may
+   turn out wrong.  This shouldn't be specified unless accompanied with -O2
+   [where the user expects debugging information to be less accurate].  */
+#define TARGET_RELAX_MASK 1
+
+/* For miscellaneous debugging purposes.  */
+#define TARGET_DEBUG_MASK 2
+#define TARGET_DEBUG (target_flags & TARGET_DEBUG_MASK)
+
+/* Align loops to 32 byte boundaries (cache line size).  */
+/* ??? This option is experimental and is not documented.  */
+#define TARGET_ALIGN_LOOPS_MASK 4
+#define TARGET_ALIGN_LOOPS (target_flags & TARGET_ALIGN_LOOPS_MASK)
+
+/* Use old compare/branch support (kept around for awhile for
+   comparison and backoff purposes).  */
+/* ??? This option is experimental and is not documented.
+   Eventually it will be deleted.  */
+#define TARGET_OLD_COMPARE_MASK 8
+#define TARGET_OLD_COMPARE (target_flags & TARGET_OLD_COMPARE_MASK)
+
+/* Macro to define tables used to set the flags.
+   This is a list in braces of pairs in braces,
+   each pair being { "NAME", VALUE }
+   where VALUE is the bits to set or minus the bits to clear.
+   An empty string NAME is used to identify the default VALUE.  */
+
+#define TARGET_SWITCHES \
+{ \
+/*  { "relax",			TARGET_RELAX_MASK },			\
+    { "no-relax",		-TARGET_RELAX_MASK },*/			\
+    { "debug",			TARGET_DEBUG_MASK },			\
+    { "align-loops",		TARGET_ALIGN_LOOPS_MASK },		\
+    { "no-align-loops",		-TARGET_ALIGN_LOOPS_MASK },		\
+    { "old-compare",		TARGET_OLD_COMPARE_MASK },		\
+    { "no-old-compare",		-TARGET_OLD_COMPARE_MASK },		\
+    SUBTARGET_SWITCHES							\
+    { "", TARGET_DEFAULT }						\
+}
+
+#define TARGET_DEFAULT (0)
+
+#define SUBTARGET_SWITCHES
+
+/* This macro is similar to `TARGET_SWITCHES' but defines names of
+   command options that have values.  Its definition is an
+   initializer with a subgrouping for each command option.
+
+   Each subgrouping contains a string constant, that defines the
+   fixed part of the option name, and the address of a variable. 
+   The variable, type `char *', is set to the variable part of the
+   given option if the fixed part matches.  The actual option name
+   is made by appending `-m' to the specified name.
+
+   Here is an example which defines `-mshort-data-NUMBER'.  If the
+   given option is `-mshort-data-512', the variable `m88k_short_data'
+   will be set to the string `"512"'.
+
+	extern char *m88k_short_data;
+	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
+
+extern char *m32r_model_string;
+extern char *m32r_sdata_string;
+#define TARGET_OPTIONS \
+{						\
+  { "model=",	&m32r_model_string	},	\
+  { "sdata=",	&m32r_sdata_string	},	\
+}
+
+/* Code Models
+
+   Code models are used to select between two choices of two separate
+   possibilities (address space size, call insn to use):
+
+   small: addresses use 24 bits, use bl to make calls
+   medium: addresses use 32 bits, use bl to make calls (*1)
+   large: addresses use 32 bits, use seth/add3/jl to make calls (*2)
+
+   The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but
+   using this one doesn't make much sense.
+
+   (*1) The linker may eventually be able to relax seth/add3 -> ld24.
+   (*2) The linker may eventually be able to relax seth/add3/jl -> bl.
+
+   Internally these are recorded as TARGET_ADDR{24,32} and
+   TARGET_CALL{26,32}.
+
+   The __model__ attribute can be used to select the code model to use when
+   accessing particular objects.  */
+
+enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE };
+
+extern enum m32r_model m32r_model;
+#define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL)
+#define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM)
+#define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE)
+#define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL)
+#define TARGET_ADDR32 (! TARGET_ADDR24)
+#define TARGET_CALL26 (! TARGET_CALL32)
+#define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE)
+
+/* The default is the small model.  */
+#define M32R_MODEL_DEFAULT "small"
+
+/* Small Data Area
+
+   The SDA consists of sections .sdata, .sbss, and .scommon.
+   .scommon isn't a real section, symbols in it have their section index
+   set to SHN_M32R_SCOMMON, though support for it exists in the linker script.
+
+   Two switches control the SDA:
+
+   -G NNN        - specifies the maximum size of variable to go in the SDA
+
+   -msdata=foo   - specifies how such variables are handled
+
+        -msdata=none  - small data area is disabled
+
+        -msdata=sdata - small data goes in the SDA, special code isn't
+                        generated to use it, and special relocs aren't
+                        generated
+
+        -msdata=use   - small data goes in the SDA, special code is generated
+                        to use the SDA and special relocs are generated
+
+   The SDA is not multilib'd, it isn't necessary.
+   MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd
+   libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use
+   -msdata=use will successfully link with them (references in header files
+   will cause the compiler to emit code that refers to library objects in
+   .data).  ??? There can be a problem if the user passes a -G value greater
+   than the default and a library object in a header file is that size.
+   The default is 8 so this should be rare - if it occurs the user
+   is required to rebuild the libraries or use a smaller value for -G.
+*/
+
+/* Maximum size of variables that go in .sdata/.sbss.
+   The -msdata=foo switch also controls how small variables are handled.  */
+#define SDATA_DEFAULT_SIZE 8
+
+extern int g_switch_value;		/* value of the -G xx switch */
+extern int g_switch_set;		/* whether -G xx was passed.  */
+
+enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE };
+
+extern enum m32r_sdata m32r_sdata;
+#define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE)
+#define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA)
+#define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE)
+
+/* Default is to disable the SDA
+   [for upward compatibility with previous toolchains].  */
+#define M32R_SDATA_DEFAULT "none"
+
+/* Define this macro as a C expression for the initializer of an array of
+   string to tell the driver program which options are defaults for this
+   target and thus do not need to be handled specially when using
+   `MULTILIB_OPTIONS'.  */
+#define MULTILIB_DEFAULTS { "mmodel=small" }
+
+/* Sometimes certain combinations of command options do not make
+   sense on a particular target machine.  You can define a macro
+   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
+   defined, is executed once just after all the command options have
+   been parsed.
+
+   Don't use this macro to turn on various extra optimizations for
+   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
+
+extern void m32r_init ();
+
+#define OVERRIDE_OPTIONS \
+do {				\
+  /* These need to be done at start up.  It's convenient to do them here.  */ \
+  m32r_init ();			\
+} while (0)
+
+/* Define this macro if debugging can be performed even without a
+   frame pointer.  If this macro is defined, GNU CC will turn on the
+   `-fomit-frame-pointer' option whenever `-O' is specified.  */
+#define CAN_DEBUG_WITHOUT_FP
+
+/* Target machine storage layout.  */
+
+/* Define to use software floating point emulator for REAL_ARITHMETIC and
+   decimal <-> binary conversion.  */
+#define REAL_ARITHMETIC
+
+/* Define this if most significant bit is lowest numbered
+   in instructions that operate on numbered bit-fields.  */
+#define BITS_BIG_ENDIAN 1
+
+/* Define this if most significant byte of a word is the lowest numbered.  */
+#define BYTES_BIG_ENDIAN 1
+
+/* Define this if most significant word of a multiword number is the lowest
+   numbered.  */
+#define WORDS_BIG_ENDIAN 1
+
+/* Define this macro if WORDS_BIG_ENDIAN is not constant.  This must
+   be a constant value with the same meaning as WORDS_BIG_ENDIAN,
+   which will be used only when compiling libgcc2.c.  Typically the
+   value will be set based on preprocessor defines.  */
+/*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/
+
+/* Number of bits in an addressable storage unit.  */
+#define BITS_PER_UNIT 8
+
+/* Width in bits of a "word", which is the contents of a machine register.
+   Note that this is not necessarily the width of data type `int';
+   if using 16-bit ints on a 68000, this would still be 32.
+   But on a machine with 16-bit registers, this would be 16.  */
+#define BITS_PER_WORD 32
+
+/* Width of a word, in units (bytes).  */
+#define UNITS_PER_WORD 4
+
+/* Define this macro if it is advisable to hold scalars in registers
+   in a wider mode than that declared by the program.  In such cases, 
+   the value is constrained to be within the bounds of the declared
+   type, but kept valid in the wider mode.  The signedness of the
+   extension may differ from that of the type.  */
+#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
+if (GET_MODE_CLASS (MODE) == MODE_INT		\
+    && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)	\
+{						\
+  (MODE) = SImode;				\
+}
+
+/* Define this macro if the promotion described by `PROMOTE_MODE'
+   should also be done for outgoing function arguments.  */
+/*#define PROMOTE_FUNCTION_ARGS*/
+
+/* Likewise, if the function return value is promoted.
+   If defined, FUNCTION_VALUE must perform the same promotions done by
+   PROMOTE_MODE.  */
+/*#define PROMOTE_FUNCTION_RETURN*/
+
+/* Width in bits of a pointer.
+   See also the macro `Pmode' defined below.  */
+#define POINTER_SIZE 32
+
+/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
+#define PARM_BOUNDARY 32
+
+/* Boundary (in *bits*) on which stack pointer should be aligned.  */
+#define STACK_BOUNDARY 32
+
+/* ALIGN FRAMES on word boundaries */
+#define M32R_STACK_ALIGN(LOC) (((LOC)+3) & ~3)
+
+/* Allocation boundary (in *bits*) for the code of a function.  */
+#define FUNCTION_BOUNDARY 32
+
+/* Alignment of field after `int : 0' in a structure.  */
+#define EMPTY_FIELD_BOUNDARY 32
+
+/* Every structure's size must be a multiple of this.  */
+#define STRUCTURE_SIZE_BOUNDARY 8
+
+/* A bitfield declared as `int' forces `int' alignment for the struct.  */
+#define PCC_BITFIELD_TYPE_MATTERS 1
+
+/* No data type wants to be aligned rounder than this.  */
+#define BIGGEST_ALIGNMENT 32
+
+/* The best alignment to use in cases where we have a choice.  */
+#define FASTEST_ALIGNMENT 32
+
+/* Make strings word-aligned so strcpy from constants will be faster.  */
+#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
+  ((TREE_CODE (EXP) == STRING_CST	\
+    && (ALIGN) < FASTEST_ALIGNMENT)	\
+   ? FASTEST_ALIGNMENT : (ALIGN))
+
+/* Make arrays of chars word-aligned for the same reasons.  */
+#define DATA_ALIGNMENT(TYPE, ALIGN)		\
+  (TREE_CODE (TYPE) == ARRAY_TYPE		\
+   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
+   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
+
+/* Set this nonzero if move instructions will actually fail to work
+   when given unaligned data.  */
+#define STRICT_ALIGNMENT 1
+
+/* Layout of source language data types.  */
+
+#define SHORT_TYPE_SIZE		16
+#define INT_TYPE_SIZE		32
+#define LONG_TYPE_SIZE		32
+#define LONG_LONG_TYPE_SIZE	64
+#define FLOAT_TYPE_SIZE		32
+#define DOUBLE_TYPE_SIZE	64
+#define LONG_DOUBLE_TYPE_SIZE	64
+
+/* Define this as 1 if `char' should by default be signed; else as 0.  */
+#define DEFAULT_SIGNED_CHAR 1
+
+#define SIZE_TYPE "long unsigned int"
+#define PTRDIFF_TYPE "long int"
+#define WCHAR_TYPE "short unsigned int"
+#define WCHAR_TYPE_SIZE 16
+
+/* Define results of standard character escape sequences.  */
+#define TARGET_BELL 007
+#define TARGET_BS 010
+#define TARGET_TAB 011
+#define TARGET_NEWLINE 012
+#define TARGET_VT 013
+#define TARGET_FF 014
+#define TARGET_CR 015
+
+/* Standard register usage.  */
+
+/* Number of actual hardware registers.
+   The hardware registers are assigned numbers for the compiler
+   from 0 to just below FIRST_PSEUDO_REGISTER.
+   All registers that the compiler knows about must be given numbers,
+   even those that are not normally considered general registers.  */
+#define FIRST_PSEUDO_REGISTER 18
+
+/* 1 for registers that have pervasive standard uses
+   and are not available for the register allocator.
+
+   0-3   - arguments/results
+   4-5   - call used [4 is used as a tmp during prologue/epilogue generation]
+   6     - call used, gptmp
+   7     - call used, static chain pointer
+   8-11  - call saved
+   12    - call saved [reserved for global pointer]
+   13    - frame pointer
+   14    - subroutine link register
+   15    - stack pointer
+   16    - arg pointer
+   17    - carry flag
+
+   By default, the extension registers are not available.  */
+
+#define FIXED_REGISTERS \
+{ 0, 0, 0, 0, 0, 0, 0, 0,	\
+  0, 0, 0, 0, 0, 0, 0, 1,	\
+  1, 0 }
+
+/* 1 for registers not available across function calls.
+   These must include the FIXED_REGISTERS and also any
+   registers that can be used without being saved.
+   The latter must include the registers where values are returned
+   and the register where structure-value addresses are passed.
+   Aside from that, you can include as many other registers as you like.  */
+
+#define CALL_USED_REGISTERS \
+{ 1, 1, 1, 1, 1, 1, 1, 1,	\
+  0, 0, 0, 0, 0, 0, 1, 1,	\
+  1, 1 }
+
+/* Zero or more C statements that may conditionally modify two variables
+   `fixed_regs' and `call_used_regs' (both of type `char []') after they
+   have been initialized from the two preceding macros.
+
+   This is necessary in case the fixed or call-clobbered registers depend
+   on target flags.
+
+   You need not define this macro if it has no work to do.  */
+
+/*#define CONDITIONAL_REGISTER_USAGE*/
+
+/* If defined, an initializer for a vector of integers, containing the
+   numbers of hard registers in the order in which GNU CC should
+   prefer to use them (from most preferred to least).  */
+#if 1 /* better for int code */
+#define REG_ALLOC_ORDER \
+{ 4, 5, 6, 7, 2, 3, 8, 9, 10, 11, 12, 13, 14, 0, 1, 15, 16, 17 }
+#else /* better for fp code at expense of int code */
+#define REG_ALLOC_ORDER \
+{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 }
+#endif
+
+/* Return number of consecutive hard regs needed starting at reg REGNO
+   to hold something of mode MODE.
+   This is ordinarily the length in words of a value of mode MODE
+   but can be less for certain modes in special long registers.  */
+#define HARD_REGNO_NREGS(REGNO, MODE) \
+((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.  */
+extern unsigned int m32r_hard_regno_mode_ok[];
+extern unsigned int m32r_mode_class[];
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0)
+
+/* A C expression that is nonzero if it is desirable to choose
+   register allocation so as to avoid move instructions between a
+   value of mode MODE1 and a value of mode MODE2.
+
+   If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
+   MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
+   MODE2)' must be zero.  */
+
+/* Tie QI/HI/SI modes together.  */
+#define MODES_TIEABLE_P(MODE1, MODE2) \
+(GET_MODE_CLASS (MODE1) == MODE_INT		\
+ && GET_MODE_CLASS (MODE2) == MODE_INT		\
+ && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD	\
+ && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
+
+/* Register classes and constants.  */
+
+/* Define the classes of registers for register constraints in the
+   machine description.  Also define ranges of constants.
+
+   One of the classes must always be named ALL_REGS and include all hard regs.
+   If there is more than one class, another class must be named NO_REGS
+   and contain no registers.
+
+   The name GENERAL_REGS must be the name of a class (or an alias for
+   another name such as ALL_REGS).  This is the class of registers
+   that is allowed by "g" or "r" in a register constraint.
+   Also, registers outside this class are allocated only when
+   instructions express preferences for them.
+
+   The classes must be numbered in nondecreasing order; that is,
+   a larger-numbered class must never be contained completely
+   in a smaller-numbered class.
+
+   For any two classes, it is very desirable that there be another
+   class that represents their union.
+
+   It is important that any condition codes have class NO_REGS.
+   See `register_operand'.  */
+
+enum reg_class {
+  NO_REGS, CARRY_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
+};
+
+#define N_REG_CLASSES (int) LIM_REG_CLASSES
+
+/* Give names of register classes as strings for dump file.   */
+#define REG_CLASS_NAMES \
+{ "NO_REGS", "CARRY_REG", "GENERAL_REGS", "ALL_REGS" }
+
+/* Define which registers fit in which classes.
+   This is an initializer for a vector of HARD_REG_SET
+   of length N_REG_CLASSES.  */
+
+#define REG_CLASS_CONTENTS \
+{ {0}, {0x20000}, {0x1ffff}, {0x3ffff} }
+
+/* The same information, inverted:
+   Return the class number of the smallest class containing
+   reg number REGNO.  This could be a conditional expression
+   or could index an array.  */
+extern enum reg_class m32r_regno_reg_class[];
+#define REGNO_REG_CLASS(REGNO) \
+(m32r_regno_reg_class[REGNO])
+
+/* The class value for index registers, and the one for base regs.  */
+#define INDEX_REG_CLASS GENERAL_REGS
+#define BASE_REG_CLASS GENERAL_REGS
+
+/* Get reg_class from a letter such as appears in the machine description.  */
+#define REG_CLASS_FROM_LETTER(C) NO_REGS
+
+/* These assume that REGNO is a hard or pseudo reg number.
+   They give nonzero only if REGNO is a hard reg of the suitable class
+   or a pseudo reg currently allocated to a suitable hard reg.
+   Since they use reg_renumber, they are safe only once reg_renumber
+   has been allocated, which happens in local-alloc.c.  */
+#define REGNO_OK_FOR_BASE_P(REGNO) \
+((REGNO) < FIRST_PSEUDO_REGISTER			\
+ ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM	\
+ : GPR_P (reg_renumber[REGNO]))
+#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
+
+/* Given an rtx X being reloaded into a reg required to be
+   in class CLASS, return the class of reg to actually use.
+   In general this is just CLASS; but on some machines
+   in some cases it is preferable to use a more restrictive class.  */
+#define PREFERRED_RELOAD_CLASS(X,CLASS) \
+(CLASS)
+
+/* Return the maximum number of consecutive registers
+   needed to represent mode MODE in a register of class CLASS.  */
+#define CLASS_MAX_NREGS(CLASS, MODE) \
+((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* The letters I, J, K, L, M, N, O, P in a register constraint string
+   can be used to stand for particular ranges of immediate operands.
+   This macro defines what the ranges are.
+   C is the letter, and VALUE is a constant value.
+   Return 1 if VALUE is in the range specified by C.  */
+/* 'I' is used for 8 bit signed immediates.
+   'J' is used for 16 bit signed immediates.
+   'K' is used for 16 bit unsigned immediates.
+   'L' is used for 16 bit immediates left shifted by 16 (sign ???).
+   'M' is used for 24 bit unsigned immediates.
+   'N' is used for any 32 bit non-symbolic value.
+   'O' is used for 5 bit unsigned immediates (shift count).
+   'P' is used for 16 bit signed immediates for compares
+       (values in the range -32767 to +32768).  */
+
+/* local to this file */
+#define INT8_P(X) ((unsigned) ((X) + 0x80) < 0x100)
+#define INT16_P(X) ((unsigned) ((X) + 0x8000) < 0x10000)
+#define CMP_INT16_P(X) ((unsigned) ((X) - 1 + 0x8000) < 0x10000)
+#define UINT16_P(X) ((unsigned) (X) < 0x10000)
+#define UPPER16_P(X) (((X) & ~0xffff0000) == 0)
+#define UINT24_P(X) ((unsigned) (X) < 0x1000000)
+#define INT32_P(X) ((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
+		    && (X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
+#define UINT5_P(X) ((unsigned) (X) < 32)
+
+#define CONST_OK_FOR_LETTER_P(VALUE, C) \
+((C) == 'I' ? INT8_P (VALUE)		\
+ : (C) == 'J' ? INT16_P (VALUE)	\
+ : (C) == 'K' ? UINT16_P (VALUE)	\
+ : (C) == 'L' ? UPPER16_P (VALUE)	\
+ : (C) == 'M' ? UINT24_P (VALUE)	\
+ : (C) == 'N' ? INT32_P (VALUE)		\
+ : (C) == 'O' ? UINT5_P (VALUE)		\
+ : (C) == 'P' ? CMP_INT16_P (VALUE)	\
+ : 0)
+
+/* Similar, but for floating constants, and defining letters G and H.
+   Here VALUE is the CONST_DOUBLE rtx itself.
+   For the m32r, handle a few constants inline.
+   ??? We needn't treat DI and DF modes differently, but for now we do.  */
+#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
+((C) == 'G' ? easy_di_const (VALUE) \
+ : (C) == 'H' ? easy_df_const (VALUE) \
+ : 0)
+
+/* A C expression that defines the optional machine-dependent constraint
+   letters that can be used to segregate specific types of operands,
+   usually memory references, for the target machine.  It should return 1 if
+   VALUE corresponds to the operand type represented by the constraint letter
+   C.  If C is not defined as an extra constraint, the value returned should
+   be 0 regardless of VALUE.  */
+/* Q is for symbolic addresses loadable with ld24.
+   R is for symbolic addresses when ld24 can't be used.  */
+#define EXTRA_CONSTRAINT(VALUE, C) \
+((C) == 'Q' \
+ ? ((TARGET_ADDR24 && GET_CODE (VALUE) == LABEL_REF) \
+    || addr24_operand (VALUE, VOIDmode)) \
+ : (C) == 'R' \
+ ? ((TARGET_ADDR32 && GET_CODE (VALUE) == LABEL_REF) \
+    || addr32_operand (VALUE, VOIDmode)) \
+ : 0)
+
+/* Stack layout and stack pointer usage.  */
+
+/* Define this macro if pushing a word onto the stack moves the stack
+   pointer to a smaller address.  */
+#define STACK_GROWS_DOWNWARD
+
+/* Define this if the nominal address of the stack frame
+   is at the high-address end of the local variables;
+   that is, each additional local variable allocated
+   goes at a more negative offset from the frame pointer.  */
+/*#define FRAME_GROWS_DOWNWARD*/
+
+/* Offset from frame pointer to start allocating local variables at.
+   If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
+   first local allocated.  Otherwise, it is the offset to the BEGINNING
+   of the first local allocated.  */
+/* The frame pointer points at the same place as the stack pointer, except if
+   alloca has been called.  */
+#define STARTING_FRAME_OFFSET \
+M32R_STACK_ALIGN (current_function_outgoing_args_size)
+
+/* Offset from the stack pointer register to the first location at which
+   outgoing arguments are placed.  */
+#define STACK_POINTER_OFFSET 0
+
+/* Offset of first parameter from the argument pointer register value.  */
+#define FIRST_PARM_OFFSET(FNDECL) 0
+
+/* A C expression whose value is RTL representing the address in a
+   stack frame where the pointer to the caller's frame is stored.
+   Assume that FRAMEADDR is an RTL expression for the address of the
+   stack frame itself.
+
+   If you don't define this macro, the default is to return the value
+   of FRAMEADDR--that is, the stack frame address is also the address
+   of the stack word that points to the previous frame.  */
+/*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
+
+/* A C expression whose value is RTL representing the value of the
+   return address for the frame COUNT steps up from the current frame.
+   FRAMEADDR is the frame pointer of the COUNT frame, or the frame
+   pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
+   is defined.  */
+/* The current return address is in r14.  */
+#if 0 /* The default value should work.  */
+#define RETURN_ADDR_RTX(COUNT, FRAME) \
+(((COUNT) == -1)				\
+ ? gen_rtx (REG, Pmode, 14)			\
+ : copy_to_reg (gen_rtx (MEM, Pmode,		\
+			 memory_address (Pmode, plus_constant ((FRAME), UNITS_PER_WORD)))))
+#endif
+
+/* Register to use for pushing function arguments.  */
+#define STACK_POINTER_REGNUM 15
+
+/* Base register for access to local variables of the function.  */
+#define FRAME_POINTER_REGNUM 13
+
+/* Base register for access to arguments of the function.  */
+#define ARG_POINTER_REGNUM 16
+
+/* The register number of the return address pointer register, which
+   is used to access the current function's return address from the
+   stack.  On some machines, the return address is not at a fixed
+   offset from the frame pointer or stack pointer or argument
+   pointer.  This register can be defined to point to the return
+   address on the stack, and then be converted by `ELIMINABLE_REGS'
+   into either the frame pointer or stack pointer.
+
+   Do not define this macro unless there is no other way to get the
+   return address from the stack.  */
+/* ??? revisit */
+/* #define RETURN_ADDRESS_POINTER_REGNUM */
+
+/* Register in which static-chain is passed to a function.  This must
+   not be a register used by the prologue.  */
+#define STATIC_CHAIN_REGNUM 7
+
+/* These aren't official macros.  */
+#define PROLOGUE_TMP_REGNUM 4
+#define RETURN_ADDR_REGNUM 14
+/* #define GP_REGNUM 12 */
+#define CARRY_REGNUM 17
+#define M32R_MAX_INT_REGS 16
+
+#define GPR_P(REGNO) ((unsigned) (REGNO) < M32R_MAX_INT_REGS)
+
+/* Eliminating the frame and arg pointers.  */
+
+/* A C expression which is nonzero if a function must have and use a
+   frame pointer.  This expression is evaluated in the reload pass.
+   If its value is nonzero the function will have a frame pointer.  */
+#define FRAME_POINTER_REQUIRED \
+(current_function_calls_alloca)
+
+#if 0
+/* C statement to store the difference between the frame pointer
+   and the stack pointer values immediately after the function prologue.
+   If `ELIMINABLE_REGS' is defined, this macro will be not be used and
+   need not be defined.  */
+#define INITIAL_FRAME_POINTER_OFFSET(VAR) \
+((VAR) = m32r_compute_frame_size (get_frame_size ()))
+#endif
+
+/* If defined, this macro specifies a table of register pairs used to
+   eliminate unneeded registers that point into the stack frame.  If
+   it is not defined, the only elimination attempted by the compiler
+   is to replace references to the frame pointer with references to
+   the stack pointer.
+
+   Note that the elimination of the argument pointer with the stack
+   pointer is specified first since that is the preferred elimination.  */
+
+#define ELIMINABLE_REGS \
+{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },			\
+ { ARG_POINTER_REGNUM,	 STACK_POINTER_REGNUM },			\
+ { ARG_POINTER_REGNUM,   FRAME_POINTER_REGNUM }}			\
+
+/* A C expression that returns non-zero if the compiler is allowed to
+   try to replace register number FROM-REG with register number
+   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
+   defined, and will usually be the constant 1, since most of the
+   cases preventing register elimination are things that the compiler
+   already knows about.  */
+
+#define CAN_ELIMINATE(FROM, TO) \
+((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM		\
+ ? ! frame_pointer_needed						\
+ : 1)
+
+/* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'.  It
+   specifies the initial difference between the specified pair of
+   registers.  This macro must be defined if `ELIMINABLE_REGS' is
+   defined.  */
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
+{									\
+  int size = m32r_compute_frame_size (get_frame_size ());		\
+									\
+ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
+   (OFFSET) = 0;							\
+ else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)	\
+   (OFFSET) = size - current_function_pretend_args_size;		\
+ else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)	\
+   (OFFSET) = size - current_function_pretend_args_size;		\
+  else									\
+    abort ();								\
+}
+
+/* Function argument passing.  */
+
+/* When a prototype says `char' or `short', really pass an `int'.  */
+#define PROMOTE_PROTOTYPES
+
+/* If defined, the maximum amount of space required for outgoing
+   arguments will be computed and placed into the variable
+   `current_function_outgoing_args_size'.  No space will be pushed
+   onto the stack for each call; instead, the function prologue should
+   increase the stack frame size by this amount.  */
+#define ACCUMULATE_OUTGOING_ARGS
+
+/* Define this macro if functions should assume that stack space has
+   been allocated for arguments even when their values are passed in
+   registers.
+
+   The value of this macro is the size, in bytes, of the area
+   reserved for arguments passed in registers for the function
+   represented by FNDECL.
+
+   This space can be allocated by the caller, or be a part of the
+   machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
+   which.  */
+#if 0
+#define REG_PARM_STACK_SPACE(FNDECL) \
+(M32R_MAX_PARM_REGS * UNITS_PER_WORD)
+#endif
+
+/* Value is the number of bytes of arguments automatically
+   popped when returning from a subroutine call.
+   FUNDECL is the declaration node of the function (as a tree),
+   FUNTYPE is the data type of the function (as a tree),
+   or for a library call it is an identifier node for the subroutine name.
+   SIZE is the number of bytes of arguments passed on the stack.  */
+#define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.  */
+#define CUMULATIVE_ARGS int
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.  */
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
+((CUM) = 0)
+
+/* The number of registers used for parameter passing.  Local to this file.  */
+#define M32R_MAX_PARM_REGS 4
+
+/* 1 if N is a possible register number for function argument passing.  */
+#define FUNCTION_ARG_REGNO_P(N) \
+((unsigned) (N) < M32R_MAX_PARM_REGS)
+
+/* The ROUND_ADVANCE* macros are local to this file.  */
+/* Round SIZE up to a word boundary.  */
+#define ROUND_ADVANCE(SIZE) \
+(((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+
+/* Round arg MODE/TYPE up to the next word boundary.  */
+#define ROUND_ADVANCE_ARG(MODE, TYPE) \
+((MODE) == BLKmode				\
+ ? ROUND_ADVANCE (int_size_in_bytes (TYPE))	\
+ : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))
+
+/* Round CUM up to the necessary point for argument MODE/TYPE.  */
+#if 0
+#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) \
+((((MODE) == BLKmode ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) \
+  > BITS_PER_WORD)	\
+ ? ((CUM) + 1 & ~1)	\
+ : (CUM))
+#else
+#define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
+#endif
+
+/* Return boolean indicating arg of type TYPE and mode MODE will be passed in
+   a reg.  This includes arguments that have to be passed by reference as the
+   pointer to them is passed in a reg if one is available (and that is what
+   we're given).
+   This macro is only used in this file.  */
+#define PASS_IN_REG_P(CUM, MODE, TYPE, NAMED) \
+(ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
+
+/* Determine where to put an argument to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).  */
+/* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
+   and the rest are pushed.  */
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
+(PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED))				\
+ ? gen_rtx (REG, (MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
+ : 0)
+
+/* ??? Quick hack to try to get varargs working the normal way.  */
+#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
+(((! current_function_varargs || (NAMED))				\
+  && PASS_IN_REG_P ((CUM), (MODE), (TYPE), (NAMED)))			\
+ ? gen_rtx (REG, (MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)))	\
+ : 0)
+
+/* A C expression for the number of words, at the beginning of an
+   argument, must be put in registers.  The value must be zero for
+   arguments that are passed entirely in registers or that are entirely
+   pushed on the stack.
+
+   On some machines, certain arguments must be passed partially in
+   registers and partially in memory.  On these machines, typically the
+   first @var{n} words of arguments are passed in registers, and the rest
+   on the stack.  If a multi-word argument (a @code{double} or a
+   structure) crosses that boundary, its first few words must be passed
+   in registers and the rest must be pushed.  This macro tells the
+   compiler when this occurs, and how many of the words should go in
+   registers.  */
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
+  function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
+
+/* A C expression that indicates when an argument must be passed by
+   reference.  If nonzero for an argument, a copy of that argument is
+   made in memory and a pointer to the argument is passed instead of
+   the argument itself.  The pointer is passed in whatever way is
+   appropriate for passing a pointer to that type.  */
+/* All arguments greater than 8 bytes are passed this way.  */
+#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
+((TYPE) && int_size_in_bytes (TYPE) > 8)
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
+((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \
+	  + ROUND_ADVANCE_ARG ((MODE), (TYPE))))
+
+/* If defined, a C expression that gives the alignment boundary, in bits,
+   of an argument with the specified mode and type.  If it is not defined, 
+   PARM_BOUNDARY is used for all arguments.  */
+#if 0
+/* We assume PARM_BOUNDARY == UNITS_PER_WORD here.  */
+#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
+(((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \
+ ? PARM_BOUNDARY \
+ : 2 * PARM_BOUNDARY)
+#endif
+
+#if 0
+/* If defined, is a C expression that produces the machine-specific
+   code for a call to `__builtin_saveregs'.  This code will be moved
+   to the very beginning of the function, before any parameter access
+   are made.  The return value of this function should be an RTX that
+   contains the value to use as the return of `__builtin_saveregs'.
+
+   The argument ARGS is a `tree_list' containing the arguments that
+   were passed to `__builtin_saveregs'.
+
+   If this macro is not defined, the compiler will output an ordinary
+   call to the library function `__builtin_saveregs'.  */
+extern struct rtx *m32r_expand_builtin_savergs ();
+#define EXPAND_BUILTIN_SAVEREGS(ARGS) m32r_expand_builtin_saveregs (ARGS)
+#endif
+
+/* This macro offers an alternative
+   to using `__builtin_saveregs' and defining the macro
+   `EXPAND_BUILTIN_SAVEREGS'.  Use it to store the anonymous register
+   arguments into the stack so that all the arguments appear to have
+   been passed consecutively on the stack.  Once this is done, you
+   can use the standard implementation of varargs that works for
+   machines that pass all their arguments on the stack.
+
+   The argument ARGS_SO_FAR is the `CUMULATIVE_ARGS' data structure,
+   containing the values that obtain after processing of the named
+   arguments.  The arguments MODE and TYPE describe the last named
+   argument--its machine mode and its data type as a tree node.
+
+   The macro implementation should do two things: first, push onto the
+   stack all the argument registers *not* used for the named
+   arguments, and second, store the size of the data thus pushed into
+   the `int'-valued variable whose name is supplied as the argument
+   PRETEND_SIZE.  The value that you store here will serve as
+   additional offset for setting up the stack frame.
+
+   If the argument NO_RTL is nonzero, it means that the
+   arguments of the function are being analyzed for the second time.
+   This happens for an inline function, which is not actually
+   compiled until the end of the source file.  The macro
+   `SETUP_INCOMING_VARARGS' should not generate any instructions in
+   this case.  */
+
+#define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
+m32r_setup_incoming_varargs (&ARGS_SO_FAR, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
+
+/* Function results.  */
+
+/* Define how to find the value returned by a function.
+   VALTYPE is the data type of the value (as a tree).
+   If the precise function being called is known, FUNC is its FUNCTION_DECL;
+   otherwise, FUNC is 0.  */
+#define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
+
+/* Define how to find the value returned by a library function
+   assuming the value has mode MODE.  */
+#define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
+
+/* 1 if N is a possible register number for a function value
+   as seen by the caller.  */
+/* ??? What about r1 in DI/DF values.  */
+#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
+
+/* A C expression which can inhibit the returning of certain function
+   values in registers, based on the type of value.  A nonzero value says
+   to return the function value in memory, just as large structures are
+   always returned.  Here TYPE will be a C expression of type `tree',
+   representing the data type of the value.  */
+#define RETURN_IN_MEMORY(TYPE) \
+(int_size_in_bytes (TYPE) > 8)
+
+/* Tell GCC to use RETURN_IN_MEMORY.  */
+#define DEFAULT_PCC_STRUCT_RETURN 0
+
+/* Register in which address to store a structure value
+   is passed to a function, or 0 to use `invisible' first argument.  */
+#define STRUCT_VALUE 0
+
+/* Function entry and exit.  */
+
+/* Initialize data used by insn expanders.  This is called from
+   init_emit, once for each function, before code is generated.  */
+#define INIT_EXPANDERS m32r_init_expanders ()
+
+/* This macro generates the assembly code for function entry.
+   FILE is a stdio stream to output the code to.
+   SIZE is an int: how many units of temporary storage to allocate.
+   Refer to the array `regs_ever_live' to determine which registers
+   to save; `regs_ever_live[I]' is nonzero if register number I
+   is ever used in the function.  This macro is responsible for
+   knowing which registers should not be saved even if used.  */
+#define FUNCTION_PROLOGUE(FILE, SIZE) \
+m32r_output_function_prologue (FILE, SIZE)
+
+/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
+   the stack pointer does not matter.  The value is tested only in
+   functions that have frame pointers.
+   No definition is equivalent to always zero.  */
+#define EXIT_IGNORE_STACK 1
+
+/* This macro generates the assembly code for function exit,
+   on machines that need it.  If FUNCTION_EPILOGUE is not defined
+   then individual return instructions are generated for each
+   return statement.  Args are same as for FUNCTION_PROLOGUE.
+
+   The function epilogue should not depend on the current stack pointer!
+   It should use the frame pointer only.  This is mandatory because
+   of alloca; we also take advantage of it to omit stack adjustments
+   before returning.  */
+#define FUNCTION_EPILOGUE(FILE, SIZE) \
+m32r_output_function_epilogue (FILE, SIZE)
+
+/* Output assembler code to FILE to increment profiler label # LABELNO
+   for profiling a function entry.  */
+#define FUNCTION_PROFILER(FILE, LABELNO)
+
+/* Trampolines.  */
+
+/* On the M32R, the trampoline is
+
+	ld24 r7,STATIC
+	ld24 r6,FUNCTION
+	jmp r6
+	nop
+
+   ??? Need addr32 support.
+*/
+
+/* Length in bytes of the trampoline for entering a nested function.  */
+#define TRAMPOLINE_SIZE 12
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.  */
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+do { \
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), \
+		  plus_constant ((CXT), 0xe7000000)); \
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
+		  plus_constant ((FNADDR), 0xe6000000)); \
+  emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), \
+		  GEN_INT (0x1fc67000)); \
+  emit_insn (gen_flush_icache (validize_mem (gen_rtx (MEM, SImode, TRAMP)))); \
+} while (0)
+
+/* Library calls.  */
+
+/* Generate calls to memcpy, memcmp and memset.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* Addressing modes, and classification of registers for them.  */
+
+/* Maximum number of registers that can appear in a valid memory address.  */
+#define MAX_REGS_PER_ADDRESS 1
+
+/* We have post-inc load and pre-dec,pre-inc store,
+   but only for 4 byte vals.  */
+#if 0
+#define HAVE_PRE_DECREMENT
+#define HAVE_PRE_INCREMENT
+#define HAVE_POST_INCREMENT
+#endif
+
+/* Recognize any constant value that is a valid address.  */
+#define CONSTANT_ADDRESS_P(X) \
+(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF	\
+ || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
+
+/* Nonzero if the constant value X is a legitimate general operand.
+   We don't allow (plus symbol large-constant) as the relocations can't
+   describe it.  INTVAL > 32767 handles both 16 bit and 24 bit relocations.
+   We allow all CONST_DOUBLE's as the md file patterns will force the
+   constant to memory if they can't handle them.  */
+
+#define LEGITIMATE_CONSTANT_P(X) \
+(! (GET_CODE (X) == CONST \
+    && GET_CODE (XEXP (X, 0)) == PLUS \
+    && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
+    && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
+    && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
+
+/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
+   and check its validity for a certain class.
+   We have two alternate definitions for each of them.
+   The usual definition accepts all pseudo regs; the other rejects
+   them unless they have been allocated suitable hard regs.
+   The symbol REG_OK_STRICT causes the latter definition to be used.
+
+   Most source files want to accept pseudo regs in the hope that
+   they will get allocated to the class that the insn wants them to be in.
+   Source files for reload pass need to be strict.
+   After reload, it makes no difference, since pseudo regs have
+   been eliminated by then.  */
+
+#ifdef REG_OK_STRICT
+
+/* Nonzero if X is a hard reg that can be used as a base reg.  */
+#define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as an index.  */
+#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
+
+#else
+
+/* Nonzero if X is a hard reg that can be used as a base reg
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_BASE_P(X) \
+(GPR_P (REGNO (X))			\
+ || (REGNO (X)) == ARG_POINTER_REGNUM	\
+ || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+/* Nonzero if X is a hard reg that can be used as an index
+   or if it is a pseudo reg.  */
+#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
+
+#endif
+
+/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
+   that is a valid memory address for an instruction.
+   The MODE argument is the machine mode for the MEM expression
+   that wants to use this address.  */
+
+/* local to this file */
+#define RTX_OK_FOR_BASE_P(X) \
+(REG_P (X) && REG_OK_FOR_BASE_P (X))
+
+/* local to this file */
+#define RTX_OK_FOR_OFFSET_P(X) \
+(GET_CODE (X) == CONST_INT && INT16_P (INTVAL (X)))
+
+/* local to this file */
+#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
+(GET_CODE (X) == PLUS				\
+ && RTX_OK_FOR_BASE_P (XEXP (X, 0))		\
+ && RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
+
+/* local to this file */
+#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
+(GET_CODE (X) == LO_SUM				\
+ && RTX_OK_FOR_BASE_P (XEXP (X, 0))		\
+ && CONSTANT_P (XEXP (X, 1)))
+
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
+{ if (RTX_OK_FOR_BASE_P (X))				\
+    goto ADDR;						\
+  if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X)))	\
+    goto ADDR;						\
+  if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X)))	\
+    goto ADDR;						\
+}
+
+/* Try machine-dependent ways of modifying an illegitimate address
+   to be legitimate.  If we find one, return the new, valid address.
+   This macro is used in only one place: `memory_address' in explow.c.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE and WIN are passed so that this macro can use
+   GO_IF_LEGITIMATE_ADDRESS.
+
+   It is always safe for this macro to do nothing.  It exists to recognize
+   opportunities to optimize the output.
+
+   ??? Is there anything useful we can do here for the M32R?  */
+
+#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
+
+/* Go to LABEL if ADDR (a legitimate address expression)
+   has an effect that depends on the machine mode it is used for.  */
+#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
+do {					\
+  if (GET_CODE (ADDR) == PRE_DEC)	\
+    goto LABEL;				\
+  if (GET_CODE (ADDR) == PRE_INC)	\
+    goto LABEL;				\
+  if (GET_CODE (ADDR) == POST_INC)	\
+    goto LABEL;				\
+} while (0)
+
+/* Condition code usage.  */
+
+/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
+   return the mode to be used for the comparison.  */
+extern enum machine_mode m32r_select_cc_mode ();
+#define SELECT_CC_MODE(OP, X, Y) \
+m32r_select_cc_mode (OP, X, Y)
+
+/* Return non-zero if SELECT_CC_MODE will never return MODE for a
+   floating point inequality comparison.  */
+#define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
+
+/* Costs.  */
+
+/* ??? I'm quite sure I don't understand enough of the subtleties involved
+   in choosing the right numbers to use here, but there doesn't seem to be
+   enough documentation on this.  What I've done is define an insn to cost
+   4 "units" and work from there.  COSTS_N_INSNS (N) is defined as (N) * 4 - 2
+   so that seems reasonable.  Some values are supposed to be defined relative
+   to each other and thus aren't necessarily related to COSTS_N_INSNS.  */
+
+/* Compute the cost of computing a constant rtl expression RTX
+   whose rtx-code is CODE.  The body of this macro is a portion
+   of a switch statement.  If the code is computed here,
+   return it with a return statement.  Otherwise, break from the switch.  */
+/* Small integers are as cheap as registers.  4 byte values can be fetched
+   as immediate constants - let's give that the cost of an extra insn.  */
+#define CONST_COSTS(X, CODE, OUTER_CODE) \
+  case CONST_INT :						\
+    if (INT16_P (INTVAL (X)))					\
+      return 0;							\
+    /* fall through */						\
+  case CONST :							\
+  case LABEL_REF :						\
+  case SYMBOL_REF :						\
+    return 4;							\
+  case CONST_DOUBLE :						\
+    {								\
+      rtx high, low;						\
+      split_double (X, &high, &low);				\
+      return 4 * (!INT16_P (INTVAL (high))			\
+		  + !INT16_P (INTVAL (low)));			\
+    }
+
+/* Compute the cost of an address.  */
+#define ADDRESS_COST(ADDR) m32r_address_cost (ADDR)
+
+/* Compute extra cost of moving data between one register class
+   and another.  */
+#define REGISTER_MOVE_COST(CLASS1, CLASS2) 2
+
+/* Compute the cost of moving data between registers and memory.  */
+/* Memory is 3 times as expensive as registers.
+   ??? Is that the right way to look at it?  */
+#define MEMORY_MOVE_COST(MODE) \
+(GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
+
+/* The cost of a branch insn.  */
+/* A value of 2 here causes GCC to avoid using branches in comparisons like
+   while (a < N && a).  Branches aren't that expensive on the M32R so
+   we define this as 1.  Defining it as 2 had a heavy hit in fp-bit.c.  */
+#define BRANCH_COST 1
+
+/* Provide the costs of a rtl expression.  This is in the body of a
+   switch on CODE.  The purpose for the cost of MULT is to encourage
+   `synth_mult' to find a synthetic multiply when reasonable.
+
+   If we need more than 12 insns to do a multiply, then go out-of-line,
+   since the call overhead will be < 10% of the cost of the multiply.  */
+#define RTX_COSTS(X, CODE, OUTER_CODE) \
+  case MULT :						\
+    return COSTS_N_INSNS (3);				\
+  case DIV :						\
+  case UDIV :						\
+  case MOD :						\
+  case UMOD :						\
+    return COSTS_N_INSNS (10);				\
+
+/* Nonzero if access to memory by bytes is slow and undesirable.
+   For RISC chips, it means that access to memory by bytes is no
+   better than access by words when possible, so grab a whole word
+   and maybe make use of that.  */
+#define SLOW_BYTE_ACCESS 1
+
+/* Define this macro if it is as good or better to call a constant
+   function address than to call an address kept in a register.  */
+#define NO_FUNCTION_CSE
+
+/* Define this macro if it is as good or better for a function to call
+   itself with an explicit address than to call an address kept in a
+   register.  */
+#define NO_RECURSIVE_FUNCTION_CSE
+
+/* Enable the register move pass.
+   This is useful for machines with only 2 address instructions.
+   It's not currently enabled by default because on the stanford benchmarks
+   the improvement wasn't significant and in a couple of cases caused a
+   significant de-optimization.  */
+/* #define ENABLE_REGMOVE_PASS */
+
+/* Section selection.  */
+
+#define TEXT_SECTION_ASM_OP	"\t.section .text"
+#define DATA_SECTION_ASM_OP	"\t.section .data"
+#define RODATA_SECTION_ASM_OP	"\t.section .rodata"
+#define BSS_SECTION_ASM_OP	"\t.section .bss"
+#define SDATA_SECTION_ASM_OP	"\t.section .sdata"
+#define SBSS_SECTION_ASM_OP	"\t.section .sbss"
+/* This one is for svr4.h.  */
+#undef CONST_SECTION_ASM_OP
+#define CONST_SECTION_ASM_OP	"\t.section .rodata"
+
+/* A list of names for sections other than the standard two, which are
+   `in_text' and `in_data'.  You need not define this macro
+   on a system with no other sections (that GCC needs to use).  */
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS in_sdata, in_sbss, in_const, in_ctors, in_dtors
+
+/* One or more functions to be defined in "varasm.c".  These
+   functions should do jobs analogous to those of `text_section' and
+   `data_section', for your additional sections.  Do not define this
+   macro if you do not define `EXTRA_SECTIONS'.  */
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS \
+CONST_SECTION_FUNCTION \
+CTORS_SECTION_FUNCTION \
+DTORS_SECTION_FUNCTION \
+SDATA_SECTION_FUNCTION \
+SBSS_SECTION_FUNCTION
+
+#define SDATA_SECTION_FUNCTION \
+void									\
+sdata_section ()							\
+{									\
+  if (in_section != in_sdata)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP);		\
+      in_section = in_sdata;						\
+    }									\
+}									\
+
+#define SBSS_SECTION_FUNCTION \
+void									\
+sbss_section ()								\
+{									\
+  if (in_section != in_sbss)						\
+    {									\
+      fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP);		\
+      in_section = in_sbss;						\
+    }									\
+}									\
+
+/* A C statement or statements to switch to the appropriate section for
+   output of EXP.  You can assume that EXP is either a `VAR_DECL' node
+   or a constant of some sort.  RELOC indicates whether the initial value
+   of EXP requires link-time relocations.  */
+extern void m32r_select_section ();
+#undef SELECT_SECTION
+#define SELECT_SECTION(EXP, RELOC) m32r_select_section ((EXP), (RELOC))
+
+/* A C statement or statements to switch to the appropriate section for
+   output of RTX in mode MODE.  You can assume that RTX
+   is some kind of constant in RTL.  The argument MODE is redundant
+   except in the case of a `const_int' rtx.  Select the section by
+   calling `text_section' or one of the alternatives for other
+   sections.
+
+   Do not define this macro if you put all constants in the read-only
+   data section.  */
+
+#undef SELECT_RTX_SECTION
+
+/* Define this macro if jump tables (for tablejump insns) should be
+   output in the text section, along with the assembler instructions.
+   Otherwise, the readonly data section is used.
+   This macro is irrelevant if there is no separate readonly data section.  */
+/*#define JUMP_TABLES_IN_TEXT_SECTION*/
+
+/* Define this macro if references to a symbol must be treated
+   differently depending on something about the variable or
+   function named by the symbol (such as what section it is in).
+
+   The macro definition, if any, is executed immediately after the
+   rtl for DECL or other node is created.
+   The value of the rtl will be a `mem' whose address is a
+   `symbol_ref'.
+
+   The usual thing for this macro to do is to store a flag in the
+   `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
+   name string in the `symbol_ref' (if one bit is not enough
+   information).  */
+
+#define SDATA_FLAG_CHAR '@'
+/* Small objects are recorded with no prefix for space efficiency since
+   they'll be the most common.  This isn't the case if the user passes
+   -mmodel={medium|large} and one could choose to not mark symbols that
+   are the default, but that complicates things.  */
+/*#define SMALL_FLAG_CHAR '#'*/
+#define MEDIUM_FLAG_CHAR '%'
+#define LARGE_FLAG_CHAR '&'
+
+#define SDATA_NAME_P(NAME) (*(NAME) == SDATA_FLAG_CHAR)
+/*#define SMALL_NAME_P(NAME) (*(NAME) == SMALL_FLAG_CHAR)*/
+#define SMALL_NAME_P(NAME) (! ENCODED_NAME_P (NAME) && ! LIT_NAME_P (NAME))
+#define MEDIUM_NAME_P(NAME) (*(NAME) == MEDIUM_FLAG_CHAR)
+#define LARGE_NAME_P(NAME) (*(NAME) == LARGE_FLAG_CHAR)
+/* For string literals, etc.  */
+#define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
+
+#define ENCODED_NAME_P(SYMBOL_NAME) \
+(SDATA_NAME_P (SYMBOL_NAME) \
+ /*|| SMALL_NAME_P (SYMBOL_NAME)*/ \
+ || MEDIUM_NAME_P (SYMBOL_NAME) \
+ || LARGE_NAME_P (SYMBOL_NAME))
+
+extern void m32r_encode_section_info ();
+#define ENCODE_SECTION_INFO(DECL) m32r_encode_section_info (DECL)
+
+/* Decode SYM_NAME and store the real name part in VAR, sans
+   the characters that encode section info.  Define this macro if
+   ENCODE_SECTION_INFO alters the symbol's name string.  */
+/* Note that we have to handle symbols like "%*start".  */
+#define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
+do {							\
+  (VAR) = (SYMBOL_NAME) + ENCODED_NAME_P (SYMBOL_NAME);	\
+  (VAR) += *(VAR) == '*';				\
+} while (0)
+
+/* PIC */
+
+/* The register number of the register used to address a table of static
+   data addresses in memory.  In some cases this register is defined by a
+   processor's ``application binary interface'' (ABI).  When this macro
+   is defined, RTL is generated for this register once, as with the stack
+   pointer and frame pointer registers.  If this macro is not defined, it
+   is up to the machine-dependent files to allocate such a register (if
+   necessary).  */
+/*#define PIC_OFFSET_TABLE_REGNUM 12*/
+
+/* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
+   clobbered by calls.  Do not define this macro if PIC_OFFSET_TABLE_REGNUM
+   is not defined.  */
+/* This register is call-saved on the M32R.  */
+/*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
+
+/* By generating position-independent code, when two different programs (A
+   and B) share a common library (libC.a), the text of the library can be
+   shared whether or not the library is linked at the same address for both
+   programs.  In some of these environments, position-independent code
+   requires not only the use of different addressing modes, but also
+   special code to enable the use of these addressing modes.
+
+   The FINALIZE_PIC macro serves as a hook to emit these special
+   codes once the function is being compiled into assembly code, but not
+   before.  (It is not done before, because in the case of compiling an
+   inline function, it would lead to multiple PIC prologues being
+   included in functions which used inline functions and were compiled to
+   assembly language.)  */
+
+/*#define FINALIZE_PIC m32r_finalize_pic ()*/
+
+/* A C expression that is nonzero if X is a legitimate immediate
+   operand on the target machine when generating position independent code.
+   You can assume that X satisfies CONSTANT_P, so you need not
+   check this.  You can also assume `flag_pic' is true, so you need not
+   check it either.  You need not define this macro if all constants
+   (including SYMBOL_REF) can be immediate operands when generating
+   position independent code.  */
+/*#define LEGITIMATE_PIC_OPERAND_P(X)*/
+
+/* Control the assembler format that we output.  */
+
+/* Output at beginning of assembler file.  */
+extern void m32r_asm_file_start ();
+#define ASM_FILE_START(FILE) m32r_asm_file_start (FILE)
+
+/* A C string constant describing how to begin a comment in the target
+   assembler language.  The compiler assumes that the comment will
+   end at the end of the line.  */
+#define ASM_COMMENT_START ";"
+
+/* Output to assembler file text saying following lines
+   may contain character constants, extra white space, comments, etc.  */
+#define ASM_APP_ON ""
+
+/* Output to assembler file text saying following lines
+   no longer contain unusual constructs.  */
+#define ASM_APP_OFF ""
+
+/* This is how to output an assembler line defining a `char' constant.  */
+#define ASM_OUTPUT_CHAR(FILE, VALUE) \
+do {						\
+  fprintf (FILE, "\t.byte\t");			\
+  output_addr_const (FILE, (VALUE));		\
+  fprintf (FILE, "\n");				\
+} while (0)
+
+/* This is how to output an assembler line defining a `short' constant.  */
+#define ASM_OUTPUT_SHORT(FILE, VALUE) \
+do {						\
+  fprintf (FILE, "\t.hword\t");			\
+  output_addr_const (FILE, (VALUE));		\
+  fprintf (FILE, "\n");				\
+} while (0)
+
+/* This is how to output an assembler line defining an `int' constant.
+   We also handle symbol output here.  */
+#define ASM_OUTPUT_INT(FILE, VALUE) \
+do {							\
+  fprintf (FILE, "\t.word\t");				\
+  output_addr_const (FILE, (VALUE));			\
+  fprintf (FILE, "\n");					\
+} while (0)
+
+/* This is how to output an assembler line defining a `float' constant.  */
+#define ASM_OUTPUT_FLOAT(FILE, VALUE) \
+do {							\
+  long t;						\
+  char str[30];						\
+  REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);		\
+  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);	\
+  fprintf (FILE, "\t.word\t0x%lx %s %s\n",		\
+	   t, ASM_COMMENT_START, str);			\
+} while (0)
+
+/* This is how to output an assembler line defining a `double' constant.  */
+#define ASM_OUTPUT_DOUBLE(FILE, VALUE) \
+do {							\
+  long t[2];						\
+  char str[30];						\
+  REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t);		\
+  REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);	\
+  fprintf (FILE, "\t.word\t0x%lx %s %s\n\t.word\t0x%lx\n", \
+	   t[0], ASM_COMMENT_START, str, t[1]);		\
+} while (0)
+
+/* This is how to output an assembler line for a numeric constant byte.  */
+#define ASM_OUTPUT_BYTE(FILE, VALUE)  \
+  fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
+
+/* The assembler's parentheses characters.  */
+#define ASM_OPEN_PAREN "("
+#define ASM_CLOSE_PAREN ")"
+
+/* This is how to output the definition of a user-level label named NAME,
+   such as the label on a static function or variable NAME.  */
+/* On the M32R we need to ensure the next instruction starts on a 32 bit
+   boundary [the previous insn must either be 2 16 bit insns or 1 32 bit].  */
+#define ASM_OUTPUT_LABEL(FILE, NAME) \
+do {					\
+  assemble_name (FILE, NAME);		\
+  fputs (":\n", FILE);			\
+} while (0)
+
+/* This is how to output a command to make the user-level label named NAME
+   defined for reference from other files.  */
+#define ASM_GLOBALIZE_LABEL(FILE, NAME) \
+do {				\
+  fputs ("\t.global\t", FILE);	\
+  assemble_name (FILE, NAME);	\
+  fputs ("\n", FILE);		\
+} while (0)
+
+/* This is how to output a reference to a user-level label named NAME.
+   `assemble_name' uses this.  */
+#undef ASM_OUTPUT_LABELREF
+#define ASM_OUTPUT_LABELREF(FILE, NAME) \
+do {							\
+  char *real_name;					\
+  STRIP_NAME_ENCODING (real_name, (NAME));		\
+  fprintf (FILE, "%s%s", USER_LABEL_PREFIX, real_name);	\
+} while (0)           
+
+/* Store in OUTPUT a string (made with alloca) containing
+   an assembler-name for a local static variable named NAME.
+   LABELNO is an integer which is different for each call.  */
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
+do {							\
+  (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10);	\
+  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO));	\
+} while (0)
+
+/* How to refer to registers in assembler output.
+   This sequence is indexed by compiler's hard-register-number (see above).  */
+#define REGISTER_NAMES \
+{							\
+  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",	\
+  "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp",	\
+  "ap", "cbit"						\
+}
+
+/* If defined, a C initializer for an array of structures containing
+   a name and a register number.  This macro defines additional names
+   for hard registers, thus allowing the `asm' option in declarations
+   to refer to registers using alternate names.  */
+#define ADDITIONAL_REGISTER_NAMES \
+{					\
+  /*{ "gp", GP_REGNUM },*/		\
+  { "r13", FRAME_POINTER_REGNUM },	\
+  { "r14", RETURN_ADDR_REGNUM },	\
+  { "r15", STACK_POINTER_REGNUM },	\
+}
+
+/* A C expression which evaluates to true if CODE is a valid
+   punctuation character for use in the `PRINT_OPERAND' macro.  */
+extern char m32r_punct_chars[];
+#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
+m32r_punct_chars[(unsigned char) (CHAR)]
+
+/* Print operand X (an rtx) in assembler syntax to file FILE.
+   CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
+   For `%' followed by punctuation, CODE is the punctuation and X is null.  */
+#define PRINT_OPERAND(FILE, X, CODE) \
+m32r_print_operand (FILE, X, CODE)
+
+/* A C compound statement to output to stdio stream STREAM the
+   assembler syntax for an instruction operand that is a memory
+   reference whose address is ADDR.  ADDR is an RTL expression.
+
+   On some machines, the syntax for a symbolic address depends on
+   the section that the address refers to.  On these machines,
+   define the macro `ENCODE_SECTION_INFO' to store the information
+   into the `symbol_ref', and then check for it here.  */
+#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
+m32r_print_operand_address (FILE, ADDR)
+
+/* If defined, C string expressions to be used for the `%R', `%L',
+   `%U', and `%I' options of `asm_fprintf' (see `final.c').  These
+   are useful when a single `md' file must support multiple assembler
+   formats.  In that case, the various `tm.h' files can define these
+   macros differently.  */
+#define REGISTER_PREFIX ""
+#define LOCAL_LABEL_PREFIX ".L"
+#define USER_LABEL_PREFIX ""
+#define IMMEDIATE_PREFIX "#"
+
+/* This is how to output an element of a case-vector that is absolute.  */
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
+do {							\
+  char label[30];					\
+  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
+  fprintf (FILE, "\t.word\t");				\
+  assemble_name (FILE, label);				\
+  fprintf (FILE, "\n");					\
+} while (0)
+
+/* This is how to output an element of a case-vector that is relative.  */
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
+do {							\
+  char label[30];					\
+  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);	\
+  fprintf (FILE, "\t.word\t");				\
+  assemble_name (FILE, label);				\
+  fprintf (FILE, "-");					\
+  ASM_GENERATE_INTERNAL_LABEL (label, "L", REL);	\
+  assemble_name (FILE, label);				\
+  fprintf (FILE, ")\n");				\
+} while (0)
+
+/* A C expression to output text to align the location counter in the way
+   that is desirable at the beginning of a loop.  */
+/* On the M32R, align loops to 32 byte boundaries (cache line size)
+   if -malign-loops.  */
+#define ASM_OUTPUT_LOOP_ALIGN(FILE) \
+do { if (TARGET_ALIGN_LOOPS) ASM_OUTPUT_ALIGN (FILE, 5); } while (0)
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+/* .balign is used to avoid confusion.  */
+#define ASM_OUTPUT_ALIGN(FILE,LOG) \
+do { if ((LOG) != 0) fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); } while (0)
+
+/* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a
+   separate, explicit argument.  If you define this macro, it is used in
+   place of `ASM_OUTPUT_COMMON', and gives you more flexibility in
+   handling the required alignment of the variable.  The alignment is
+   specified as the number of bits.  */
+
+#define SCOMMON_ASM_OP ".scomm"
+
+#undef ASM_OUTPUT_ALIGNED_COMMON
+#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
+do {									\
+  if (! TARGET_SDATA_NONE						\
+      && (SIZE) > 0 && (SIZE) <= g_switch_value)			\
+    fprintf ((FILE), "\t%s\t", SCOMMON_ASM_OP);				\
+  else									\
+    fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
+  assemble_name ((FILE), (NAME));					\
+  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
+} while (0)
+
+#if 0 /* not needed, delete later */
+/* Like `ASM_OUTPUT_LOCAL' except takes the required alignment as a
+   separate, explicit argument.  If you define this macro, it is used in
+   place of `ASM_OUTPUT_LOCAL', and gives you more flexibility in
+   handling the required alignment of the variable.  The alignment is
+   specified as the number of bits.  */
+
+extern void sbss_section ();
+
+#undef ASM_OUTPUT_ALIGNED_LOCAL
+#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
+do {									\
+  if ((SIZE) > 0 && (SIZE) <= g_switch_value)				\
+    {									\
+      sbss_section ();							\
+      ASM_OUTPUT_ALIGN (FILE, exact_log2 (ALIGN / BITS_PER_UNIT));	\
+      ASM_OUTPUT_LABEL (FILE, NAME);					\
+      ASM_OUTPUT_SKIP (FILE, SIZE);					\
+      if (!flag_inhibit_size_directive)					\
+	{								\
+	  fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);			\
+	  assemble_name (FILE, NAME);					\
+	  fprintf (FILE, ",%d\n",  SIZE);				\
+	}								\
+    }									\
+  else									\
+    {									\
+      /* This is copied from svr4.h.  */				\
+      fprintf ((FILE), "\t%s\t", LOCAL_ASM_OP);				\
+      assemble_name ((FILE), (NAME));					\
+      fprintf ((FILE), "\n");						\
+      ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);		\
+    }									\
+} while (0)
+#endif
+
+/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
+   separate, explicit argument.  If you define this macro, it is used in
+   place of `ASM_OUTPUT_BSS', and gives you more flexibility in
+   handling the required alignment of the variable.  The alignment is
+   specified as the number of bits.
+
+   For the M32R we need sbss support.  */
+
+#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
+do {									\
+  ASM_GLOBALIZE_LABEL (FILE, NAME);					\
+  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
+} while (0)
+
+/* Debugging information.  */
+
+/* Generate DBX and DWARF debugging information.  */
+#define DBX_DEBUGGING_INFO
+#define DWARF_DEBUGGING_INFO
+
+/* Prefer STABS (for now).  */
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+
+/* How to renumber registers for dbx and gdb.  */
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+/* Turn off splitting of long stabs.  */
+#define DBX_CONTIN_LENGTH 0
+
+/* Miscellaneous.  */
+
+/* Specify the machine mode that this machine uses
+   for the index in the tablejump instruction.  */
+#define CASE_VECTOR_MODE Pmode
+
+/* Define this if the tablejump instruction expects the table
+   to contain offsets from the address of the table.
+   Do not define this if the table should contain absolute addresses.  */
+/* It's not clear what PIC will look like or whether we want to use -fpic
+   for the embedded form currently being talked about.  For now require -fpic
+   to get pc relative switch tables.  */
+/*#define CASE_VECTOR_PC_RELATIVE*/
+
+/* Define if operations between registers always perform the operation
+   on the full register even if a narrower mode is specified.  */
+#define WORD_REGISTER_OPERATIONS
+
+/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
+   will either zero-extend or sign-extend.  The value of this macro should
+   be the code that says which one of the two operations is implicitly
+   done, NIL if none.  */
+#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
+
+/* Specify the tree operation to be used to convert reals to integers.  */
+#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
+
+/* This is the kind of divide that is easiest to do in the general case.  */
+#define EASY_DIV_EXPR TRUNC_DIV_EXPR
+
+/* Max number of bytes we can move from memory to memory
+   in one reasonably fast instruction.  */
+#define MOVE_MAX 4
+
+/* Define this to be nonzero if shift instructions ignore all but the low-order
+   few bits.  */
+#define SHIFT_COUNT_TRUNCATED 1
+
+/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
+   is done just by pretending it is already truncated.  */
+#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
+
+/* We assume that the store-condition-codes instructions store 0 for false
+   and some other value for true.  This is the value stored for true.  */
+#define STORE_FLAG_VALUE 1
+
+/* Specify the machine mode that pointers have.
+   After generation of rtl, the compiler makes no further distinction
+   between pointers and any other objects of this machine mode.  */
+/* ??? The M32R doesn't have full 32 bit pointers, but making this PSImode has
+   it's own problems (you have to add extendpsisi2 and truncsipsi2).
+   Try to avoid it.  */
+#define Pmode SImode
+
+/* A function address in a call instruction.  */
+#define FUNCTION_MODE SImode
+
+/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
+   is a valid machine specific attribute for DECL.
+   The attributes in ATTRIBUTES have previously been assigned to TYPE.  */
+extern int m32r_valid_machine_attribute ();
+#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
+m32r_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
+
+/* A C expression that returns zero if the attributes on TYPE1 and TYPE2 are
+   incompatible, one if they are compatible, and two if they are
+   nearly compatible (which causes a warning to be generated).  */
+extern int m32r_comp_type_attributes ();
+#define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \
+m32r_comp_type_attributes (TYPE1, TYPE2)
+
+/* Give newly defined TYPE some default attributes.  */
+extern void m32r_set_default_type_attributes ();
+#define SET_DEFAULT_TYPE_ATTRIBUTES(TYPE) \
+m32r_set_default_type_attributes (TYPE)
+
+/* Define the information needed to generate branch and scc insns.  This is
+   stored from the compare operation.  Note that we can't use "rtx" here
+   since it hasn't been defined!  */
+extern struct rtx_def *m32r_compare_op0, *m32r_compare_op1;
+
+/* Define the function that build the compare insn for scc and bcc.  */
+extern struct rtx_def *gen_compare ();
+
+/* M32R function types.   */
+enum m32r_function_type {
+  M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT
+};
+#define M32R_INTERRUPT_P(TYPE) \
+((TYPE) == M32R_FUNCTION_INTERRUPT)
+/* Compute the type of a function from its DECL.  */
+enum m32r_function_type m32r_compute_function_type ();
diff --git a/gnu/usr.bin/gcc/config/m32r/m32r.md b/gnu/usr.bin/gcc/config/m32r/m32r.md
new file mode 100644
index 00000000000..4c8b2e54ffb
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/m32r/m32r.md
@@ -0,0 +1,1469 @@
+;; Machine description of the Mitsubishi M32R cpu for GNU C compiler
+;; Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+
+;; This file is part of GNU CC.
+
+;; GNU CC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+
+;; GNU CC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GNU CC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;; unspec usage
+;; 0 - blockage
+;; 1 - flush_icache
+;; 2 - load_sda_base
+
+;; Insn type.  Used to default other attribute values.
+;; move4 = 4 byte move
+(define_attr "type"
+  "move,move4,load,store,unary,binary,compare,shift,mul,div,uncond_branch,branch,call,multi,misc"
+  (const_string "misc"))
+
+;; Length in bytes.
+(define_attr "length" ""
+  (cond [(eq_attr "type" "move,unary,shift,mul,div")
+	 (const_int 2)
+
+	 (eq_attr "type" "binary")
+	 (if_then_else (match_operand 2 "register_operand" "")
+		       (const_int 2) (const_int 4))
+
+	 (eq_attr "type" "compare")
+	 (if_then_else (match_operand 1 "register_operand" "")
+		       (const_int 2) (const_int 4))
+
+	 (eq_attr "type" "load")
+	 (if_then_else (match_operand 1 "memreg_operand" "")
+		       (const_int 2) (const_int 4))
+
+	 (eq_attr "type" "store")
+	 (if_then_else (match_operand 0 "memreg_operand" "")
+		       (const_int 2) (const_int 4))
+
+	 (eq_attr "type" "multi")
+	 (const_int 8)
+
+	 (eq_attr "type" "uncond_branch,branch,call")
+	 (const_int 4)]
+
+	 (const_int 4)))
+
+;; The length here is the length of a single asm.  Unfortunately it might be
+;; 2 or 4 so we must allow for 4.  That's ok though.
+(define_asm_attributes
+  [(set_attr "length" "4")
+   (set_attr "type" "multi")])
+
+;; Function units of the M32R
+;; Units that take one cycle do not need to be specified.
+
+;; (define_function_unit {name} {num-units} {n-users} {test}
+;;                       {ready-delay} {issue-delay} [{conflict-list}])
+
+;; References to loaded registers should wait a cycle.
+;; Memory with load-delay of 1 (i.e. 2 cycle load).
+(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
+
+;; Hack to get GCC to better pack the instructions.
+;; We pretend there is a separate long function unit that conflicts with
+;; both the left and right 16 bit insn slots.
+
+(define_function_unit "left" 1 1
+  (eq_attr "length" "2")
+  1 0
+  [(not (eq_attr "length" "2"))])
+
+(define_function_unit "right" 1 1
+  (eq_attr "length" "1")
+  1 0
+  [(not (eq_attr "length" "2"))])
+
+(define_function_unit "long" 1 1
+  (not (eq_attr "length" "2"))
+  1 0
+  [(eq_attr "length" "2")])
+
+;; Expand prologue as RTL
+;; ??? Unfinished.
+
+;(define_expand "prologue"
+;  [(const_int 1)]
+;  ""
+;  "
+;{
+;}")
+
+;; Move instructions.
+;;
+;; For QI and HI moves, the register must contain the full properly
+;; sign-extended value.  nonzero_bits assumes this [otherwise
+;; SHORT_IMMEDIATES_SIGN_EXTEND must be used, but the comment for it
+;; says it's a kludge and the .md files should be fixed instead].
+
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "general_operand" "")
+	(match_operand:QI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* Everything except mem = const or mem = mem can be done easily.
+     Objects in the small data area are handled too.  */
+
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (QImode, operands[1]);
+}")
+
+(define_insn "*movqi_insn"
+  [(set (match_operand:QI 0 "move_dest_operand" "=r,r,r,r,m")
+	(match_operand:QI 1 "move_src_operand" "r,I,JQR,m,r"))]
+  "register_operand (operands[0], QImode) || register_operand (operands[1], QImode)"
+  "@
+   mv %0,%1
+   ldi %0,%#%1
+   ldi %0,%#%1
+   ldub %0,%1
+   stb %1,%0"
+  [(set_attr "type" "move,move,move4,load,store")])
+
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "general_operand" "")
+	(match_operand:HI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* Everything except mem = const or mem = mem can be done easily.  */
+
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (HImode, operands[1]);
+}")
+
+(define_insn "*movhi_insn"
+  [(set (match_operand:HI 0 "move_dest_operand" "=r,r,r,r,r,m")
+	(match_operand:HI 1 "move_src_operand" "r,I,JQR,K,m,r"))]
+  "register_operand (operands[0], HImode) || register_operand (operands[1], HImode)"
+  "@
+   mv %0,%1
+   ldi %0,%#%1
+   ldi %0,%#%1
+   ld24 %0,%#%1
+   lduh %0,%1
+   sth %1,%0"
+  [(set_attr "type" "move,move,move4,move4,load,store")])
+
+(define_expand "movsi"
+  [(set (match_operand:SI 0 "general_operand" "")
+	(match_operand:SI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* Everything except mem = const or mem = mem can be done easily.  */
+
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (SImode, operands[1]);
+
+  /* Small Data Area reference?  */
+  if (small_data_operand (operands[1], SImode))
+    {
+      emit_insn (gen_movsi_sda (operands[0], operands[1]));
+      DONE;
+    }
+
+  /* If medium or large code model, symbols have to be loaded with
+     seth/add3.  */
+  if (addr32_operand (operands[1], SImode))
+    {
+      emit_insn (gen_movsi_addr32 (operands[0], operands[1]));
+      DONE;
+    }
+}")
+
+(define_insn "*movsi_insn"
+  [(set (match_operand:SI 0 "move_dest_operand" "=r,r,r,r,r,r,r,m")
+;; ??? Do we need a const_double constraint here for large unsigned values?
+	(match_operand:SI 1 "move_src_operand" "r,I,J,MQ,L,N,m,r"))]
+  "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
+  "@
+   mv %0,%1
+   ldi %0,%#%1 ; %X1
+   ldi %0,%#%1 ; %X1
+   ld24 %0,%#%1 ; %X1
+   seth %0,%#%T1
+   seth %0,%#%T1\;or3 %0,%0,%#%B1
+   ld %0,%1
+   st %1,%0"
+  [(set_attr "type" "move,move,move4,move4,move4,multi,load,store")])
+
+; Try to use a four byte / two byte pair for constants not loadable with
+; ldi, ld24, seth.
+
+(define_split
+ [(set (match_operand:SI 0 "register_operand" "")
+       (match_operand:SI 1 "two_insn_const_operand" ""))]
+  ""
+  [(set (match_dup 0) (match_dup 2))
+   (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 3)))]
+  "
+{
+  unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
+  unsigned HOST_WIDE_INT tmp;
+  int shift;
+
+  /* In all cases we will emit two instructions.  However we try to
+     use 2 byte instructions wherever possible.  We can assume the
+     constant isn't loadable with any of ldi, ld24, or seth.  */
+
+  /* See if we can load a 24 bit unsigned value and invert it.  */
+  if (UINT24_P (~ val))
+    {
+      emit_insn (gen_movsi (operands[0], GEN_INT (~ val)));
+      emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
+      DONE;
+    }
+
+  /* See if we can load a 24 bit unsigned value and shift it into place.
+     0x01fffffe is just beyond ld24's range.  */
+  for (shift = 1, tmp = 0x01fffffe;
+       shift < 8;
+       ++shift, tmp <<= 1)
+    {
+      if ((val & ~tmp) == 0)
+	{
+	  emit_insn (gen_movsi (operands[0], GEN_INT (val >> shift)));
+	  emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (shift)));
+	  DONE;
+	}
+    }
+
+  /* Can't use any two byte insn, fall back to seth/or3.  */
+  operands[2] = GEN_INT ((val) & 0xffff0000);
+  operands[3] = GEN_INT ((val) & 0xffff);
+}")
+
+;; Small data area support.
+;; The address of _SDA_BASE_ is loaded into a register and all objects in
+;; the small data area are indexed off that.  This is done for each reference
+;; but cse will clean things up for us.  We let the compiler choose the
+;; register to use so we needn't allocate (and maybe even fix) a special
+;; register to use.  Since the load and store insns have a 16 bit offset the
+;; total size of the data area can be 64K.  However, if the data area lives
+;; above 16M (24 bits), _SDA_BASE_ will have to be loaded with seth/add3 which
+;; would then yield 3 instructions to reference an object [though there would
+;; be no net loss if two or more objects were referenced].  The 3 insns can be
+;; reduced back to 2 if the size of the small data area were reduced to 32K
+;; [then seth + ld/st would work for any object in the area].  Doing this
+;; would require special handling of _SDA_BASE_ (its value would be
+;; (.sdata + 32K) & 0xffff0000) and reloc computations would be different
+;; [I think].  What to do about this is deferred until later and for now we
+;; require .sdata to be in the first 16M.
+
+(define_expand "movsi_sda"
+  [(set (match_dup 2)
+	(unspec [(const_int 0)] 2))
+   (set (match_operand:SI 0 "register_operand" "")
+	(lo_sum:SI (match_dup 2)
+		   (match_operand:SI 1 "small_data_operand" "")))]
+  ""
+  "
+{
+  if (reload_in_progress || reload_completed)
+    operands[2] = operands[0];
+  else
+    operands[2] = gen_reg_rtx (SImode);
+}")
+
+(define_insn "*load_sda_base"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec [(const_int 0)] 2))]
+  ""
+  "ld24 %0,#_SDA_BASE_"
+  [(set_attr "type" "move4")])
+
+;; 32 bit address support.
+
+(define_expand "movsi_addr32"
+  [(set (match_dup 2)
+	; addr32_operand isn't used because it's too restrictive,
+	; seth_add3_operand is more general and thus safer.
+	(high:SI (match_operand:SI 1 "seth_add3_operand" "")))
+   (set (match_operand:SI 0 "register_operand" "")
+	(lo_sum:SI (match_dup 2) (match_dup 1)))]
+  ""
+  "
+{
+  if (reload_in_progress || reload_completed)
+    operands[2] = operands[0];
+  else
+    operands[2] = gen_reg_rtx (SImode);
+}")
+
+(define_insn "set_hi_si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(high:SI (match_operand 1 "symbolic_operand" "")))]
+  ""
+  "seth %0,%#shigh(%1)"
+  [(set_attr "type" "move4")])
+
+(define_insn "lo_sum_si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (match_operand:SI 2 "immediate_operand" "in")))]
+  ""
+  "add3 %0,%1,%#%B2"
+  [(set_attr "length" "4")])
+
+(define_expand "movdi"
+  [(set (match_operand:DI 0 "general_operand" "")
+	(match_operand:DI 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* Everything except mem = const or mem = mem can be done easily.  */
+
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (DImode, operands[1]);
+
+  if (CONSTANT_P (operands[1])
+      && ! easy_di_const (operands[1]))
+    {
+      rtx mem = force_const_mem (DImode, operands[1]);
+      rtx reg = ((reload_in_progress || reload_completed)
+		 ? copy_to_suggested_reg (XEXP (mem, 0),
+					  gen_rtx (REG, Pmode, REGNO (operands[0])),
+					  Pmode)
+		 : force_reg (Pmode, XEXP (mem, 0)));
+      operands[1] = change_address (mem, DImode, reg);
+    }
+}")
+
+(define_insn "*movdi_insn"
+  [(set (match_operand:DI 0 "move_dest_operand" "=r,r,r,m")
+	(match_operand:DI 1 "move_double_src_operand" "r,nG,m,r"))]
+  "register_operand (operands[0], DImode) || register_operand (operands[1], DImode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0 :
+      /* We normally copy the low-numbered register first.  However, if
+	 the first register operand 0 is the same as the second register of
+	 operand 1, we must copy in the opposite order.  */
+      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
+	return \"mv %R0,%R1\;mv %0,%1\";
+      else
+	return \"mv %0,%1\;mv %R0,%R1\";
+    case 1 :
+      return \"#\";
+    case 2 :
+      /* If the low-address word is used in the address, we must load it
+	 last.  Otherwise, load it first.  Note that we cannot have
+	 auto-increment in that case since the address register is known to be
+	 dead.  */
+      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			     operands [1], 0))
+	{
+	  return \"ld %R0,%R1\;ld %0,%1\";
+	}
+      else
+	{
+	  /* Try to use auto-inc addressing if we can.  */
+	  if (GET_CODE (XEXP (operands[1], 0)) == REG
+	      && dead_or_set_p (insn, XEXP (operands[1], 0)))
+	    {
+	      operands[1] = XEXP (operands[1], 0);
+	      return \"ld %0,@%1+\;ld %R0,@%1\";
+	    }
+	  return \"ld %0,%1\;ld %R0,%R1\";
+	}
+    case 3 :
+      /* Try to use auto-inc addressing if we can.  */
+      if (GET_CODE (XEXP (operands[0], 0)) == REG
+	  && dead_or_set_p (insn, XEXP (operands[0], 0)))
+	{
+	  operands[0] = XEXP (operands[0], 0);
+	  return \"st %1,@%0\;st %R1,@+%0\";
+	}
+      return \"st %1,%0\;st %R1,%R0\";
+    }
+}"
+  [(set_attr "type" "multi,multi,multi,multi")
+   (set_attr "length" "4,4,6,6")])
+
+(define_split
+  [(set (match_operand:DI 0 "register_operand" "")
+	(match_operand:DI 1 "const_double_operand" ""))]
+  "reload_completed"
+  [(set (match_dup 2) (match_dup 4))
+   (set (match_dup 3) (match_dup 5))]
+  "
+{
+  operands[2] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN == 0);
+  operands[3] = gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+  split_double (operands[1], operands + 4, operands + 5);
+}")
+
+;; Floating point move insns.
+
+(define_expand "movsf"
+  [(set (match_operand:SF 0 "general_operand" "")
+	(match_operand:SF 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* Everything except mem = const or mem = mem can be done easily.  */
+
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (SFmode, operands[1]);
+}")
+
+(define_insn "*movsf_insn"
+  [(set (match_operand:SF 0 "move_dest_operand" "=r,r,r,m")
+	(match_operand:SF 1 "move_src_operand" "r,F,m,r"))]
+  "register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0 :
+      return \"mv %0,%1\";
+    case 1 :
+      {
+	REAL_VALUE_TYPE r;
+	long l;
+	REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+	REAL_VALUE_TO_TARGET_SINGLE (r, l);
+	operands[1] = GEN_INT (l);
+	if (l == 0)
+	  return \"ldi %0,%#0\";
+	if ((l & 0xffff) == 0)
+	  return \"seth %0,%#%T1\";
+	else
+	  return \"seth %0,%#%T1\;or3 %0,%0,%#%B1\";
+      }
+    case 2 :
+      return \"ld %0,%1\";
+    case 3 :
+      return \"st %1,%0\";
+    }
+}"
+  ;; ??? Length of alternative 1 is either 2, 4 or 8.
+  [(set_attr "type" "move,multi,load,store")])
+
+(define_expand "movdf"
+  [(set (match_operand:DF 0 "general_operand" "")
+	(match_operand:DF 1 "general_operand" ""))]
+  ""
+  "
+{
+  /* Everything except mem = const or mem = mem can be done easily.  */
+
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (DFmode, operands[1]);
+
+  if (GET_CODE (operands[1]) == CONST_DOUBLE
+      && ! easy_df_const (operands[1]))
+    {
+      rtx mem = force_const_mem (DFmode, operands[1]);
+      rtx reg = ((reload_in_progress || reload_completed)
+		 ? copy_to_suggested_reg (XEXP (mem, 0),
+					  gen_rtx (REG, Pmode, REGNO (operands[0])),
+					  Pmode)
+		 : force_reg (Pmode, XEXP (mem, 0)));
+      operands[1] = change_address (mem, DFmode, reg);
+    }
+}")
+
+(define_insn "*movdf_insn"
+  [(set (match_operand:DF 0 "move_dest_operand" "=r,r,r,m")
+	(match_operand:DF 1 "move_double_src_operand" "r,H,m,r"))]
+  "register_operand (operands[0], DFmode) || register_operand (operands[1], DFmode)"
+  "*
+{
+  switch (which_alternative)
+    {
+    case 0 :
+      /* We normally copy the low-numbered register first.  However, if
+	 the first register operand 0 is the same as the second register of
+	 operand 1, we must copy in the opposite order.  */
+      if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
+	return \"mv %R0,%R1\;mv %0,%1\";
+      else
+	return \"mv %0,%1\;mv %R0,%R1\";
+    case 1 :
+      {
+	REAL_VALUE_TYPE r;
+	long l[2];
+	REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
+	REAL_VALUE_TO_TARGET_DOUBLE (r, l);
+	operands[1] = GEN_INT (l[0]);
+	if (l[0] == 0 && l[1] == 0)
+	  return \"ldi %0,%#0\;ldi %R0,%#0\";
+	else if (l[1] != 0)
+	  abort ();
+	else if ((l[0] & 0xffff) == 0)
+	  return \"seth %0,%#%T1\;ldi %R0,%#0\";
+	else
+	  abort ();
+      }
+    case 2 :
+      /* If the low-address word is used in the address, we must load it
+	 last.  Otherwise, load it first.  Note that we cannot have
+	 auto-increment in that case since the address register is known to be
+	 dead.  */
+      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
+			     operands [1], 0))
+	{
+	  return \"ld %R0,%R1\;ld %0,%1\";
+	}
+      else
+	{
+	  /* Try to use auto-inc addressing if we can.  */
+	  if (GET_CODE (XEXP (operands[1], 0)) == REG
+	      && dead_or_set_p (insn, XEXP (operands[1], 0)))
+	    {
+	      operands[1] = XEXP (operands[1], 0);
+	      return \"ld %0,@%1+\;ld %R0,@%1\";
+	    }
+	  return \"ld %0,%1\;ld %R0,%R1\";
+	}
+    case 3 :
+      /* Try to use auto-inc addressing if we can.  */
+      if (GET_CODE (XEXP (operands[0], 0)) == REG
+	  && dead_or_set_p (insn, XEXP (operands[0], 0)))
+	{
+	  operands[0] = XEXP (operands[0], 0);
+	  return \"st %1,@%0\;st %R1,@+%0\";
+	}
+      return \"st %1,%0\;st %R1,%R0\";
+    }
+}"
+  [(set_attr "type" "multi,multi,multi,multi")
+   (set_attr "length" "4,6,6,6")])
+
+;; Zero extension instructions.
+
+(define_insn "zero_extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "=r,r")
+	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+  ""
+  "@
+   and3 %0,%1,%#255
+   ldub %0,%1"
+  [(set_attr "type" "unary,load")
+   (set_attr "length" "4,*")])
+
+(define_insn "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+  ""
+  "@
+   and3 %0,%1,%#255
+   ldub %0,%1"
+  [(set_attr "type" "unary,load")
+   (set_attr "length" "4,*")])
+
+(define_insn "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+  ""
+  "@
+   and3 %0,%1,%#65535
+   lduh %0,%1"
+  [(set_attr "type" "unary,load")
+   (set_attr "length" "4,*")])
+
+;; Sign extension instructions.
+;; ??? See v850.md.
+
+;; These patterns originally accepted general_operands, however, slightly
+;; better code is generated by only accepting register_operands, and then
+;; letting combine generate the lds[hb] insns.
+;; [This comment copied from sparc.md, I think.]
+
+(define_expand "extendqihi2"
+  [(set (match_operand:HI 0 "register_operand" "")
+	(sign_extend:HI (match_operand:QI 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx temp = gen_reg_rtx (SImode);
+  rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
+  int op1_subword = 0;
+  int op0_subword = 0;
+
+  if (GET_CODE (operand1) == SUBREG)
+    {
+      op1_subword = SUBREG_WORD (operand1);
+      operand1 = XEXP (operand1, 0);
+    }
+  if (GET_CODE (operand0) == SUBREG)
+    {
+      op0_subword = SUBREG_WORD (operand0);
+      operand0 = XEXP (operand0, 0);
+    }
+  emit_insn (gen_ashlsi3 (temp, gen_rtx (SUBREG, SImode, operand1,
+					 op1_subword),
+			  shift_24));
+  if (GET_MODE (operand0) != SImode)
+    operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subword);
+  emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
+  DONE;
+}")
+
+(define_insn "*sign_extendqihi2_insn"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
+  ""
+  "ldb %0,%1"
+  [(set_attr "type" "load")])
+
+(define_expand "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx temp = gen_reg_rtx (SImode);
+  rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
+  int op1_subword = 0;
+
+  if (GET_CODE (operand1) == SUBREG)
+    {
+      op1_subword = SUBREG_WORD (operand1);
+      operand1 = XEXP (operand1, 0);
+    }
+
+  emit_insn (gen_ashlsi3 (temp, gen_rtx (SUBREG, SImode, operand1,
+					 op1_subword),
+			  shift_24));
+  emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
+  DONE;
+}")
+
+(define_insn "*sign_extendqisi2_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
+  ""
+  "ldb %0,%1"
+  [(set_attr "type" "load")])
+
+(define_expand "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
+  ""
+  "
+{
+  rtx temp = gen_reg_rtx (SImode);
+  rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16);
+  int op1_subword = 0;
+
+  if (GET_CODE (operand1) == SUBREG)
+    {
+      op1_subword = SUBREG_WORD (operand1);
+      operand1 = XEXP (operand1, 0);
+    }
+
+  emit_insn (gen_ashlsi3 (temp, gen_rtx (SUBREG, SImode, operand1,
+					 op1_subword),
+			  shift_16));
+  emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
+  DONE;
+}")
+
+(define_insn "*sign_extendhisi2_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
+  ""
+  "ldh %0,%1"
+  [(set_attr "type" "load")])
+
+;; Arithmetic instructions.
+
+; ??? Adding an alternative to split add3 of small constants into two
+; insns yields better instruction packing but slower code.  Adds of small
+; values is done a lot.
+
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(plus:SI (match_operand:SI 1 "register_operand" "%0,0,r")
+		 (match_operand:SI 2 "nonmemory_operand" "r,I,J")))]
+  ""
+  "@
+   add %0,%2
+   addi %0,%#%2
+   add3 %0,%1,%#%2"
+  [(set_attr "type" "binary")
+   (set_attr "length" "2,2,4")])
+
+;(define_split
+;  [(set (match_operand:SI 0 "register_operand" "")
+;	(plus:SI (match_operand:SI 1 "register_operand" "")
+;		 (match_operand:SI 2 "int8_operand" "")))]
+;  "reload_completed
+;   && REGNO (operands[0]) != REGNO (operands[1])
+;   && INT8_P (INTVAL (operands[2]))
+;   && INTVAL (operands[2]) != 0"
+;  [(set (match_dup 0) (match_dup 1))
+;   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
+;  "")
+
+(define_insn "adddi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "%0")
+		 (match_operand:DI 2 "register_operand" "r")))
+   (clobber (reg:CC 17))]
+  ""
+  "*
+{
+  /* ??? The cmp clears the condition bit.  Can we speed up somehow?  */
+  return \"cmp %L0,%L0\;addx %L0,%L2\;addx %H0,%H2\";
+}"
+  [(set_attr "type" "binary")
+   (set_attr "length" "6")])
+
+(define_insn "subsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(minus:SI (match_operand:SI 1 "register_operand" "0")
+		  (match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "sub %0,%2"
+  [(set_attr "type" "binary")])
+
+(define_insn "subdi3"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(minus:DI (match_operand:DI 1 "register_operand" "0")
+		  (match_operand:DI 2 "register_operand" "r")))
+   (clobber (reg:CC 17))]
+  ""
+  "*
+{
+  /* ??? The cmp clears the condition bit.  Can we speed up somehow?  */
+  return \"cmp %L0,%L0\;subx %L0,%L2\;subx %H0,%H2\";
+}"
+  [(set_attr "type" "binary")
+   (set_attr "length" "6")])
+
+; Multiply/Divide instructions.
+
+(define_insn "mulhisi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "r"))
+		 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
+  ""
+  "mullo %1,%2\;mvfacmi %0"
+  [(set_attr "type" "mul")
+   (set_attr "length" "4")])
+
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(mult:SI (match_operand:SI 1 "register_operand" "%0")
+		 (match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "mul %0,%2"
+  [(set_attr "type" "mul")])
+
+(define_insn "divsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(div:SI (match_operand:SI 1 "register_operand" "0")
+		(match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "div %0,%2"
+  [(set_attr "type" "div")])
+
+(define_insn "udivsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(udiv:SI (match_operand:SI 1 "register_operand" "0")
+		 (match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "divu %0,%2"
+  [(set_attr "type" "div")])
+
+(define_insn "modsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(mod:SI (match_operand:SI 1 "register_operand" "0")
+		(match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "rem %0,%2"
+  [(set_attr "type" "div")])
+
+(define_insn "umodsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(umod:SI (match_operand:SI 1 "register_operand" "0")
+		 (match_operand:SI 2 "register_operand" "r")))]
+  ""
+  "remu %0,%2"
+  [(set_attr "type" "div")])
+
+;; Boolean instructions.
+;;
+;; We don't define the DImode versions as expand_binop does a good enough job.
+;; And if it doesn't it should be fixed.
+
+(define_insn "andsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(and:SI (match_operand:SI 1 "register_operand" "%0,r")
+		(match_operand:SI 2 "nonmemory_operand" "r,K")))]
+  ""
+  "@
+   and %0,%2
+   and3 %0,%1,%#%2 ; %X2"
+  [(set_attr "type" "binary")])
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(ior:SI (match_operand:SI 1 "register_operand" "%0,r")
+		(match_operand:SI 2 "nonmemory_operand" "r,K")))]
+  ""
+  "@
+   or %0,%2
+   or3 %0,%1,%#%2 ; %X2"
+  [(set_attr "type" "binary")])
+
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(xor:SI (match_operand:SI 1 "register_operand" "%0,r")
+		(match_operand:SI 2 "nonmemory_operand" "r,K")))]
+  ""
+  "@
+   xor %0,%2
+   xor3 %0,%1,%#%2 ; %X2"
+  [(set_attr "type" "binary")])
+
+(define_insn "negsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "neg %0,%1"
+  [(set_attr "type" "unary")])
+
+(define_insn "one_cmplsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operand:SI 1 "register_operand" "r")))]
+  ""
+  "not %0,%1"
+  [(set_attr "type" "unary")])
+
+;; Shift instructions.
+
+(define_insn "ashlsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
+		   (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
+  ""
+  "@
+   sll %0,%2
+   slli %0,%#%2
+   sll3 %0,%1,%#%2"
+  [(set_attr "type" "shift")
+   (set_attr "length" "2,2,4")])
+
+(define_insn "ashrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
+		     (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
+  ""
+  "@
+   sra %0,%2
+   srai %0,%#%2
+   sra3 %0,%1,%#%2"
+  [(set_attr "type" "shift")
+   (set_attr "length" "2,2,4")])
+
+(define_insn "lshrsi3"
+  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
+	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
+		     (match_operand:SI 2 "reg_or_uint16_operand" "r,O,K")))]
+  ""
+  "@
+   srl %0,%2
+   srli %0,%#%2
+   srl3 %0,%1,%#%2"
+  [(set_attr "type" "shift")
+   (set_attr "length" "2,2,4")])
+
+;; Compare instructions.
+;; This controls RTL generation and register allocation.
+
+;; We generate RTL for comparisons and branches by having the cmpxx 
+;; patterns store away the operands.  Then the bcc patterns
+;; emit RTL for both the compare and the branch.
+;;
+;; On the m32r it is more efficient to use the bxxz instructions and
+;; thus merge the compare and branch into one instruction, so they are
+;; preferred.
+
+(define_expand "cmpsi"
+  [(set (reg:CC 17)
+	(compare:CC (match_operand:SI 0 "register_operand" "")
+		    (match_operand:SI 1 "nonmemory_operand" "")))]
+  ""
+  "
+{
+  m32r_compare_op0 = operands[0];
+  m32r_compare_op1 = operands[1];
+  DONE;
+}")
+
+;; The cmp_xxx_insn patterns set the condition bit to the result of the
+;; comparison.  There isn't a "compare equal" instruction so cmp_eqsi_insn
+;; is quite inefficient.  However, it is rarely used.
+
+(define_insn "cmp_eqsi_insn"
+  [(set (reg:CC 17)
+	(eq:CC (match_operand:SI 0 "register_operand" "r,r")
+	       (match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
+   (clobber (match_scratch:SI 2 "=&r,&r"))]
+  "TARGET_OLD_COMPARE"
+  "@
+   mv %2,%0\;sub %2,%1\;cmpui %2,#1
+   add3 %2,%0,%#%N1\;cmpui %2,#1"
+  [(set_attr "type" "compare,compare")
+   (set_attr "length" "8,8")])
+
+(define_insn "cmp_ltsi_insn"
+  [(set (reg:CC 17)
+	(lt:CC (match_operand:SI 0 "register_operand" "r,r")
+	       (match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
+  ""
+  "@
+   cmp %0,%1
+   cmpi %0,%#%1"
+  [(set_attr "type" "compare")])
+
+(define_insn "cmp_ltusi_insn"
+  [(set (reg:CC 17)
+	(ltu:CC (match_operand:SI 0 "register_operand" "r,r")
+	        (match_operand:SI 1 "reg_or_uint16_operand" "r,K")))]
+  ""
+  "@
+   cmpu %0,%1
+   cmpui %0,%#%1"
+  [(set_attr "type" "compare")])
+
+;; reg == small constant comparisons are best handled by putting the result
+;; of the comparison in a tmp reg and then using beqz/bnez.
+;; ??? The result register doesn't contain 0/STORE_FLAG_VALUE,
+;; it contains 0/non-zero.
+
+(define_insn "cmp_ne_small_const_insn"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ne:SI (match_operand:SI 1 "register_operand" "r")
+	       (match_operand:SI 2 "cmp_int16_operand" "P")))]
+  ""
+  "add3 %0,%1,%#%N2"
+  [(set_attr "type" "compare")
+   (set_attr "length" "4")])
+
+;; These control RTL generation for conditional jump insns.
+
+(define_expand "beq"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (EQ, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "bne"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (NE, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "bgt"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (GT, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "ble"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (LE, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "bge"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (GE, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "blt"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (LT, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "bgtu"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (GTU, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "bleu"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (LEU, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "bgeu"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (GEU, m32r_compare_op0, m32r_compare_op1);
+}")
+
+(define_expand "bltu"
+  [(set (pc)
+	(if_then_else (match_dup 1)
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "
+{
+  operands[1] = gen_compare (LTU, m32r_compare_op0, m32r_compare_op1);
+}")
+
+;; Now match both normal and inverted jump.
+
+(define_insn "*branch_insn"
+  [(set (pc)
+	(if_then_else (match_operator 1 "eqne_comparison_operator"
+				      [(reg 17) (const_int 0)])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == NE)
+    return \"bc %l0\";
+  else
+    return \"bnc %l0\";
+}"
+  [(set_attr "type" "branch")
+   ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+   ; lengths and insn alignments that are complex to track.
+   ; It's not important that we be hyper-precise here.  It may be more
+   ; important blah blah blah when the chip supports parallel execution
+   ; blah blah blah but until then blah blah blah this is simple and
+   ; suffices.
+   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						 (const_int 400))
+					   (const_int 800))
+				      (const_int 2)
+				      (const_int 4)))])
+
+(define_insn "*rev_branch_insn"
+  [(set (pc)
+	(if_then_else (match_operator 1 "eqne_comparison_operator"
+				      [(reg 17) (const_int 0)])
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ;"REVERSIBLE_CC_MODE (GET_MODE (XEXP (operands[1], 0)))"
+  ""
+  "*
+{
+  if (GET_CODE (operands[1]) == EQ)
+    return \"bc %l0\";
+  else
+    return \"bnc %l0\";
+}"
+  [(set_attr "type" "branch")
+   ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+   ; lengths and insn alignments that are complex to track.
+   ; It's not important that we be hyper-precise here.  It may be more
+   ; important blah blah blah when the chip supports parallel execution
+   ; blah blah blah but until then blah blah blah this is simple and
+   ; suffices.
+   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						 (const_int 400))
+					   (const_int 800))
+				      (const_int 2)
+				      (const_int 4)))])
+
+; reg/reg compare and branch insns
+
+(define_insn "*reg_branch_insn"
+  [(set (pc)
+	(if_then_else (match_operator 1 "eqne_comparison_operator"
+				      [(match_operand:SI 2 "register_operand" "r")
+				       (match_operand:SI 3 "register_operand" "r")])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  /* Is branch target reachable with beq/bne?  */
+  if (get_attr_length (insn) == 4)
+    {
+      if (GET_CODE (operands[1]) == EQ)
+	return \"beq %2,%3,%l0\";
+      else
+	return \"bne %2,%3,%l0\";
+    }
+  else
+    {
+      if (GET_CODE (operands[1]) == EQ)
+	return \"bne %2,%3,1f\;bra %l0\;1:\";
+      else
+	return \"beq %2,%3,1f\;bra %l0\;1:\";
+    }
+}"
+  [(set_attr "type" "branch")
+  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
+  ; which is complex to track and inaccurate length specs.
+   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						 (const_int 25000))
+					   (const_int 50000))
+				      (const_int 4)
+				      (const_int 8)))])
+
+(define_insn "*rev_reg_branch_insn"
+  [(set (pc)
+	(if_then_else (match_operator 1 "eqne_comparison_operator"
+				      [(match_operand:SI 2 "register_operand" "r")
+				       (match_operand:SI 3 "register_operand" "r")])
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  /* Is branch target reachable with beq/bne?  */
+  if (get_attr_length (insn) == 4)
+    {
+      if (GET_CODE (operands[1]) == NE)
+	return \"beq %2,%3,%l0\";
+      else
+	return \"bne %2,%3,%l0\";
+    }
+  else
+    {
+      if (GET_CODE (operands[1]) == NE)
+	return \"bne %2,%3,1f\;bra %l0\;1:\";
+      else
+	return \"beq %2,%3,1f\;bra %l0\;1:\";
+    }
+}"
+  [(set_attr "type" "branch")
+  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
+  ; which is complex to track and inaccurate length specs.
+   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						 (const_int 25000))
+					   (const_int 50000))
+				      (const_int 4)
+				      (const_int 8)))])
+
+; reg/zero compare and branch insns
+
+(define_insn "*zero_branch_insn"
+  [(set (pc)
+	(if_then_else (match_operator 1 "signed_comparison_operator"
+				      [(match_operand:SI 2 "register_operand" "r")
+				       (const_int 0)])
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))]
+  ""
+  "*
+{
+  char *br,*invbr;
+  char asmtext[40];
+
+  switch (GET_CODE (operands[1]))
+    {
+      case EQ : br = \"eq\"; invbr = \"ne\"; break;
+      case NE : br = \"ne\"; invbr = \"eq\"; break;
+      case LE : br = \"le\"; invbr = \"gt\"; break;
+      case GT : br = \"gt\"; invbr = \"le\"; break;
+      case LT : br = \"lt\"; invbr = \"ge\"; break;
+      case GE : br = \"ge\"; invbr = \"lt\"; break;
+    }
+
+  /* Is branch target reachable with bxxz?  */
+  if (get_attr_length (insn) == 4)
+    {
+      sprintf (asmtext, \"b%sz %%2,%%l0\", br);
+      output_asm_insn (asmtext, operands);
+    }
+  else
+    {
+      sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", invbr);
+      output_asm_insn (asmtext, operands);
+    }
+  return \"\";
+}"
+  [(set_attr "type" "branch")
+  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
+  ; which is complex to track and inaccurate length specs.
+   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						 (const_int 25000))
+					   (const_int 50000))
+				      (const_int 4)
+				      (const_int 8)))])
+
+(define_insn "*rev_zero_branch_insn"
+  [(set (pc)
+	(if_then_else (match_operator 1 "eqne_comparison_operator"
+				      [(match_operand:SI 2 "register_operand" "r")
+				       (const_int 0)])
+		      (pc)
+		      (label_ref (match_operand 0 "" ""))))]
+  ""
+  "*
+{
+  char *br,*invbr;
+  char asmtext[40];
+
+  switch (GET_CODE (operands[1]))
+    {
+      case EQ : br = \"eq\"; invbr = \"ne\"; break;
+      case NE : br = \"ne\"; invbr = \"eq\"; break;
+      case LE : br = \"le\"; invbr = \"gt\"; break;
+      case GT : br = \"gt\"; invbr = \"le\"; break;
+      case LT : br = \"lt\"; invbr = \"ge\"; break;
+      case GE : br = \"ge\"; invbr = \"lt\"; break;
+    }
+
+  /* Is branch target reachable with bxxz?  */
+  if (get_attr_length (insn) == 4)
+    {
+      sprintf (asmtext, \"b%sz %%2,%%l0\", invbr);
+      output_asm_insn (asmtext, operands);
+    }
+  else
+    {
+      sprintf (asmtext, \"b%sz %%2,1f\;bra %%l0\;1:\", br);
+      output_asm_insn (asmtext, operands);
+    }
+  return \"\";
+}"
+  [(set_attr "type" "branch")
+  ; We use 25000/50000 instead of 32768/65536 to account for slot filling
+  ; which is complex to track and inaccurate length specs.
+   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						 (const_int 25000))
+					   (const_int 50000))
+				      (const_int 4)
+				      (const_int 8)))])
+
+;; Unconditional and other jump instructions.
+
+(define_insn "jump"
+  [(set (pc) (label_ref (match_operand 0 "" "")))]
+  ""
+  "bra %l0"
+  [(set_attr "type" "uncond_branch")
+   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
+						 (const_int 400))
+					   (const_int 800))
+				      (const_int 2)
+				      (const_int 4)))])
+
+(define_insn "indirect_jump"
+  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
+  ""
+  "jmp %a0"
+  [(set_attr "type" "uncond_branch")
+   (set_attr "length" "2")])
+ 
+(define_insn "tablejump"
+  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmp %a0"
+  [(set_attr "type" "uncond_branch")
+   (set_attr "length" "2")])
+
+(define_expand "call"
+  ;; operands[1] is stack_size_rtx
+  ;; operands[2] is next_arg_register
+  [(parallel [(call (match_operand:SI 0 "call_operand" "")
+		    (match_operand 1 "" ""))
+	     (clobber (reg:SI 14))])]
+  ""
+  "")
+
+(define_insn "*call_via_reg"
+  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
+	 (match_operand 1 "" ""))
+   (clobber (reg:SI 14))]
+  ""
+  "jl %0"
+  [(set_attr "type" "call")
+   (set_attr "length" "2")])
+
+(define_insn "*call_via_label"
+  [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
+	 (match_operand 1 "" ""))
+   (clobber (reg:SI 14))]
+  ""
+  "*
+{
+  int call26_p = call26_operand (operands[0], FUNCTION_MODE);
+
+  if (! call26_p)
+    {
+      /* We may not be able to reach with a `bl' insn so punt and leave it to
+	 the linker.
+	 We do this here, rather than doing a force_reg in the define_expand
+	 so these insns won't be separated, say by scheduling, thus simplifying
+	 the linker.  */
+      return \"seth r14,%T0\;add3 r14,r14,%B0\;jl r14\";
+    }
+  else
+    return \"bl %0\";
+}"
+  [(set_attr "type" "call")
+   (set (attr "length")
+	(if_then_else (eq (symbol_ref "call26_operand (operands[0], FUNCTION_MODE)")
+			  (const_int 0))
+		      (const_int 12) ; 10 + 2 for nop filler
+		      ; The return address must be on a 4 byte boundary so
+		      ; there's no point in using a value of 2 here.  A 2 byte
+		      ; insn may go in the left slot but we currently can't
+		      ; use such knowledge.
+		      (const_int 4)))])
+
+(define_expand "call_value"
+  ;; operand 2 is stack_size_rtx
+  ;; operand 3 is next_arg_register
+  [(parallel [(set (match_operand 0 "register_operand" "=r")
+		   (call (match_operand:SI 1 "call_operand" "")
+			 (match_operand 2 "" "")))
+	     (clobber (reg:SI 14))])]
+  ""
+  "")
+
+(define_insn "*call_value_via_reg"
+  [(set (match_operand 0 "register_operand" "=r")
+	(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	      (match_operand 2 "" "")))
+   (clobber (reg:SI 14))]
+  ""
+  "jl %1"
+  [(set_attr "type" "call")
+   (set_attr "length" "2")])
+
+(define_insn "*call_value_via_label"
+  [(set (match_operand 0 "register_operand" "=r")
+	(call (mem:SI (match_operand:SI 1 "call_address_operand" ""))
+	      (match_operand 2 "" "")))
+   (clobber (reg:SI 14))]
+  ""
+  "*
+{
+  int call26_p = call26_operand (operands[1], FUNCTION_MODE);
+
+  if (! call26_p)
+    {
+      /* We may not be able to reach with a `bl' insn so punt and leave it to
+	 the linker.
+	 We do this here, rather than doing a force_reg in the define_expand
+	 so these insns won't be separated, say by scheduling, thus simplifying
+	 the linker.  */
+      return \"seth r14,%T1\;add3 r14,r14,%B1\;jl r14\";
+    }
+  else
+    return \"bl %1\";
+}"
+  [(set_attr "type" "call")
+   (set (attr "length")
+	(if_then_else (eq (symbol_ref "call26_operand (operands[1], FUNCTION_MODE)")
+			  (const_int 0))
+		      (const_int 12) ; 10 + 2 for nop filler
+		      ; The return address must be on a 4 byte boundary so
+		      ; there's no point in using a value of 2 here.  A 2 byte
+		      ; insn may go in the left slot but we currently can't
+		      ; use such knowledge.
+		      (const_int 4)))])
+
+(define_insn "nop"
+  [(const_int 0)]
+  ""
+  "nop"
+  [(set_attr "type" "misc")
+   (set_attr "length" "2")])
+
+;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
+;; all of memory.  This blocks insns from being moved across this point.
+
+(define_insn "blockage"
+  [(unspec_volatile [(const_int 0)] 0)]
+  ""
+  "")
+
+;; Special pattern to flush the icache.
+
+(define_insn "flush_icache"
+  [(unspec_volatile [(match_operand 0 "memory_operand" "m")] 0)]
+  ""
+  "* return \"nop ; flush-icache\";"
+  [(set_attr "type" "misc")])
+
+;; Split up troublesome insns for better scheduling.
+
+;; Peepholes go at the end.
+
+;; ??? Setting the type attribute may not be useful, but for completeness
+;; we do it.
+
+(define_peephole
+  [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
+			 (const_int 4)))
+        (match_operand:SI 1 "register_operand" "r"))]
+  "dead_or_set_p (insn, operands[0])"
+  "st %1,@+%0"
+  [(set_attr "type" "store")
+   (set_attr "length" "2")])
diff --git a/gnu/usr.bin/gcc/config/m32r/t-m32r b/gnu/usr.bin/gcc/config/m32r/t-m32r
new file mode 100644
index 00000000000..6005eb96db3
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/m32r/t-m32r
@@ -0,0 +1,57 @@
+# lib1funcs.asm is currently empty.
+CROSS_LIBGCC1 =
+
+# These are really part of libgcc1, but this will cause them to be
+# built correctly, so...
+
+LIB2FUNCS_EXTRA = fp-bit.c dp-bit.c
+
+# Turn off the SDA while compiling libgcc2.  There are no headers for it
+# and we want maximal upward compatibility here.
+
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+# We need to use -fpic when we are using gcc to compile the routines in
+# initfini.c.  This is only really needed when we are going to use gcc/g++
+# to produce a shared library, but since we don't know ahead of time when
+# we will be doing that, we just always use -fpic when compiling the
+# routines in initfini.c.
+# -fpic currently isn't supported for the m32r.
+
+CRTSTUFF_T_CFLAGS =
+
+# .init/.fini section routines
+
+crtinit.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
+	  -DCRT_INIT -finhibit-size-directive -fno-inline-functions \
+	  -g0 -c $(srcdir)/config/m32r/initfini.c -o crtinit.o
+
+crtfini.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
+	  -DCRT_FINI -finhibit-size-directive -fno-inline-functions \
+	  -g0 -c $(srcdir)/config/m32r/initfini.c -o crtfini.o
+
+# -mmodel={small,medium} requires separate libraries.
+# We don't build libraries for the large model, instead we use the medium
+# libraries.  The only difference is that the large model can handle jumps
+# more than 26 signed bits away.
+
+MULTILIB_OPTIONS = mmodel=small/mmodel=medium
+MULTILIB_DIRNAMES = small medium
+MULTILIB_MATCHES = mmodel?medium=mmodel?large
+
+# Set MULTILIB_EXTRA_OPTS so shipped libraries have small data in .sdata and
+# SHN_M32R_SCOMMON.
+# This is important for objects referenced in system header files.
+MULTILIB_EXTRA_OPTS = msdata=sdata
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib
diff --git a/gnu/usr.bin/gcc/config/m32r/xm-m32r.h b/gnu/usr.bin/gcc/config/m32r/xm-m32r.h
new file mode 100644
index 00000000000..57100c875cd
--- /dev/null
+++ b/gnu/usr.bin/gcc/config/m32r/xm-m32r.h
@@ -0,0 +1,47 @@
+/* Configuration for GNU C-compiler for the M32R processor.
+   Copyright (C) 1996 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* #defines that need visibility everywhere.  */
+#define FALSE 0
+#define TRUE 1
+
+/* This describes the machine the compiler is hosted on.  */
+#define HOST_BITS_PER_CHAR 8
+#define HOST_BITS_PER_SHORT 16
+#define HOST_BITS_PER_INT 32
+#define HOST_BITS_PER_LONG 32
+#define HOST_BITS_PER_LONGLONG 64
+
+/* Doubles are stored in memory with the high order word first.  This
+   matters when cross-compiling.  */
+#define HOST_WORDS_BIG_ENDIAN 1
+
+/* target machine dependencies.
+   tm.h is a symbolic link to the actual target specific file.   */
+#include "tm.h"
+
+/* Arguments to use with `exit'.  */
+#define SUCCESS_EXIT_CODE 0
+#define FATAL_EXIT_CODE 33
+
+/* If compiled with Sun CC, the use of alloca requires this #include.  */
+#ifndef __GNUC__
+#include "alloca.h"
+#endif