Convert the gcc 3 scheduling information to the gcc 4 model.

1 files changed, 165 insertions, 1 deletions

diff --git a/gnu/gcc/gcc/config/m88k/m88k.md b/gnu/gcc/gcc/config/m88k/m88k.md
index a59e9a62a9c..69078b865db 100644
--- a/gnu/gcc/gcc/config/m88k/m88k.md
+++ b/gnu/gcc/gcc/config/m88k/m88k.md
@@ -2,7 +2,6 @@
 ;;  Copyright (C) 1988, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000
 ;;  Free Software Foundation, Inc.
 ;;  Contributed by Michael Tiemann (tiemann@mcc.com)
-;;  Currently maintained by (gcc@dg-rtp.dg.com)
 
 ;; This file is part of GCC.
 
@@ -92,6 +91,171 @@
   [(eq_attr "type" "!branch,call,marith,weird") ; required.
    (nil) (nil)])
 
+;; Scheduling information
+
+;; This section is derived from the old define_function_unit description.
+;; Each reservation can be overriden on a processor-by-processor basis.
+
+; An abstract block diagram of the function units for the m88100.
+;
+;			    *
+;			    |
+;			+---v----+
+;			| decode |
+;			+-vv-v-v-+	 fpu
+;	       ,----------'| | `----------------------.
+;	       |	   | |			      |	,-----.
+;	  load |     store | | arith		      |	|     |
+;	       |	   | |			    +-v-v-+   |	dp source
+;	       |	   | |			    | fp1 |---'
+;     store    |	   | |	    div		    +-v-v-+
+;   ,------.   |	   | |	  ,-----. ,-----------'	`-----------.
+;   |	   |   |	   | |	  |	| |			    |
+;   |	+--v---v--+    ,---' |	  |   +-v-v---+			+---v---+
+;   |	| stage	2 |    |     |	  `---|	add 2 |			| mul 2	|
+;   |	+---------+    |  +--v--+     +-------+		  imul	+-------+
+;   |	| stage	1 |    |  | alu	|     |	add 3 |	       ,--------| mul 3	|
+;   |	+---------+    |  +--v--+     +-------+	       |	+-------+
+;   |	| stage	0 |    |     |	      |	add 4 |	       |	| mul 4	|
+;   |	+--v---v--+    |     |	      +---v---+	       |	+-------+
+;   |	   |   |       |     |		  |	       |	| mul 5	|
+;   |	   *   |       |     |		  |	       |	+---v---+
+;   |	       |       |     |		  |	  +----v----+	    |
+;   |	  load |       |     |	   fp add `------>| fp last |<------' fp mul
+;   |	       |       |     |			  +---v-v--^+
+;   |	       |       |     |			      |	|  |
+;   |	       |       |     |			      |	`--' dp	dest
+;   |	       |    +--v-----v--+		      |
+;   |	       `--->| writeback	|<--------------------'
+;   |		    +--v-----v--+
+;   |		       |     |
+;   `------------------'     *
+;
+; The decode unit need not be specified.
+; Consideration of writeback contention is critical to superb scheduling.
+
+(define_automaton "alu,fpu")
+
+(define_cpu_unit "alu" "alu")
+(define_cpu_unit "fpu" "fpu")
+
+(define_insn_reservation "generic_alu" 1
+ (eq_attr "type" "!store,marith,weird")
+ "alu")
+
+(define_insn_reservation "generic_alu_2" 2
+ (eq_attr "type" "marith,weird")
+ "alu")
+
+; 88100 specific
+
+(define_insn_reservation "store_88100" 1
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "store,loada"))
+ "alu")
+
+(define_insn_reservation "load_88100" 3
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "load"))
+ "alu")
+
+(define_insn_reservation "loadd_88100" 3
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "loadd"))
+ "alu*2")
+
+; The times are adjusted to include fp1 and fplast, but then are further
+; adjusted based on the actual generated code.  The notation to the right
+; is the total latency.  A range denotes a group of instructions and/or
+; conditions (the extra clock of fplast time with some sequences).
+
+(define_insn_reservation "spmul_88100" 4
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "spmul"))
+ "fpu")									; 6-8
+(define_insn_reservation "dpmul_88100" 7
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "dpmul"))
+ "fpu")									; 9-10
+(define_insn_reservation "imul_88100" 3
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "imul"))
+ "fpu")									; 4
+
+(define_insn_reservation "spdiv_88100" 30
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "spdiv"))
+ "fpu")									; 30-31
+(define_insn_reservation "dpdiv_88100" 60
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "dpdiv"))
+ "fpu")									; 60-61
+(define_insn_reservation "idiv_88100" 38
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "idiv"))
+ "fpu")									; 38
+
+(define_insn_reservation "spadd_88100" 3
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "spadd,spcmp"))
+ "fpu")									; 5-6
+(define_insn_reservation "dpadd_88100" 4
+ (and (eq_attr "cpu" "m88100")
+      (eq_attr "type" "dpadd,dpcmp"))
+ "fpu")									; 6-7
+
+; 88110 specific
+
+(define_insn_reservation "alu_88110" 2
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "loada,arith,mov"))
+ "alu")
+(define_insn_reservation "arith_88110" 4
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "marith,weird"))
+ "alu")
+
+(define_insn_reservation "bit_88110" 2
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "bit"))
+ "alu*2")
+
+(define_insn_reservation "load_88110" 3
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "load,loadd"))
+ "alu*2")
+(define_insn_reservation "store_88110" 1
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "store"))
+ "alu*2")
+
+(define_insn_reservation "spdiv_88110" 25
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "spdiv"))
+ "fpu*2")								; 13
+(define_insn_reservation "dpdiv_88110" 45
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "dpdiv"))
+ "fpu*2")								; 23
+(define_insn_reservation "idiv_88110" 35
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "idiv"))
+ "fpu*2")								; 18
+
+(define_insn_reservation "mul_88110" 5
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "imul,spmul,dpmul"))
+ "fpu*2")								; 3
+
+(define_insn_reservation "fpadd_88110" 5
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "spadd,dpadd"))
+ "fpu*2")								; 3
+(define_insn_reservation "fpcmp_88110" 2
+ (and (eq_attr "cpu" "!m88100")
+      (eq_attr "type" "spcmp,dpcmp"))
+ "fpu*2")								; 1
+
 ;; Superoptimizer sequences
 
 ;; geu+: { r = ((unsigned_word) v0 >= (unsigned_word) v1) + v2; }