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authorScott Soule Cheloha <cheloha@cvs.openbsd.org>2022-11-19 16:23:49 +0000
committerScott Soule Cheloha <cheloha@cvs.openbsd.org>2022-11-19 16:23:49 +0000
commit80ed729e08f13b4c92d3f73e4c0091003c978f39 (patch)
treedc7aaf30342c6fc021fde87bd188af6852e18406 /sbin/route/route.8
parent328894c4a068dfbe71c693ce00c494c8cf96db65 (diff)
mips64, loongson, octeon: switch to clockintr
- Remove mips64-specific clock interrupt scheduling bits from cpu_info. - Add missing tick_nsec initialization to cpu_initclocks(). - Disable the glxclk interrupt clock on loongson. visa@/miod@ say it can be removed later if it isn't useful for anything else. - Wire up cp0_intrclock. Notes: - The loongson apm_suspend() changes are untested, but deraadt@ claims APM suspend/resume on loongson doesn't work anyway. - loongson and octeon now have a randomized statclock(), stathz = hz. With input from miod@, visa@. Tested by miod@, visa@. Link: https://marc.info/?l=openbsd-tech&m=166776379603497&w=2 ok visa@ mlarkin@
Diffstat (limited to 'sbin/route/route.8')
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