Tolerate difference in some of the features advertised by the

ID_AA64PFR0_EL1 register across cores.  The CSV2/CSV3 features are handled
on a per-core basis so it is fine if they are different.  And we only
support 64-bit userland so it is fine if the EL0/EL1/EL2/EL3 fields are
different too.

This prevents us from printing a warning on the Rockchip RK3588 SoC which
combines Cortex-A55 with Cortex-A76 that implement a sightly different
feature set.

ok deraadt@, mlarkin@

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