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authorAlexander Bluhm <bluhm@cvs.openbsd.org>2021-09-01 09:50:22 +0000
committerAlexander Bluhm <bluhm@cvs.openbsd.org>2021-09-01 09:50:22 +0000
commite49f1d0b9fe28e5d6c615146f2628754fa0ada71 (patch)
treec4697e13a68ba2f31a6c327173af870a18d77ae9 /sys/arch/amd64/include/atomic.h
parent6738c2d19f88a6372e96d982149d05c57b97a55f (diff)
Older AMD CPUs that do not support IBRS need an lfence after ret
to stop speculation. This seems to be necessary when the branch predictor hits the ret for the first time. In their white paper to mitigate speculation attacks, AMD's retpoline example has an explicit lfence. Adjust our retpoline assembly macro in the kernel. OK guenther@ mortimer@ deraadt@
Diffstat (limited to 'sys/arch/amd64/include/atomic.h')
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