Page Attribute Tables (PAT) support for x86.

PAT allows setting per-mapping cachability bits. Our main interest in it
for write combining mappings so we do not have to rely so heaviliy on
mtrrs (which are stupidly set up on more and more machines). MD flags to
pmap allow setting these bits (which bus_space now uses for PREFETCHABLE
maps), if a vm page has a bit set, then we will use WC for all mappings
of a page (used for userland mappings). We also check for known errata
and fall back to UC- mappings in that case.

comments from kettenis@, tedu@ and william@. kettenis@, tedu@ ok.

2 files changed, 20 insertions, 10 deletions

diff --git a/sys/arch/amd64/include/pmap.h b/sys/arch/amd64/include/pmap.h
index 29b45bfb562..6eacd435fa7 100644
--- a/sys/arch/amd64/include/pmap.h
+++ b/sys/arch/amd64/include/pmap.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.h,v 1.31 2010/04/22 07:55:02 jasper Exp $	*/
+/*	$OpenBSD: pmap.h,v 1.32 2010/05/08 16:54:07 oga Exp $	*/
 /*	$NetBSD: pmap.h,v 1.1 2003/04/26 18:39:46 fvdl Exp $	*/
 
 /*
@@ -331,12 +331,14 @@ struct pmap {
  */
 #define PMAP_PA_MASK	~((paddr_t)PAGE_MASK) /* to remove the flags */
 #define	PMAP_NOCACHE	0x1 /* set the non-cacheable bit. */
+#define	PMAP_WC		0x2 /* set page write combining. */
 
 /*
  * We keep mod/ref flags in struct vm_page->pg_flags.
  */
-#define PG_PMAP_MOD	PG_PMAP0
-#define PG_PMAP_REF	PG_PMAP1
+#define	PG_PMAP_MOD	PG_PMAP0
+#define	PG_PMAP_REF	PG_PMAP1
+#define	PG_PMAP_WC      PG_PMAP2
 
 /*
  * for each managed physical page we maintain a list of <PMAP,VA>'s
diff --git a/sys/arch/amd64/include/pte.h b/sys/arch/amd64/include/pte.h
index 16d51cf4fce..c8431fd1fb0 100644
--- a/sys/arch/amd64/include/pte.h
+++ b/sys/arch/amd64/include/pte.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pte.h,v 1.6 2010/04/20 19:22:06 oga Exp $	*/
+/*	$OpenBSD: pte.h,v 1.7 2010/05/08 16:54:07 oga Exp $	*/
 /*	$NetBSD: pte.h,v 1.1 2003/04/26 18:39:47 fvdl Exp $	*/
 
 /*
@@ -110,16 +110,24 @@ typedef u_int64_t pt_entry_t;		/* PTE */
 #define	PG_N		0x0000000000000010UL	/* non-cacheable */
 #define	PG_U		0x0000000000000020UL	/* used */
 #define	PG_M		0x0000000000000040UL	/* modified */
-#define PG_PS		0x0000000000000080UL	/* 2MB page size */
-#define PG_G		0x0000000000000100UL	/* not flushed */
-#define PG_AVAIL1	0x0000000000000200UL
-#define PG_AVAIL2	0x0000000000000400UL
-#define PG_AVAIL3	0x0000000000000800UL
-#define PG_NX		0x8000000000000000UL	/* non-executable */
+#define	PG_PAT		0x0000000000000080UL	/* PAT bit. (on pte) */
+#define	PG_PS		0x0000000000000080UL	/* 2MB page size (on pde) */
+#define	PG_G		0x0000000000000100UL	/* not flushed */
+#define	PG_AVAIL1	0x0000000000000200UL
+#define	PG_AVAIL2	0x0000000000000400UL
+#define	PG_AVAIL3	0x0000000000000800UL
+#define	PG_PATLG	0x0000000000001000UL	/* PAT on large pages */
+#define	PG_NX		0x8000000000000000UL	/* non-executable */
 #define	PG_FRAME	0x000ffffffffff000UL
 
 #define	PG_LGFRAME	0x000fffffffc00000UL	/* large (2M) page frame mask */
 
+/* Cacheability bits when we are using PAT */
+#define	PG_WB		(0)		/* The default */
+#define	PG_WC		(PG_WT)		/* WT and CD is WC */
+#define	PG_UCMINUS	(PG_N)		/* UC but mtrr can override */
+#define	PG_UC		(PG_WT | PG_N)	/* hard UC */
+
 /*
  * short forms of protection codes
  */