diff options
| author | Mike Larkin <mlarkin@cvs.openbsd.org> | 2016-06-22 07:22:01 +0000 |
|---|---|---|
| committer | Mike Larkin <mlarkin@cvs.openbsd.org> | 2016-06-22 07:22:01 +0000 |
| commit | f00fd9c5abd4488973635a6952f2278bcac78efb (patch) | |
| tree | 36250ea68a76257fd25dc721a645bade5f48645f /sys/arch/amd64 | |
| parent | d59cb32ccd44b1b826afca30b1875d2cda08daad (diff) | |
Identify UMIP feature, if available.
ok millert, kettenis, deraadt
Diffstat (limited to 'sys/arch/amd64')
| -rw-r--r-- | sys/arch/amd64/amd64/identcpu.c | 3 | ||||
| -rw-r--r-- | sys/arch/amd64/include/specialreg.h | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/sys/arch/amd64/amd64/identcpu.c b/sys/arch/amd64/amd64/identcpu.c index 777d6450931..839c4d0533d 100644 --- a/sys/arch/amd64/amd64/identcpu.c +++ b/sys/arch/amd64/amd64/identcpu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: identcpu.c,v 1.72 2016/02/03 03:25:08 guenther Exp $ */ +/* $OpenBSD: identcpu.c,v 1.73 2016/06/22 07:22:00 mlarkin Exp $ */ /* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */ /* @@ -193,6 +193,7 @@ const struct { }, cpu_seff0_ecxfeatures[] = { { SEFF0ECX_PREFETCHWT1, "PREFETCHWT1" }, { SEFF0ECX_AVX512VBMI, "AVX512VBMI" }, + { SEFF0ECX_UMIP, "UMIP" }, { SEFF0ECX_PKU, "PKU" }, }, cpu_tpm_eaxfeatures[] = { { TPM_SENSOR, "SENSOR" }, diff --git a/sys/arch/amd64/include/specialreg.h b/sys/arch/amd64/include/specialreg.h index 43169338e8b..c9a6e065be7 100644 --- a/sys/arch/amd64/include/specialreg.h +++ b/sys/arch/amd64/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.43 2016/04/26 15:57:09 mlarkin Exp $ */ +/* $OpenBSD: specialreg.h,v 1.44 2016/06/22 07:22:00 mlarkin Exp $ */ /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ @@ -90,6 +90,7 @@ #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ +#define CR4_UMIP 0x00000800 /* user mode instruction prevention */ #define CR4_VMXE 0x00002000 /* enable virtual machine operation */ #define CR4_SMXE 0x00004000 /* enable safe mode operation */ #define CR4_FSGSBASE 0x00010000 /* enable {RD,WR}{FS,GS}BASE ops */ @@ -210,6 +211,7 @@ /* SEFF ECX bits */ #define SEFF0ECX_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */ #define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */ +#define SEFF0ECX_UMIP 0x00000004 /* UMIP support */ #define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ /* |