spelling/grammar cleanups

jolan drahn uwe dlg ok

6 files changed, 34 insertions, 34 deletions

diff --git a/sys/arch/arm/xscale/pxa2x0_apm.c b/sys/arch/arm/xscale/pxa2x0_apm.c
index bf01f06e324..9a2d908c118 100644
--- a/sys/arch/arm/xscale/pxa2x0_apm.c
+++ b/sys/arch/arm/xscale/pxa2x0_apm.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_apm.c,v 1.10 2005/03/30 14:24:39 dlg Exp $	*/
+/*	$OpenBSD: pxa2x0_apm.c,v 1.11 2005/04/06 01:31:05 pascoe Exp $	*/
 
 /*-
  * Copyright (c) 2001 Alexander Guy.  All rights reserved.
@@ -78,7 +78,7 @@ int	apm_userstandbys;
 int	apm_suspends;
 int	apm_battlow;
 
-/* battery percentage at where we get verbose in our warnings.  This
+/* battery percentage at which we get verbose in our warnings.  This
    value can be changed using sysctl(8), value machdep.apmwarn.
    Setting it to zero kills all warnings */
 int	cpu_apmwarn = 10;
@@ -118,7 +118,7 @@ struct filterops apmread_filtops =
 #define	SCFLAG_OWRITE	(1 << 1)
 #define	SCFLAG_OPEN	(SCFLAG_OREAD|SCFLAG_OWRITE)
 
-/* This structure must be keept in sync with pxa2x0_apm_asm.S. */
+/* This structure must be kept in sync with pxa2x0_apm_asm.S. */
 struct pxa2x0_memcfg {
 	/* SDRAM refresh */
 	u_int32_t mdrefr_high;		/* 0x00 */
@@ -331,7 +331,7 @@ apm_get_event(struct pxa2x0_apm_softc *sc, u_long *event_type)
 {
 	struct	apm_power_info power;
 
-	/* Periodic callbacks could be replaced with a machine-dependant
+	/* Periodic callbacks could be replaced with a machine-dependent
 	   get_event function. */
 	if (sc->sc_periodic_check != NULL)
 		sc->sc_periodic_check(sc);
@@ -1269,7 +1269,7 @@ pxa2x0_pi2c_print(struct pxa2x0_apm_softc *sc)
 
 	(void)pxa2x0_pi2c_getvoltage(sc->sc_iot, sc->sc_pm_ioh, &value);
 	printf("xscale core voltage: %s\n", value == PI2C_VOLTAGE_HIGH ?
-	    "high" : (value == PI2C_VOLTAGE_LOW ? "low" : "unkown"));
+	    "high" : (value == PI2C_VOLTAGE_LOW ? "low" : "unknown"));
 }
 #endif
 
diff --git a/sys/arch/arm/xscale/pxa2x0_intr.c b/sys/arch/arm/xscale/pxa2x0_intr.c
index e5586ece8bd..6309128cb18 100644
--- a/sys/arch/arm/xscale/pxa2x0_intr.c
+++ b/sys/arch/arm/xscale/pxa2x0_intr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_intr.c,v 1.9 2005/02/28 22:10:01 drahn Exp $ */
+/*	$OpenBSD: pxa2x0_intr.c,v 1.10 2005/04/06 01:31:05 pascoe Exp $ */
 /*	$NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $	*/
 
 /*
@@ -196,7 +196,7 @@ pxa2x0_irq_handler(void *arg)
 	irqbits = read_icu(SAIPIC_IP);
 
 	while ((irqno = find_first_bit(irqbits)) >= 0) {
-		/* XXX: Shuould we handle IRQs in priority order? */
+		/* XXX: Should we handle IRQs in priority order? */
 
 		/* raise spl to stop interrupts of lower priorities */
 		if (saved_spl_level < extirq_level[irqno])
@@ -262,10 +262,10 @@ pxa2x0_update_intr_masks(int irqno, int level)
 		pxa2x0_imask[i] |= mask; /* Enable interrupt at lower level */
 
 	for( ; i < NIPL-1; ++i)
-		pxa2x0_imask[i] &= ~mask; /* Disable itnerrupt at upper level */
+		pxa2x0_imask[i] &= ~mask; /* Disable interrupt at upper level */
 
 	/*
-	 * Enforce a heirarchy that gives "slow" device (or devices with
+	 * Enforce a hierarchy that gives "slow" device (or devices with
 	 * limited input buffer space/"real-time" requirements) a better
 	 * chance at not dropping data.
 	 */
@@ -491,7 +491,7 @@ pxa2x0_intr_disestablish(void *cookie)
 }
 
 /*
- * Glue for drivers of sa11x0 compatible integrated logics.
+ * Glue for drivers of sa11x0 compatible integrated logic.
  */
 void *
 sa11x0_intr_establish(sa11x0_chipset_tag_t ic, int irq, int type, int level,
@@ -527,7 +527,7 @@ pxa2x0_splx(int new)
 	pxa2x0_setipl(new);
 	restore_interrupts(psw);
 
-	/* If there are software interrupts to process, do it. */
+	/* If there are pending software interrupts, process them. */
 	if (softint_pending & pxa2x0_imask[current_spl_level])
 		pxa2x0_do_pending();
 }
diff --git a/sys/arch/arm/xscale/pxa2x0_lcd.h b/sys/arch/arm/xscale/pxa2x0_lcd.h
index 6ad1c2b92c5..3ad91375355 100644
--- a/sys/arch/arm/xscale/pxa2x0_lcd.h
+++ b/sys/arch/arm/xscale/pxa2x0_lcd.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_lcd.h,v 1.7 2005/01/21 16:22:34 miod Exp $ */
+/*	$OpenBSD: pxa2x0_lcd.h,v 1.8 2005/04/06 01:31:05 pascoe Exp $ */
 /* $NetBSD: pxa2x0_lcd.h,v 1.2 2003/06/17 09:43:14 bsh Exp $ */
 /*
  * Copyright (c) 2002  Genetec Corporation.  All rights reserved.
@@ -40,14 +40,14 @@
 #include <dev/rasops/rasops.h>
 #include <machine/bus.h>
 
-/* LCD Contoroller */
+/* LCD Controller */
 
 struct	lcd_dma_descriptor {
 	uint32_t	fdadr;	/* next frame descriptor */
 	uint32_t	fsadr;	/* frame start address */
 	uint32_t	fidr;	/* frame ID */
 	uint32_t	ldcmd;	/* DMA command */
-#define	LDCMD_PAL	(1U<<26)	/* Pallet buffer */
+#define	LDCMD_PAL	(1U<<26)	/* Palette buffer */
 #define LDCMD_SOFINT	(1U<<22)	/* Start of Frame interrupt */
 #define LDCMD_EOFINT	(1U<<21)	/* End of Frame interrupt */
 };
@@ -110,7 +110,7 @@ struct lcd_panel_geometry {
 	short pixel_clock_div;		/* pixel clock divider */
 	short ac_bias;			/* AC bias pin frequency */
 
-	short hsync_pulse_width;	/* Horizontao sync pulse width */
+	short hsync_pulse_width;	/* Horizontal sync pulse width */
 	short beg_line_wait;		/* beginning of line wait (BLW) */
 	short end_line_wait;		/* end of line pxel wait (ELW) */
 
diff --git a/sys/arch/arm/xscale/pxa2x0_pcic.c b/sys/arch/arm/xscale/pxa2x0_pcic.c
index 3a2d979d793..3100ecc1c59 100644
--- a/sys/arch/arm/xscale/pxa2x0_pcic.c
+++ b/sys/arch/arm/xscale/pxa2x0_pcic.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pxa2x0_pcic.c,v 1.11 2005/03/09 22:11:10 drahn Exp $ */
+/* $OpenBSD: pxa2x0_pcic.c,v 1.12 2005/04/06 01:31:05 pascoe Exp $ */
 /*
  * Copyright (c) 2005 Dale Rahn <drahn@openbsd.org>
  *
@@ -77,7 +77,7 @@ void	pxapcic_detach_card(struct pxapcic_socket *h, int flags);
 
 int pxapcic_intr_detect(void *arg);
 
-/* DONT CONFIGURE CF slot 1 for now */
+/* DON'T CONFIGURE CF slot 1 for now */
 #define NUM_CF_CARDS 2
 
 struct cfattach pxapcic_ca = {
@@ -117,7 +117,7 @@ pxapcic_mem_alloc(pch, size, pmh)
 {
 	struct pxapcic_socket *so = pch;
 
-	/* All we need is bus space tag */
+	/* All we need is the bus space tag */
 	memset(pmh, 0, sizeof(*pmh));
 	pmh->memt = so->sc->sc_iot;
 	return (0);
@@ -441,7 +441,7 @@ pxapcic_event_thread(void *arg)
 
 		(void) tsleep(sock, PWAIT, "pxapcicev", 0);
 
-		/* sleep .25s to avoid chatterling interrupts */
+		/* sleep .25s to avoid chattering interrupts */
 		(void) tsleep((caddr_t)sock, PWAIT,
 		    "pxapcicss", hz/4);
 
@@ -530,7 +530,7 @@ pxapcic_create_event_thread(void *arg)
 
 	csr = bus_space_read_2(sc->sc_iot, sock->scooph, SCOOP_REG_CSR);
 
-	/* if there's a card there, then attach it  */
+	/* if there's a card there, attach it  */
 
 	switch (csr & SCP_CSR_MISSING) {
 	case 0: /* PRESENT */
@@ -627,7 +627,7 @@ pxapcic_attach(struct device *parent, struct device *self, void *aux)
 		}
 		error = bus_space_map(iot, pa, size, 0, &scooph);
 		if (error) {
-			printf ("%s%d:failed to map memory %x for scoop\n",
+			printf ("%s%d: failed to map memory %x for scoop\n",
 			    sc->sc_dev.dv_xname, i, pa);
 			    continue;
 		}
diff --git a/sys/arch/arm/xscale/pxa2x0reg.h b/sys/arch/arm/xscale/pxa2x0reg.h
index f7ac066886c..8b8719b78a5 100644
--- a/sys/arch/arm/xscale/pxa2x0reg.h
+++ b/sys/arch/arm/xscale/pxa2x0reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0reg.h,v 1.15 2005/04/05 13:12:05 pascoe Exp $ */
+/*	$OpenBSD: pxa2x0reg.h,v 1.16 2005/04/06 01:31:05 pascoe Exp $ */
 /* $NetBSD: pxa2x0reg.h,v 1.4 2003/06/11 20:43:01 scw Exp $ */
 
 /*
@@ -304,7 +304,7 @@ struct pxa2x0_dma_desc {
 #define  CCCR_RUN_X16	 (16<<0) /* 208Mhz, 104/208Mhz mem, 104Mhz LCD */
 
 #define CLKMAN_CKEN	0x04	/* Clock Enable Register */
-#define CLKMAN_OSCC	0x08	/* Osillcator Configuration Register */
+#define CLKMAN_OSCC	0x08	/* Oscillator Configuration Register */
 
 #define CCCR_N_SHIFT	7
 #define CCCR_N_MASK	(0x07<<CCCR_N_SHIFT)
@@ -464,9 +464,9 @@ struct pxa2x0_dma_desc {
 #define  MDREFR_K1FREE	(1<<24)	/* SDCLK1 free run */
 #define  MDREFR_K2FREE	(1<<25)	/* SDCLK2 free run */
 
-#define MEMCTL_MSC0	0x08	/* Asychronous Statis memory Control CS[01] */
-#define MEMCTL_MSC1	0x0c	/* Asychronous Statis memory Control CS[23] */
-#define MEMCTL_MSC2	0x10	/* Asychronous Statis memory Control CS[45] */
+#define MEMCTL_MSC0	0x08	/* Asynchronous Static memory Control CS[01] */
+#define MEMCTL_MSC1	0x0c	/* Asynchronous Static memory Control CS[23] */
+#define MEMCTL_MSC2	0x10	/* Asynchronous Static memory Control CS[45] */
 #define  MSC_RBUFF_SHIFT 15	/* return data buffer */
 #define  MSC_RBUFF	(1<<MSC_RBUFF_SHIFT)
 #define  MSC_RRR_SHIFT   12  	/* recovery time */
@@ -524,7 +524,7 @@ struct pxa2x0_dma_desc {
 #define  LCCR0_RDSTM	(1U<<23) /* Read Status Interrupt Mask */
 #define  LCCR0_CMDIM	(1U<<24) /* Command Interrupt Mask */
 #define  LCCR0_OUC	(1U<<25) /* Overlay Underlay Control */
-#define  LCCR0_LDDALT	(1U<<26) /* LDD Alernate Mapping Control Bit */
+#define  LCCR0_LDDALT	(1U<<26) /* LDD Alternate Mapping Control Bit */
 
 #define  LCCR0_IMASK	(LCCR0_LDM|LCCR0_SFM|LCCR0_IUM|LCCR0_EFM|LCCR0_QDM|LCCR0_BM|LCCR0_OUM)
 
@@ -594,7 +594,7 @@ struct pxa2x0_dma_desc {
 #define  CMDAT_WRITE		(1<<3) /* 1=write 0=read operation */
 #define  CMDAT_STREAM_BLOCK	(1<<4) /* stream mode */
 #define  CMDAT_BUSY		(1<<5) /* busy signal is expected */
-#define  CMDAT_INIT		(1<<6) /* preceede command with 80 clocks */
+#define  CMDAT_INIT		(1<<6) /* precede command with 80 clocks */
 #define  CMDAT_MMC_DMA_EN	(1<<7) /* DMA enable */
 #define MMC_RESTO	0x14	/* expected response time out */
 #define MMC_RDTO 	0x18	/* expected data read time out */
@@ -674,13 +674,13 @@ struct pxa2x0_dma_desc {
 
 /* address to access codec registers */
 #define AC97_PRIAUDIO	0x0200	/* Primary audio codec */
-#define AC97_SECAUDIO	0x0300	/* Secondary autio codec */
+#define AC97_SECAUDIO	0x0300	/* Secondary audio codec */
 #define AC97_PRIMODEM	0x0400	/* Primary modem codec */
 #define AC97_SECMODEM	0x0500	/* Secondary modem codec */
 #define	AC97_CODEC_BASE(c)	(AC97_PRIAUDIO + ((c) * 0x100))
 
 /*
- * USB device controller differs between pxa255 and pxa27x, defined seperately
+ * USB device controller differs between pxa255 and pxa27x, defined separately
  */
 
 /*
@@ -688,7 +688,7 @@ struct pxa2x0_dma_desc {
  */
 #define USBHC_STAT	0x0060	/* UHC Status Register */
 #define  USBHC_STAT_RWUE	(1<<7)	/* HCI Remote Wake-Up Event */
-#define  USBHC_STAT_HBA		(1<<8)	/* HCI Buffer Acrive */
+#define  USBHC_STAT_HBA		(1<<8)	/* HCI Buffer Active */
 #define  USBHC_STAT_HTA		(1<<10)	/* HCI Transfer Abort */
 #define  USBHC_STAT_UPS1	(1<<11)	/* USB Power Sense Port 1 */
 #define  USBHC_STAT_UPS2	(1<<12)	/* USB Power Sense Port 2 */
diff --git a/sys/arch/arm/xscale/pxa2x0var.h b/sys/arch/arm/xscale/pxa2x0var.h
index 81c9d49b25e..309ddf81ad4 100644
--- a/sys/arch/arm/xscale/pxa2x0var.h
+++ b/sys/arch/arm/xscale/pxa2x0var.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0var.h,v 1.3 2005/01/12 17:14:37 uwe Exp $ */
+/*	$OpenBSD: pxa2x0var.h,v 1.4 2005/04/06 01:31:06 pascoe Exp $ */
 /* $NetBSD: pxa2x0var.h,v 1.2 2003/06/05 13:48:28 scw Exp $ */
 
 /*
@@ -72,8 +72,8 @@ extern void pxa2x0_turbo_mode(int);
 extern int pxa2x0_i2c_master_tx( int, uint8_t *, int );
 
 /*
- * Probe the memory controller to deterimine which SDRAM are
- * populated, and what size of SDRAM is present in each bank.
+ * Probe the memory controller to determine which SDRAM banks
+ * are populated, and what size SDRAM is present in each bank.
  *
  * This routine should be called from a port's initarm()
  * function, with the first parameter set to the address