Adjust OpenBSD/arm64 files with FreeBSD origin to show the upstream

revision.  While there, update a few of those files.

Prompted by mikeb@.

8 files changed, 438 insertions, 76 deletions

diff --git a/sys/arch/arm64/arm64/locore.S b/sys/arch/arm64/arm64/locore.S
index 9fb7f252631..eeb82b1a761 100644
--- a/sys/arch/arm64/arm64/locore.S
+++ b/sys/arch/arm64/arm64/locore.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.S,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
+/* $OpenBSD: locore.S,v 1.2 2016/12/18 14:40:25 patrick Exp $ */
 /*-
  * Copyright (c) 2012-2014 Andrew Turner
  * All rights reserved.
@@ -24,7 +24,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/arm64/arm64/locore.S 282867 2015-05-13 18:57:03Z zbb $
  */
 
 #include "assym.h"
@@ -562,7 +562,7 @@ mair:
 	.quad	MAIR_ATTR(0x00, 0) | MAIR_ATTR(0x44, 1) | MAIR_ATTR(0xff, 2)
 tcr:
 	.quad (TCR_TxSZ(64 - VIRT_BITS) | TCR_ASID_16 | TCR_TG1_4K | \
-		TCR_SH0(3)|TCR_SH1(3)|TCR_ORGNx(1)|TCR_IRGNx(1))
+	    TCR_CACHE_ATTRS | TCR_SMP_ATTRS)
 sctlr_set:
 	/* Bits to set */
 	.quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \
diff --git a/sys/arch/arm64/arm64/support.S b/sys/arch/arm64/arm64/support.S
index 7167ff2b0a9..cd6950170cc 100644
--- a/sys/arch/arm64/arm64/support.S
+++ b/sys/arch/arm64/arm64/support.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: support.S,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
+/* $OpenBSD: support.S,v 1.2 2016/12/18 14:40:25 patrick Exp $ */
 /*-
  * Copyright (c) 2014 Andrew Turner
  * Copyright (c) 2014-2015 The FreeBSD Foundation
@@ -31,8 +31,12 @@
  */
 
 #include <machine/asm.h>
+#if 0
+__FBSDID("$FreeBSD: head/sys/arm64/arm64/support.S 297615 2016-04-06 14:08:10Z andrew $");
+#endif
 
 #include <machine/setjmp.h>
+#include <machine/vmparam.h>
 
 #include "assym.h"
 
@@ -41,6 +45,7 @@
  */
 ENTRY(fsu_fault)
 	SET_FAULT_HANDLER(xzr, x1)	/* Reset the handler function */
+fsu_fault_nopcb:
 	mov	x0, #-1
 	ret
 END(fsu_fault)
@@ -49,6 +54,9 @@ END(fsu_fault)
  * int casueword32(volatile uint32_t *, uint32_t, uint32_t *, uint32_t)
  */
 ENTRY(casueword32)
+	ldr	x4, =(VM_MAXUSER_ADDRESS-3)
+	cmp	x0, x4
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x4)	/* And set it */
 1:	ldxr	w4, [x0]		/* Load-exclusive the data */
@@ -56,9 +64,9 @@ ENTRY(casueword32)
 	b.ne	2f			/* Not equal, exit */
 	stxr	w5, w3, [x0]		/* Store the new data */
 	cbnz	w5, 1b			/* Retry on failure */
-	ldrb	w0, [x0]		/* Try loading the data */
 2:	SET_FAULT_HANDLER(xzr, x5)	/* Reset the fault handler */
 	str	w4, [x2]		/* Store the read data */
+	mov	x0, #0			/* Success */
 	ret				/* Return */
 END(casueword32)
 
@@ -66,6 +74,9 @@ END(casueword32)
  * int casueword(volatile u_long *, u_long, u_long *, u_long)
  */
 ENTRY(casueword)
+	ldr	x4, =(VM_MAXUSER_ADDRESS-7)
+	cmp	x0, x4
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x4)	/* And set it */
 1:	ldxr	x4, [x0]		/* Load-exclusive the data */
@@ -73,9 +84,9 @@ ENTRY(casueword)
 	b.ne	2f			/* Not equal, exit */
 	stxr	w5, x3, [x0]		/* Store the new data */
 	cbnz	w5, 1b			/* Retry on failure */
-	ldrb	w0, [x0]		/* Try loading the data */
 2:	SET_FAULT_HANDLER(xzr, x5)	/* Reset the fault handler */
 	str	x4, [x2]		/* Store the read data */
+	mov	x0, #0			/* Success */
 	ret				/* Return */
 END(casueword)
 
@@ -83,6 +94,9 @@ END(casueword)
  * int fubyte(volatile const void *)
  */
 ENTRY(fubyte)
+	ldr	x1, =VM_MAXUSER_ADDRESS
+	cmp	x0, x1
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x1)	/* And set it */
 	ldrb	w0, [x0]		/* Try loading the data */
@@ -94,6 +108,9 @@ END(fubyte)
  * int fuword(volatile const void *)
  */
 ENTRY(fuword16)
+	ldr	x1, =(VM_MAXUSER_ADDRESS-1)
+	cmp	x0, x1
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x1)	/* And set it */
 	ldrh	w0, [x0]		/* Try loading the data */
@@ -105,6 +122,9 @@ END(fuword16)
  * int32_t fueword32(volatile const void *, int32_t *)
  */
 ENTRY(fueword32)
+	ldr	x2, =(VM_MAXUSER_ADDRESS-3)
+	cmp	x0, x2
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x2)	/* And set it */
 	ldr	w0, [x0]		/* Try loading the data */
@@ -120,6 +140,9 @@ END(fueword32)
  */
 ENTRY(fueword)
 EENTRY(fueword64)
+	ldr	x2, =(VM_MAXUSER_ADDRESS-7)
+	cmp	x0, x2
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x2)	/* And set it */
 	ldr	x0, [x0]		/* Try loading the data */
@@ -134,6 +157,9 @@ END(fueword)
  * int subyte(volatile void *, int)
  */
 ENTRY(subyte)
+	ldr	x2, =VM_MAXUSER_ADDRESS
+	cmp	x0, x2
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x2)	/* And set it */
 	strb	w1, [x0]		/* Try storing the data */
@@ -146,6 +172,9 @@ END(subyte)
  * int suword16(volatile void *, int)
  */
 ENTRY(suword16)
+	ldr	x2, =(VM_MAXUSER_ADDRESS-1)
+	cmp	x0, x2
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x2)	/* And set it */
 	strh	w1, [x0]		/* Try storing the data */
@@ -158,6 +187,9 @@ END(suword16)
  * int suword32(volatile void *, int)
  */
 ENTRY(suword32)
+	ldr	x2, =(VM_MAXUSER_ADDRESS-3)
+	cmp	x0, x2
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x2)	/* And set it */
 	str	w1, [x0]		/* Try storing the data */
@@ -171,6 +203,9 @@ END(suword32)
  */
 ENTRY(suword)
 EENTRY(suword64)
+	ldr	x2, =(VM_MAXUSER_ADDRESS-7)
+	cmp	x0, x2
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_fault		/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x2)	/* And set it */
 	str	x1, [x0]		/* Try storing the data */
@@ -199,6 +234,9 @@ END(fsu_fault)
  * int fuswintr(void *)
  */
 ENTRY(fuswintr)
+	ldr	x1, =(VM_MAXUSER_ADDRESS-3)
+	cmp	x0, x1
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_intr_fault	/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x1)	/* And set it */
 	ldr	w0, [x0]		/* Try loading the data */
@@ -210,6 +248,9 @@ END(fuswintr)
  * int suswintr(void *base, int word)
  */
 ENTRY(suswintr)
+	ldr	x2, =(VM_MAXUSER_ADDRESS-3)
+	cmp	x0, x2
+	b.cs	fsu_fault_nopcb
 	adr	x6, fsu_intr_fault	/* Load the fault handler */
 	SET_FAULT_HANDLER(x6, x2)	/* And set it */
 	str	w1, [x0]		/* Try storing the data */
@@ -221,7 +262,7 @@ END(suswintr)
 ENTRY(setjmp)
 	/* Store the stack pointer */
 	mov	x8, sp
-	str	x8, [x0]
+	str	x8, [x0], #8
 
 	/* Store the general purpose registers and lr */
 	stp	x19, x20, [x0], #16
@@ -253,3 +294,38 @@ ENTRY(longjmp)
 	mov	x0, x1
 	ret
 END(longjmp)
+
+/*
+ * pagezero, simple implementation
+ */
+ENTRY(pagezero_simple)
+	add	x1, x0, #PAGE_SIZE
+
+1:
+	stp	xzr, xzr, [x0], #0x10
+	stp	xzr, xzr, [x0], #0x10
+	stp	xzr, xzr, [x0], #0x10
+	stp	xzr, xzr, [x0], #0x10
+	cmp	x0, x1
+	b.ne	1b
+	ret
+
+END(pagezero_simple)
+
+/*
+ * pagezero, cache assisted
+ */
+ENTRY(pagezero_cache)
+	add	x1, x0, #PAGE_SIZE
+
+	ldr	x2, =dczva_line_size
+	ldr	x2, [x2]
+
+1:
+	dc	zva, x0
+	add	x0, x0, x2
+	cmp	x0, x1
+	b.ne	1b
+	ret
+
+END(pagezero_cache)
diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h
index f6e99ea0130..4cad9e6bfed 100644
--- a/sys/arch/arm64/include/armreg.h
+++ b/sys/arch/arm64/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
+/* $OpenBSD: armreg.h,v 1.2 2016/12/18 14:40:25 patrick Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -28,12 +28,14 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $
  */
 
 #ifndef _MACHINE_ARMREG_H_
 #define	_MACHINE_ARMREG_H_
 
+#define	INSN_SIZE		4
+
 #define	READ_SPECIALREG(reg)						\
 ({	uint64_t val;							\
 	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (val));	\
@@ -42,6 +44,13 @@
 #define	WRITE_SPECIALREG(reg, val)					\
 	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)val))
 
+/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
+#define	CNTHCTL_EVNTI_MASK	(0xf << 4) /* Bit to trigger event stream */
+#define	CNTHCTL_EVNTDIR		(1 << 3) /* Control transition trigger bit */
+#define	CNTHCTL_EVNTEN		(1 << 2) /* Enable event stream */
+#define	CNTHCTL_EL1PCEN		(1 << 1) /* Allow EL0/1 physical timer access */
+#define	CNTHCTL_EL1PCTEN	(1 << 0) /*Allow EL0/1 physical counter access*/
+
 /* CPACR_EL1 */
 #define	CPACR_FPEN_MASK		(0x3 << 20)
 #define	 CPACR_FPEN_TRAP_ALL1	(0x0 << 20) /* Traps from EL0 and EL1 */
@@ -58,6 +67,12 @@
 #define	CTR_ILINE_MASK		(0xf << CTR_ILINE_SHIFT)
 #define	CTR_ILINE_SIZE(reg)	(((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
 
+/* DCZID_EL0 - Data Cache Zero ID register */
+#define DCZID_DZP		(1 << 4) /* DC ZVA prohibited if non-0 */
+#define DCZID_BS_SHIFT		0
+#define DCZID_BS_MASK		(0xf << DCZID_BS_SHIFT)
+#define	DCZID_BS_SIZE(reg)	(((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
+
 /* ESR_ELx */
 #define	ESR_ELx_ISS_MASK	0x00ffffff
 #define	 ISS_INSN_FnV		(0x01 << 10)
@@ -75,7 +90,33 @@
 #define	 ISS_DATa_CM		(0x01 << 8)
 #define	 ISS_INSN_S1PTW		(0x01 << 7)
 #define	 ISS_DATa_WnR		(0x01 << 6)
-#define	 ISS_DATA_DFSC_MASK	(0x1f << 0)
+#define	 ISS_DATA_DFSC_MASK	(0x3f << 0)
+#define	 ISS_DATA_DFSC_ASF_L0	(0x00 << 0)
+#define	 ISS_DATA_DFSC_ASF_L1	(0x01 << 0)
+#define	 ISS_DATA_DFSC_ASF_L2	(0x02 << 0)
+#define	 ISS_DATA_DFSC_ASF_L3	(0x03 << 0)
+#define	 ISS_DATA_DFSC_TF_L0	(0x04 << 0)
+#define	 ISS_DATA_DFSC_TF_L1	(0x05 << 0)
+#define	 ISS_DATA_DFSC_TF_L2	(0x06 << 0)
+#define	 ISS_DATA_DFSC_TF_L3	(0x07 << 0)
+#define	 ISS_DATA_DFSC_AFF_L1	(0x09 << 0)
+#define	 ISS_DATA_DFSC_AFF_L2	(0x0a << 0)
+#define	 ISS_DATA_DFSC_AFF_L3	(0x0b << 0)
+#define	 ISS_DATA_DFSC_PF_L1	(0x0d << 0)
+#define	 ISS_DATA_DFSC_PF_L2	(0x0e << 0)
+#define	 ISS_DATA_DFSC_PF_L3	(0x0f << 0)
+#define	 ISS_DATA_DFSC_EXT	(0x10 << 0)
+#define	 ISS_DATA_DFSC_EXT_L0	(0x14 << 0)
+#define	 ISS_DATA_DFSC_EXT_L1	(0x15 << 0)
+#define	 ISS_DATA_DFSC_EXT_L2	(0x16 << 0)
+#define	 ISS_DATA_DFSC_EXT_L3	(0x17 << 0)
+#define	 ISS_DATA_DFSC_ECC	(0x18 << 0)
+#define	 ISS_DATA_DFSC_ECC_L0	(0x1c << 0)
+#define	 ISS_DATA_DFSC_ECC_L1	(0x1d << 0)
+#define	 ISS_DATA_DFSC_ECC_L2	(0x1e << 0)
+#define	 ISS_DATA_DFSC_ECC_L3	(0x1f << 0)
+#define	 ISS_DATA_DFSC_ALIGN	(0x21 << 0)
+#define	 ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
 #define	ESR_ELx_IL		(0x01 << 25)
 #define	ESR_ELx_EC_SHIFT	26
 #define	ESR_ELx_EC_MASK		(0x3f << 26)
@@ -86,13 +127,14 @@
 #define	 EXCP_SVC		0x15	/* SVC trap */
 #define	 EXCP_MSR		0x18	/* MSR/MRS trap */
 #define	 EXCP_INSN_ABORT_L	0x20	/* Instruction abort, from lower EL */
-#define	 EXCP_INSN_ABORT	0x21	/* Instruction abort, from same EL */
+#define	 EXCP_INSN_ABORT	0x21	/* Instruction abort, from same EL */ 
 #define	 EXCP_PC_ALIGN		0x22	/* PC alignment fault */
 #define	 EXCP_DATA_ABORT_L	0x24	/* Data abort, from lower EL */
-#define	 EXCP_DATA_ABORT	0x25	/* Data abort, from same EL */
+#define	 EXCP_DATA_ABORT	0x25	/* Data abort, from same EL */ 
 #define	 EXCP_SP_ALIGN		0x26	/* SP slignment fault */
 #define	 EXCP_TRAP_FP		0x2c	/* Trapped FP exception */
 #define	 EXCP_SERROR		0x2f	/* SError interrupt */
+#define	 EXCP_SOFTSTP_EL0	0x32	/* Software Step, from lower EL */
 #define	 EXCP_SOFTSTP_EL1	0x33	/* Software Step, from same EL */
 #define	 EXCP_WATCHPT_EL1	0x35	/* Watchpoint, from same EL */
 #define	 EXCP_BRK		0x3c	/* Breakpoint */
@@ -109,29 +151,238 @@
 /* ICC_PMR_EL1 */
 #define	ICC_PMR_EL1_PRIO_MASK	(0xFFUL)
 
+/* ICC_SGI1R_EL1 */
+#define	ICC_SGI1R_EL1_TL_MASK		0xffffUL
+#define	ICC_SGI1R_EL1_AFF1_SHIFT	16
+#define	ICC_SGI1R_EL1_SGIID_SHIFT	24
+#define	ICC_SGI1R_EL1_AFF2_SHIFT	32
+#define	ICC_SGI1R_EL1_AFF3_SHIFT	48
+#define	ICC_SGI1R_EL1_SGIID_MASK	0xfUL
+#define	ICC_SGI1R_EL1_IRM		(0x1UL << 40)
+
 /* ICC_SRE_EL1 */
 #define	ICC_SRE_EL1_SRE		(1U << 0)
 
 /* ICC_SRE_EL2 */
+#define	ICC_SRE_EL2_SRE		(1U << 0)
 #define	ICC_SRE_EL2_EN		(1U << 3)
 
+/* ID_AA64DFR0_EL1 */
+#define	ID_AA64DFR0_MASK		0xf0f0ffff
+#define	ID_AA64DFR0_DEBUG_VER_SHIFT	0
+#define	ID_AA64DFR0_DEBUG_VER_MASK	(0xf << ID_AA64DFR0_DEBUG_VER_SHIFT)
+#define	ID_AA64DFR0_DEBUG_VER(x)	((x) & ID_AA64DFR0_DEBUG_VER_MASK)
+#define	 ID_AA64DFR0_DEBUG_VER_8	(0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT)
+#define	 ID_AA64DFR0_DEBUG_VER_8_VHE	(0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT)
+#define	ID_AA64DFR0_TRACE_VER_SHIFT	4
+#define	ID_AA64DFR0_TRACE_VER_MASK	(0xf << ID_AA64DFR0_TRACE_VER_SHIFT)
+#define	ID_AA64DFR0_TRACE_VER(x)	((x) & ID_AA64DFR0_TRACE_VER_MASK)
+#define	 ID_AA64DFR0_TRACE_VER_NONE	(0x0 << ID_AA64DFR0_TRACE_VER_SHIFT)
+#define	 ID_AA64DFR0_TRACE_VER_IMPL	(0x1 << ID_AA64DFR0_TRACE_VER_SHIFT)
+#define	ID_AA64DFR0_PMU_VER_SHIFT	8
+#define	ID_AA64DFR0_PMU_VER_MASK	(0xf << ID_AA64DFR0_PMU_VER_SHIFT)
+#define	ID_AA64DFR0_PMU_VER(x)		((x) & ID_AA64DFR0_PMU_VER_MASK)
+#define	 ID_AA64DFR0_PMU_VER_NONE	(0x0 << ID_AA64DFR0_PMU_VER_SHIFT)
+#define	 ID_AA64DFR0_PMU_VER_3		(0x1 << ID_AA64DFR0_PMU_VER_SHIFT)
+#define	 ID_AA64DFR0_PMU_VER_3_1	(0x4 << ID_AA64DFR0_PMU_VER_SHIFT)
+#define	 ID_AA64DFR0_PMU_VER_IMPL	(0xf << ID_AA64DFR0_PMU_VER_SHIFT)
+#define	ID_AA64DFR0_BRPS_SHIFT		12
+#define	ID_AA64DFR0_BRPS_MASK		(0xf << ID_AA64DFR0_BRPS_SHIFT)
+#define	ID_AA64DFR0_BRPS(x)		\
+    ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
+#define	ID_AA64DFR0_WRPS_SHIFT		20
+#define	ID_AA64DFR0_WRPS_MASK		(0xf << ID_AA64DFR0_WRPS_SHIFT)
+#define	ID_AA64DFR0_WRPS(x)		\
+    ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
+#define	ID_AA64DFR0_CTX_CMPS_SHIFT	28
+#define	ID_AA64DFR0_CTX_CMPS_MASK	(0xf << ID_AA64DFR0_CTX_CMPS_SHIFT)
+#define	ID_AA64DFR0_CTX_CMPS(x)		\
+    ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
+
+/* ID_AA64ISAR0_EL1 */
+#define	ID_AA64ISAR0_MASK		0xf0fffff0
+#define	ID_AA64ISAR0_AES_SHIFT		4
+#define	ID_AA64ISAR0_AES_MASK		(0xf << ID_AA64ISAR0_AES_SHIFT)
+#define	ID_AA64ISAR0_AES(x)		((x) & ID_AA64ISAR0_AES_MASK)
+#define	 ID_AA64ISAR0_AES_NONE		(0x0 << ID_AA64ISAR0_AES_SHIFT)
+#define	 ID_AA64ISAR0_AES_BASE		(0x1 << ID_AA64ISAR0_AES_SHIFT)
+#define	 ID_AA64ISAR0_AES_PMULL		(0x2 << ID_AA64ISAR0_AES_SHIFT)
+#define	ID_AA64ISAR0_SHA1_SHIFT		8
+#define	ID_AA64ISAR0_SHA1_MASK		(0xf << ID_AA64ISAR0_SHA1_SHIFT)
+#define	ID_AA64ISAR0_SHA1(x)		((x) & ID_AA64ISAR0_SHA1_MASK)
+#define	 ID_AA64ISAR0_SHA1_NONE		(0x0 << ID_AA64ISAR0_SHA1_SHIFT)
+#define	 ID_AA64ISAR0_SHA1_BASE		(0x1 << ID_AA64ISAR0_SHA1_SHIFT)
+#define	ID_AA64ISAR0_SHA2_SHIFT		12
+#define	ID_AA64ISAR0_SHA2_MASK		(0xf << ID_AA64ISAR0_SHA2_SHIFT)
+#define	ID_AA64ISAR0_SHA2(x)		((x) & ID_AA64ISAR0_SHA2_MASK)
+#define	 ID_AA64ISAR0_SHA2_NONE		(0x0 << ID_AA64ISAR0_SHA2_SHIFT)
+#define	 ID_AA64ISAR0_SHA2_BASE		(0x1 << ID_AA64ISAR0_SHA2_SHIFT)
+#define	ID_AA64ISAR0_CRC32_SHIFT	16
+#define	ID_AA64ISAR0_CRC32_MASK		(0xf << ID_AA64ISAR0_CRC32_SHIFT)
+#define	ID_AA64ISAR0_CRC32(x)		((x) & ID_AA64ISAR0_CRC32_MASK)
+#define	 ID_AA64ISAR0_CRC32_NONE	(0x0 << ID_AA64ISAR0_CRC32_SHIFT)
+#define	 ID_AA64ISAR0_CRC32_BASE	(0x1 << ID_AA64ISAR0_CRC32_SHIFT)
+#define	ID_AA64ISAR0_ATOMIC_SHIFT	20
+#define	ID_AA64ISAR0_ATOMIC_MASK	(0xf << ID_AA64ISAR0_ATOMIC_SHIFT)
+#define	ID_AA64ISAR0_ATOMIC(x)		((x) & ID_AA64ISAR0_ATOMIC_MASK)
+#define	 ID_AA64ISAR0_ATOMIC_NONE	(0x0 << ID_AA64ISAR0_ATOMIC_SHIFT)
+#define	 ID_AA64ISAR0_ATOMIC_IMPL	(0x2 << ID_AA64ISAR0_ATOMIC_SHIFT)
+#define	ID_AA64ISAR0_RDM_SHIFT		28
+#define	ID_AA64ISAR0_RDM_MASK		(0xf << ID_AA64ISAR0_RDM_SHIFT)
+#define	ID_AA64ISAR0_RDM(x)		((x) & ID_AA64ISAR0_RDM_MASK)
+#define	 ID_AA64ISAR0_RDM_NONE		(0x0 << ID_AA64ISAR0_RDM_SHIFT)
+#define	 ID_AA64ISAR0_RDM_IMPL		(0x1 << ID_AA64ISAR0_RDM_SHIFT)
+
+/* ID_AA64MMFR0_EL1 */
+#define	ID_AA64MMFR0_MASK		0xffffffff
+#define	ID_AA64MMFR0_PA_RANGE_SHIFT	0
+#define	ID_AA64MMFR0_PA_RANGE_MASK	(0xf << ID_AA64MMFR0_PA_RANGE_SHIFT)
+#define	ID_AA64MMFR0_PA_RANGE(x)	((x) & ID_AA64MMFR0_PA_RANGE_MASK)
+#define	 ID_AA64MMFR0_PA_RANGE_4G	(0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT)
+#define	 ID_AA64MMFR0_PA_RANGE_64G	(0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT)
+#define	 ID_AA64MMFR0_PA_RANGE_1T	(0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT)
+#define	 ID_AA64MMFR0_PA_RANGE_4T	(0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT)
+#define	 ID_AA64MMFR0_PA_RANGE_16T	(0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT)
+#define	 ID_AA64MMFR0_PA_RANGE_256T	(0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT)
+#define	ID_AA64MMFR0_ASID_BITS_SHIFT	4
+#define	ID_AA64MMFR0_ASID_BITS_MASK	(0xf << ID_AA64MMFR0_ASID_BITS_SHIFT)
+#define	ID_AA64MMFR0_ASID_BITS(x)	((x) & ID_AA64MMFR0_ASID_BITS_MASK)
+#define	 ID_AA64MMFR0_ASID_BITS_8	(0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT)
+#define	 ID_AA64MMFR0_ASID_BITS_16	(0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT)
+#define	ID_AA64MMFR0_BIGEND_SHIFT	8
+#define	ID_AA64MMFR0_BIGEND_MASK	(0xf << ID_AA64MMFR0_BIGEND_SHIFT)
+#define	ID_AA64MMFR0_BIGEND(x)		((x) & ID_AA64MMFR0_BIGEND_MASK)
+#define	 ID_AA64MMFR0_BIGEND_FIXED	(0x0 << ID_AA64MMFR0_BIGEND_SHIFT)
+#define	 ID_AA64MMFR0_BIGEND_MIXED	(0x1 << ID_AA64MMFR0_BIGEND_SHIFT)
+#define	ID_AA64MMFR0_S_NS_MEM_SHIFT	12
+#define	ID_AA64MMFR0_S_NS_MEM_MASK	(0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT)
+#define	ID_AA64MMFR0_S_NS_MEM(x)	((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
+#define	 ID_AA64MMFR0_S_NS_MEM_NONE	(0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
+#define	 ID_AA64MMFR0_S_NS_MEM_DISTINCT	(0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
+#define	ID_AA64MMFR0_BIGEND_EL0_SHIFT	16
+#define	ID_AA64MMFR0_BIGEND_EL0_MASK	(0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
+#define	ID_AA64MMFR0_BIGEND_EL0(x)	((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
+#define	 ID_AA64MMFR0_BIGEND_EL0_FIXED	(0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
+#define	 ID_AA64MMFR0_BIGEND_EL0_MIXED	(0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
+#define	ID_AA64MMFR0_TGRAN16_SHIFT	20
+#define	ID_AA64MMFR0_TGRAN16_MASK	(0xf << ID_AA64MMFR0_TGRAN16_SHIFT)
+#define	ID_AA64MMFR0_TGRAN16(x)		((x) & ID_AA64MMFR0_TGRAN16_MASK)
+#define	 ID_AA64MMFR0_TGRAN16_NONE	(0x0 << ID_AA64MMFR0_TGRAN16_SHIFT)
+#define	 ID_AA64MMFR0_TGRAN16_IMPL	(0x1 << ID_AA64MMFR0_TGRAN16_SHIFT)
+#define	ID_AA64MMFR0_TGRAN64_SHIFT	24
+#define	ID_AA64MMFR0_TGRAN64_MASK	(0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
+#define	ID_AA64MMFR0_TGRAN64(x)		((x) & ID_AA64MMFR0_TGRAN64_MASK)
+#define	 ID_AA64MMFR0_TGRAN64_IMPL	(0x0 << ID_AA64MMFR0_TGRAN64_SHIFT)
+#define	 ID_AA64MMFR0_TGRAN64_NONE	(0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
+#define	ID_AA64MMFR0_TGRAN4_SHIFT	28
+#define	ID_AA64MMFR0_TGRAN4_MASK	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
+#define	ID_AA64MMFR0_TGRAN4(x)		((x) & ID_AA64MMFR0_TGRAN4_MASK)
+#define	 ID_AA64MMFR0_TGRAN4_IMPL	(0x0 << ID_AA64MMFR0_TGRAN4_SHIFT)
+#define	 ID_AA64MMFR0_TGRAN4_NONE	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
+
+/* ID_AA64MMFR1_EL1 */
+#define	ID_AA64MMFR1_MASK		0x00ffffff
+#define	ID_AA64MMFR1_HAFDBS_SHIFT	0
+#define	ID_AA64MMFR1_HAFDBS_MASK	(0xf << ID_AA64MMFR1_HAFDBS_SHIFT)
+#define	ID_AA64MMFR1_HAFDBS(x)		((x) & ID_AA64MMFR1_HAFDBS_MASK)
+#define	 ID_AA64MMFR1_HAFDBS_NONE	(0x0 << ID_AA64MMFR1_HAFDBS_SHIFT)
+#define	 ID_AA64MMFR1_HAFDBS_AF		(0x1 << ID_AA64MMFR1_HAFDBS_SHIFT)
+#define	 ID_AA64MMFR1_HAFDBS_AF_DBS	(0x2 << ID_AA64MMFR1_HAFDBS_SHIFT)
+#define	ID_AA64MMFR1_VMIDBITS_SHIFT	4
+#define	ID_AA64MMFR1_VMIDBITS_MASK	(0xf << ID_AA64MMFR1_VMIDBITS_SHIFT)
+#define	ID_AA64MMFR1_VMIDBITS(x)	((x) & ID_AA64MMFR1_VMIDBITS_MASK)
+#define	 ID_AA64MMFR1_VMIDBITS_8	(0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT)
+#define	 ID_AA64MMFR1_VMIDBITS_16	(0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT)
+#define	ID_AA64MMFR1_VH_SHIFT		8
+#define	ID_AA64MMFR1_VH_MASK		(0xf << ID_AA64MMFR1_VH_SHIFT)
+#define	ID_AA64MMFR1_VH(x)		((x) & ID_AA64MMFR1_VH_MASK)
+#define	 ID_AA64MMFR1_VH_NONE		(0x0 << ID_AA64MMFR1_VH_SHIFT)
+#define	 ID_AA64MMFR1_VH_IMPL		(0x1 << ID_AA64MMFR1_VH_SHIFT)
+#define	ID_AA64MMFR1_HPDS_SHIFT		12
+#define	ID_AA64MMFR1_HPDS_MASK		(0xf << ID_AA64MMFR1_HPDS_SHIFT)
+#define	ID_AA64MMFR1_HPDS(x)		((x) & ID_AA64MMFR1_HPDS_MASK)
+#define	 ID_AA64MMFR1_HPDS_NONE		(0x0 << ID_AA64MMFR1_HPDS_SHIFT)
+#define	 ID_AA64MMFR1_HPDS_IMPL		(0x1 << ID_AA64MMFR1_HPDS_SHIFT)
+#define	ID_AA64MMFR1_LO_SHIFT		16
+#define	ID_AA64MMFR1_LO_MASK		(0xf << ID_AA64MMFR1_LO_SHIFT)
+#define	ID_AA64MMFR1_LO(x)		((x) & ID_AA64MMFR1_LO_MASK)
+#define	 ID_AA64MMFR1_LO_NONE		(0x0 << ID_AA64MMFR1_LO_SHIFT)
+#define	 ID_AA64MMFR1_LO_IMPL		(0x1 << ID_AA64MMFR1_LO_SHIFT)
+#define	ID_AA64MMFR1_PAN_SHIFT		20
+#define	ID_AA64MMFR1_PAN_MASK		(0xf << ID_AA64MMFR1_PAN_SHIFT)
+#define	ID_AA64MMFR1_PAN(x)		((x) & ID_AA64MMFR1_PAN_MASK)
+#define	 ID_AA64MMFR1_PAN_NONE		(0x0 << ID_AA64MMFR1_PAN_SHIFT)
+#define	 ID_AA64MMFR1_PAN_IMPL		(0x1 << ID_AA64MMFR1_PAN_SHIFT)
+
 /* ID_AA64PFR0_EL1 */
-#define	ID_AA64PFR0_EL0_MASK	(0xf << 0)
-#define	ID_AA64PFR0_EL1_MASK	(0xf << 4)
-#define	ID_AA64PFR0_EL2_MASK	(0xf << 8)
-#define	ID_AA64PFR0_EL3_MASK	(0xf << 12)
-#define	ID_AA64PFR0_FP_MASK	(0xf << 16)
-#define	 ID_AA64PFR0_FP_IMPL	(0x0 << 16) /* Floating-point implemented */
-#define	 ID_AA64PFR0_FP_NONE	(0xf << 16) /* Floating-point not implemented */
-#define	ID_AA64PFR0_ADV_SIMD_MASK (0xf << 20)
-#define	ID_AA64PFR0_GIC_SHIFT	(24)
-#define	ID_AA64PFR0_GIC_BITS	(0x4) /* Number of bits in GIC field */
-#define	ID_AA64PFR0_GIC_MASK	(0xf << ID_AA64PFR0_GIC_SHIFT)
-#define	 ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT)
+#define	ID_AA64PFR0_MASK		0x0fffffff
+#define	ID_AA64PFR0_EL0_SHIFT		0
+#define	ID_AA64PFR0_EL0_MASK		(0xf << ID_AA64PFR0_EL0_SHIFT)
+#define	ID_AA64PFR0_EL0(x)		((x) & ID_AA64PFR0_EL0_MASK)
+#define	 ID_AA64PFR0_EL0_64		(1 << ID_AA64PFR0_EL0_SHIFT)
+#define	 ID_AA64PFR0_EL0_64_32		(2 << ID_AA64PFR0_EL0_SHIFT)
+#define	ID_AA64PFR0_EL1_SHIFT		4
+#define	ID_AA64PFR0_EL1_MASK		(0xf << ID_AA64PFR0_EL1_SHIFT)
+#define	ID_AA64PFR0_EL1(x)		((x) & ID_AA64PFR0_EL1_MASK)
+#define	 ID_AA64PFR0_EL1_64		(1 << ID_AA64PFR0_EL1_SHIFT)
+#define	 ID_AA64PFR0_EL1_64_32		(2 << ID_AA64PFR0_EL1_SHIFT)
+#define	ID_AA64PFR0_EL2_SHIFT		8
+#define	ID_AA64PFR0_EL2_MASK		(0xf << ID_AA64PFR0_EL2_SHIFT)
+#define	ID_AA64PFR0_EL2(x)		((x) & ID_AA64PFR0_EL2_MASK)
+#define	 ID_AA64PFR0_EL2_NONE		(0 << ID_AA64PFR0_EL2_SHIFT)
+#define	 ID_AA64PFR0_EL2_64		(1 << ID_AA64PFR0_EL2_SHIFT)
+#define	 ID_AA64PFR0_EL2_64_32		(2 << ID_AA64PFR0_EL2_SHIFT)
+#define	ID_AA64PFR0_EL3_SHIFT		12
+#define	ID_AA64PFR0_EL3_MASK		(0xf << ID_AA64PFR0_EL3_SHIFT)
+#define	ID_AA64PFR0_EL3(x)		((x) & ID_AA64PFR0_EL3_MASK)
+#define	 ID_AA64PFR0_EL3_NONE		(0 << ID_AA64PFR0_EL3_SHIFT)
+#define	 ID_AA64PFR0_EL3_64		(1 << ID_AA64PFR0_EL3_SHIFT)
+#define	 ID_AA64PFR0_EL3_64_32		(2 << ID_AA64PFR0_EL3_SHIFT)
+#define	ID_AA64PFR0_FP_SHIFT		16
+#define	ID_AA64PFR0_FP_MASK		(0xf << ID_AA64PFR0_FP_SHIFT)
+#define	ID_AA64PFR0_FP(x)		((x) & ID_AA64PFR0_FP_MASK)
+#define	 ID_AA64PFR0_FP_IMPL		(0x0 << ID_AA64PFR0_FP_SHIFT)
+#define	 ID_AA64PFR0_FP_NONE		(0xf << ID_AA64PFR0_FP_SHIFT)
+#define	ID_AA64PFR0_ADV_SIMD_SHIFT	20
+#define	ID_AA64PFR0_ADV_SIMD_MASK	(0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
+#define	ID_AA64PFR0_ADV_SIMD(x)		((x) & ID_AA64PFR0_ADV_SIMD_MASK)
+#define	 ID_AA64PFR0_ADV_SIMD_IMPL	(0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT)
+#define	 ID_AA64PFR0_ADV_SIMD_NONE	(0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
+#define	ID_AA64PFR0_GIC_BITS		0x4 /* Number of bits in GIC field */
+#define	ID_AA64PFR0_GIC_SHIFT		24
+#define	ID_AA64PFR0_GIC_MASK		(0xf << ID_AA64PFR0_GIC_SHIFT)
+#define	ID_AA64PFR0_GIC(x)		((x) & ID_AA64PFR0_GIC_MASK)
+#define	 ID_AA64PFR0_GIC_CPUIF_NONE	(0x0 << ID_AA64PFR0_GIC_SHIFT)
+#define	 ID_AA64PFR0_GIC_CPUIF_EN	(0x1 << ID_AA64PFR0_GIC_SHIFT)
 
 /* MAIR_EL1 - Memory Attribute Indirection Register */
 #define	MAIR_ATTR_MASK(idx)	(0xff << ((n)* 8))
 #define	MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
+#define	 MAIR_DEVICE_nGnRnE	0x00
+#define	 MAIR_NORMAL_NC		0x44
+#define	 MAIR_NORMAL_WT		0x88
+#define	 MAIR_NORMAL_WB		0xff
+
+/* PAR_EL1 - Physical Address Register */
+#define	PAR_F_SHIFT		0
+#define	PAR_F			(0x1 << PAR_F_SHIFT)
+#define	PAR_SUCCESS(x)		(((x) & PAR_F) == 0)
+/* When PAR_F == 0 (success) */
+#define	PAR_SH_SHIFT		7
+#define	PAR_SH_MASK		(0x3 << PAR_SH_SHIFT)
+#define	PAR_NS_SHIFT		9
+#define	PAR_NS_MASK		(0x3 << PAR_NS_SHIFT)
+#define	PAR_PA_SHIFT		12
+#define	PAR_PA_MASK		0x0000fffffffff000
+#define	PAR_ATTR_SHIFT		56
+#define	PAR_ATTR_MASK		(0xff << PAR_ATTR_SHIFT)
+/* When PAR_F == 1 (aborted) */
+#define	PAR_FST_SHIFT		1
+#define	PAR_FST_MASK		(0x3f << PAR_FST_SHIFT)
+#define	PAR_PTW_SHIFT		8
+#define	PAR_PTW_MASK		(0x1 << PAR_PTW_SHIFT)
+#define	PAR_S_SHIFT		9
+#define	PAR_S_MASK		(0x1 << PAR_S_SHIFT)
 
 /* SCTLR_EL1 - System Control Register */
 #define	SCTLR_RES0	0xc8222400	/* Reserved, write 0 */
@@ -201,20 +452,33 @@
 #define	TCR_TG1_4K	(2 << TCR_TG1_SHIFT)
 #define	TCR_TG1_64K	(3 << TCR_TG1_SHIFT)
 
-#define TCR_SH0_SHIFT	12
-#define TCR_SH1_SHIFT	28
-#define TCR_SH0(x)	((x) << TCR_SH0_SHIFT)
-#define TCR_SH1(x)	((x) << TCR_SH1_SHIFT)
-#define TCR_ORGN1_SHIFT	26
-#define TCR_IRGN1_SHIFT	24
-#define TCR_ORGN0_SHIFT	10
-#define TCR_IRGN0_SHIFT	8
-#define TCR_ORGNx(x)	(((x) << TCR_ORGN1_SHIFT)|((x) << TCR_ORGN0_SHIFT))
-#define TCR_IRGNx(x)	(((x) << TCR_IRGN1_SHIFT)|((x) << TCR_IRGN0_SHIFT))
-#define TCR_SH1(x)	((x) << TCR_SH1_SHIFT)
+#define	TCR_SH1_SHIFT	28
+#define	TCR_SH1_IS	(0x3UL << TCR_SH1_SHIFT)
+#define	TCR_ORGN1_SHIFT	26
+#define	TCR_ORGN1_WBWA	(0x1UL << TCR_ORGN1_SHIFT)
+#define	TCR_IRGN1_SHIFT	24
+#define	TCR_IRGN1_WBWA	(0x1UL << TCR_IRGN1_SHIFT)
+#define	TCR_SH0_SHIFT	12
+#define	TCR_SH0_IS	(0x3UL << TCR_SH0_SHIFT)
+#define	TCR_ORGN0_SHIFT	10
+#define	TCR_ORGN0_WBWA	(0x1UL << TCR_ORGN0_SHIFT)
+#define	TCR_IRGN0_SHIFT	8
+#define	TCR_IRGN0_WBWA	(0x1UL << TCR_IRGN0_SHIFT)
+
+#define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
+				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
+
+#ifdef SMP
+#define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
+#else
+#define	TCR_SMP_ATTRS	0
+#endif
+
 #define	TCR_T1SZ_SHIFT	16
 #define	TCR_T0SZ_SHIFT	0
-#define	TCR_TxSZ(x)	(((x) << TCR_T1SZ_SHIFT) | ((x) << TCR_T0SZ_SHIFT))
+#define	TCR_T1SZ(x)	((x) << TCR_T1SZ_SHIFT)
+#define	TCR_T0SZ(x)	((x) << TCR_T0SZ_SHIFT)
+#define	TCR_TxSZ(x)	(TCR_T1SZ(x) | TCR_T0SZ(x))
 
 /* Saved Program Status Register */
 #define	DBG_SPSR_SS	(0x1 << 21)
@@ -224,25 +488,39 @@
 #define	DBG_MDSCR_KDE	(0x1 << 13)
 #define	DBG_MDSCR_MDE	(0x1 << 15)
 
+/* Perfomance Monitoring Counters */
+#define	PMCR_E		(1 << 0) /* Enable all counters */
+#define	PMCR_P		(1 << 1) /* Reset all counters */
+#define	PMCR_C		(1 << 2) /* Clock counter reset */
+#define	PMCR_D		(1 << 3) /* CNTR counts every 64 clk cycles */
+#define	PMCR_X		(1 << 4) /* Export to ext. monitoring (ETM) */
+#define	PMCR_DP		(1 << 5) /* Disable CCNT if non-invasive debug*/
+#define	PMCR_LC		(1 << 6) /* Long cycle count enable */
+#define	PMCR_IMP_SHIFT	24 /* Implementer code */
+#define	PMCR_IMP_MASK	(0xff << PMCR_IMP_SHIFT)
+#define	PMCR_IDCODE_SHIFT	16 /* Identification code */
+#define	PMCR_IDCODE_MASK	(0xff << PMCR_IDCODE_SHIFT)
+#define	 PMCR_IDCODE_CORTEX_A57	0x01
+#define	 PMCR_IDCODE_CORTEX_A72	0x02
+#define	 PMCR_IDCODE_CORTEX_A53	0x03
+#define	PMCR_N_SHIFT	11       /* Number of counters implemented */
+#define	PMCR_N_MASK	(0x1f << PMCR_N_SHIFT)
 
 /* Individual CPUs are probably best IDed by everything but the revision. */
-#define CPU_ID_CPU_MASK                0xfffffff0
+#define	CPU_ID_CPU_MASK		0xfffffff0
 
 /* ARM64 CPUs */
-#define CPU_ID_CORTEX_A53       0x410fd030
-#define CPU_ID_CORTEX_A53_R1    0x411fd030
-#define CPU_ID_CORTEX_A53_MASK  0xff0ffff0
-#define CPU_ID_CORTEX_A57       0x410fd070
-#define CPU_ID_CORTEX_A57_R1    0x411fd070
-#define CPU_ID_CORTEX_A57_MASK  0xff0ffff0
-#define CPU_ID_CORTEX_A72       0x410fd080
-#define CPU_ID_CORTEX_A72_R1    0x411fd080
-#define CPU_ID_CORTEX_A57_MASK  0xff0ffff0
-
-
-#define I_bit (1 << 7)	/* IRQ disable */
-#define F_bit 0		/* FIQ disable - not actually used */
+#define	CPU_ID_CORTEX_A53	0x410fd030
+#define	CPU_ID_CORTEX_A53_R1	0x411fd030
+#define	CPU_ID_CORTEX_A53_MASK	0xff0ffff0
+#define	CPU_ID_CORTEX_A57	0x410fd070
+#define	CPU_ID_CORTEX_A57_R1	0x411fd070
+#define	CPU_ID_CORTEX_A57_MASK	0xff0ffff0
+#define	CPU_ID_CORTEX_A72	0x410fd080
+#define	CPU_ID_CORTEX_A72_R1	0x411fd080
+#define	CPU_ID_CORTEX_A57_MASK	0xff0ffff0
 
-#define INSN_SIZE	4
+#define I_bit (1 << 7)		/* IRQ disable */
+#define F_bit 0			/* FIQ disable - not actually used */
 
 #endif /* !_MACHINE_ARMREG_H_ */
diff --git a/sys/arch/arm64/include/bootconfig.h b/sys/arch/arm64/include/bootconfig.h
index f6f3598a2df..5f1c49124f5 100644
--- a/sys/arch/arm64/include/bootconfig.h
+++ b/sys/arch/arm64/include/bootconfig.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bootconfig.h,v 1.1 2016/12/17 23:38:33 patrick Exp $	*/
+/*	$OpenBSD: bootconfig.h,v 1.2 2016/12/18 14:40:25 patrick Exp $	*/
 /*	$NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $	*/
 
 /*-
@@ -26,7 +26,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/arm64/include/machdep.h 281494 2015-04-13 14:43:10Z andrew $
  */
 
 #ifndef _MACHINE_BOOTCONFIG_H_
diff --git a/sys/arch/arm64/include/hypervisor.h b/sys/arch/arm64/include/hypervisor.h
index 2c51be0f54b..8a7ee6ce4e3 100644
--- a/sys/arch/arm64/include/hypervisor.h
+++ b/sys/arch/arm64/include/hypervisor.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: hypervisor.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
+/* $OpenBSD: hypervisor.h,v 1.2 2016/12/18 14:40:25 patrick Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * All rights reserved.
@@ -24,7 +24,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/arm64/include/hypervisor.h 281494 2015-04-13 14:43:10Z andrew $
  */
 
 #ifndef _MACHINE_HYPERVISOR_H_
diff --git a/sys/arch/arm64/include/vfp.h b/sys/arch/arm64/include/vfp.h
index f6240aab92f..74a52506e08 100644
--- a/sys/arch/arm64/include/vfp.h
+++ b/sys/arch/arm64/include/vfp.h
@@ -1,9 +1,11 @@
-/* $OpenBSD: vfp.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
-/*
- * Copyright (c) 2012 Mark Tinguely
- *
+/* $OpenBSD: vfp.h,v 1.2 2016/12/18 14:40:25 patrick Exp $ */
+/*-
+ * Copyright (c) 2015 The FreeBSD Foundation
  * All rights reserved.
  *
+ * This software was developed by Andrew Turner under
+ * sponsorship from the FreeBSD Foundation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
@@ -24,24 +26,26 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- * $FreeBSD$
+ *
+ * $FreeBSD: head/sys/arm64/include/vfp.h 281494 2015-04-13 14:43:10Z andrew $
  */
 
-
-#ifndef _MACHINE__VFP_H_
-#define _MACHINE__VFP_H_
+#ifndef _MACHINE_VFP_H_
+#define	_MACHINE_VFP_H_
 
 #ifdef _KERNEL
-/* Only kernel defines exist here */
 
-#define VFP_KFPEN	(1 << 20)
-#define VFP_UFPEN	(3 << 20)
+#define	VFP_KFPEN	(1 << 20)
+#define	VFP_UFPEN	(3 << 20)
+
+#ifndef LOCORE
+void	vfp_init(void);
+void	vfp_discard(struct proc *);
+void	vfp_save(void);
+void	vfp_enable(void);
+int	vfp_fault(vaddr_t, uint32_t, trapframe_t *, int);
+#endif
 
-void		vfp_init(void);
-void		vfp_discard(struct proc *p);
-void		vfp_save(void);
-void		vfp_enable(void);
-int vfp_fault(vaddr_t pc, uint32_t insn, trapframe_t *tf, int fault_code);
+#endif
 
-#endif /* _KERNEL */
-#endif /* _MACHINE__VFP_H_ */
+#endif /* !_MACHINE_VFP_H_ */
diff --git a/sys/arch/arm64/stand/efiboot/self_reloc.c b/sys/arch/arm64/stand/efiboot/self_reloc.c
index 5f23698d6a3..f82759212f3 100644
--- a/sys/arch/arm64/stand/efiboot/self_reloc.c
+++ b/sys/arch/arm64/stand/efiboot/self_reloc.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: self_reloc.c,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
+/* $OpenBSD: self_reloc.c,v 1.2 2016/12/18 14:40:25 patrick Exp $ */
 /*-
  * Copyright (c) 2008-2010 Rui Paulo <rpaulo@FreeBSD.org>
  * All rights reserved.
@@ -25,6 +25,10 @@
  * SUCH DAMAGE.
  */
 
+#if 0
+__FBSDID("$FreeBSD: head/sys/boot/common/self_reloc.c 309360 2016-12-01 14:28:37Z emaste $");
+#endif
+
 #include <sys/param.h>
 #include <sys/exec_elf.h>
 #include <machine/reloc.h>
diff --git a/sys/arch/arm64/stand/efiboot/start.S b/sys/arch/arm64/stand/efiboot/start.S
index 0720a2195e2..cebef49de0d 100644
--- a/sys/arch/arm64/stand/efiboot/start.S
+++ b/sys/arch/arm64/stand/efiboot/start.S
@@ -1,4 +1,4 @@
-/* $OpenBSD: start.S,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
+/* $OpenBSD: start.S,v 1.2 2016/12/18 14:40:25 patrick Exp $ */
 /*-
  * Copyright (c) 2014 Andrew Turner
  * All rights reserved.
@@ -24,7 +24,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/boot/efi/loader/arch/arm64/start.S 282727 2015-05-10 13:24:26Z ian $
  */
 
 /*