It's been a quarter century: we can assume volatile is present with that name.

ok dlg@ mpi@ deraadt@

11 files changed, 61 insertions, 61 deletions

diff --git a/sys/arch/arm/arm/cpu.c b/sys/arch/arm/arm/cpu.c
index acf9cc6d350..fe1c76f522e 100644
--- a/sys/arch/arm/arm/cpu.c
+++ b/sys/arch/arm/arm/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.17 2013/08/06 23:15:43 jsg Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.18 2014/03/29 18:09:28 guenther Exp $	*/
 /*	$NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $	*/
 
 
@@ -570,7 +570,7 @@ cpu_alloc_idlepcb(struct cpu_info *ci)
  * on the CPU.
  */
 void
-atomic_setbits_int(__volatile unsigned int *uip, unsigned int v)
+atomic_setbits_int(volatile unsigned int *uip, unsigned int v)
 {
 	int oldirqstate;
 	oldirqstate = disable_interrupts(I32_bit|F32_bit);
@@ -579,7 +579,7 @@ atomic_setbits_int(__volatile unsigned int *uip, unsigned int v)
 }
 
 void
-atomic_clearbits_int(__volatile unsigned int *uip, unsigned int v)
+atomic_clearbits_int(volatile unsigned int *uip, unsigned int v)
 {
 	int oldirqstate;
 	oldirqstate = disable_interrupts(I32_bit|F32_bit);
diff --git a/sys/arch/arm/arm/cpufunc.c b/sys/arch/arm/arm/cpufunc.c
index 557519098e5..7a8a47135cf 100644
--- a/sys/arch/arm/arm/cpufunc.c
+++ b/sys/arch/arm/arm/cpufunc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.c,v 1.24 2013/09/03 16:48:26 patrick Exp $	*/
+/*	$OpenBSD: cpufunc.c,v 1.25 2014/03/29 18:09:28 guenther Exp $	*/
 /*	$NetBSD: cpufunc.c,v 1.65 2003/11/05 12:53:15 scw Exp $	*/
 
 /*
@@ -641,7 +641,7 @@ get_cachetype_cp15()
 	u_int ctype, isize, dsize;
 	u_int multiplier;
 
-	__asm __volatile("mrc p15, 0, %0, c0, c0, 1"
+	__asm volatile("mrc p15, 0, %0, c0, c0, 1"
 		: "=r" (ctype));
 
 	/*
@@ -786,7 +786,7 @@ arm_get_cachetype_cp15v7(void)
 	uint32_t sel, level;
 
 	/* CLIDR - Cache Level ID Register */
-	__asm __volatile("mrc p15, 1, %0, c0, c0, 1"
+	__asm volatile("mrc p15, 1, %0, c0, c0, 1"
 		: "=r" (cache_level_id) :);
 	cpu_drain_writebuf();
 
@@ -802,11 +802,11 @@ arm_get_cachetype_cp15v7(void)
 		    cache_level_id & (0x2 << level)) {
 			sel = level << 1 | 0 << 0; /* L1 | unified/data cache */
 			/* CSSELR - Cache Size Selection Register */
-			__asm __volatile("mcr p15, 2, %0, c0, c0, 0"
+			__asm volatile("mcr p15, 2, %0, c0, c0, 0"
 				:: "r" (sel));
 			cpu_drain_writebuf();
 			/* CCSIDR - Cache Size Identification Register */
-			__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
+			__asm volatile("mrc p15, 1, %0, c0, c0, 0"
 			: "=r" (cachereg) :);
 			cpu_drain_writebuf();
 			sets = ((cachereg >> 13) & 0x7fff) + 1;
@@ -831,11 +831,11 @@ arm_get_cachetype_cp15v7(void)
 		if (cache_level_id & (0x1 << level)) {
 			sel = level << 1 | 1 << 0; /* L1 | instruction cache */
 			/* CSSELR - Cache Size Selection Register */
-			__asm __volatile("mcr p15, 2, %0, c0, c0, 0"
+			__asm volatile("mcr p15, 2, %0, c0, c0, 0"
 				:: "r" (sel));
 			cpu_drain_writebuf();
 			/* CCSIDR - Cache Size Identification Register */
-			__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
+			__asm volatile("mrc p15, 1, %0, c0, c0, 0"
 			: "=r" (cachereg) :);
 			cpu_drain_writebuf();
 			sets = ((cachereg >> 13) & 0x7fff) + 1;
@@ -860,7 +860,7 @@ armv7_idcache_wbinv_all()
 {
 	uint32_t arg;
 	arg = 0;
-	__asm __volatile("mcr	p15, 0, r0, c7, c5, 0" :: "r" (arg));
+	__asm volatile("mcr	p15, 0, r0, c7, c5, 0" :: "r" (arg));
 	armv7_dcache_wbinv_all();
 }
 /* brute force cache flushing */
@@ -892,7 +892,7 @@ armv7_dcache_wbinv_all()
 			word = wayval | setval | lvl;
 
 			/* Clean D cache SE with Set/Index */
-			__asm __volatile("mcr	p15, 0, %0, c7, c10, 2"
+			__asm volatile("mcr	p15, 0, %0, c7, c10, 2"
 			    : : "r" (word));
 			wayval += wayincr;
 		}
@@ -1067,7 +1067,7 @@ set_cpufuncs()
 		 *	- overflow indications cleared
 		 *	- all counters disabled
 		 */
-		__asm __volatile("mcr p14, 0, %0, c0, c0, 0"
+		__asm volatile("mcr p14, 0, %0, c0, c0, 0"
 			:
 			: "r" (PMNC_P|PMNC_C|PMNC_PMN0_IF|PMNC_PMN1_IF|
 			       PMNC_CC_IF));
@@ -1077,7 +1077,7 @@ set_cpufuncs()
 		/*
 		 * Crank CCLKCFG to maximum legal value.
 		 */
-		__asm __volatile ("mcr p14, 0, %0, c6, c0, 0"
+		__asm volatile ("mcr p14, 0, %0, c6, c0, 0"
 			:
 			: "r" (XSCALE_CCLKCFG));
 #endif
@@ -1087,7 +1087,7 @@ set_cpufuncs()
 		 * don't really support it, yet.  Clear any pending
 		 * error indications.
 		 */
-		__asm __volatile("mcr p13, 0, %0, c0, c1, 0"
+		__asm volatile("mcr p13, 0, %0, c0, c1, 0"
 			:
 			: "r" (BCUCTL_E0|BCUCTL_E1|BCUCTL_EV));
 
@@ -1126,7 +1126,7 @@ set_cpufuncs()
 		 *	- overflow indications cleared
 		 *	- all counters disabled
 		 */
-		__asm __volatile("mcr p14, 0, %0, c0, c0, 0"
+		__asm volatile("mcr p14, 0, %0, c0, c0, 0"
 			:
 			: "r" (PMNC_P|PMNC_C|PMNC_PMN0_IF|PMNC_PMN1_IF|
 			       PMNC_CC_IF));
@@ -1282,7 +1282,7 @@ arm9e_setup()
 	cpu_idcache_wbinv_all();
 
 	/* Now really make sure they are clean.  */
-	__asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
+	__asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
 
 	/* Set the control register */
 	curcpu()->ci_ctrl = cpuctrl;
@@ -1300,7 +1300,7 @@ arm10_setup()
 	arm9e_setup();
 
 	/* Allow detection code to find the VFP if it's fitted.  */
-	__asm __volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
+	__asm volatile ("mcr\tp15, 0, %0, c1, c0, 2" : : "r" (0x0fffffff));
 }
 #endif	/* CPU_ARM10 */
 
@@ -1473,14 +1473,14 @@ xscale_setup()
 	cpu_control(0xffffffff, cpuctrl);
 
 	/* Make sure write coalescing is turned on */
-	__asm __volatile("mrc p15, 0, %0, c1, c0, 1"
+	__asm volatile("mrc p15, 0, %0, c1, c0, 1"
 		: "=r" (auxctl));
 #ifdef XSCALE_NO_COALESCE_WRITES
 	auxctl |= XSCALE_AUXCTL_K;
 #else
 	auxctl &= ~XSCALE_AUXCTL_K;
 #endif
-	__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
+	__asm volatile("mcr p15, 0, %0, c1, c0, 1"
 		: : "r" (auxctl));
 }
 #endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
diff --git a/sys/arch/arm/arm/pmap.c b/sys/arch/arm/arm/pmap.c
index 4daa4285936..f40fbdf642b 100644
--- a/sys/arch/arm/arm/pmap.c
+++ b/sys/arch/arm/arm/pmap.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap.c,v 1.45 2013/11/04 00:35:30 dlg Exp $	*/
+/*	$OpenBSD: pmap.c,v 1.46 2014/03/29 18:09:28 guenther Exp $	*/
 /*	$NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $	*/
 
 /*
@@ -3002,8 +3002,8 @@ pmap_activate(struct proc *p)
 	if (p == curproc) {
 		u_int cur_dacr, cur_ttb;
 
-		__asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
-		__asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
+		__asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
+		__asm volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
 
 		cur_ttb &= ~(L1_TABLE_SIZE - 1);
 
@@ -4767,9 +4767,9 @@ pmap_pte_init_armv7(void)
 	pmap_copy_page_func = pmap_copy_page_v7;
 
 	/* probe L1 dcache */
-	__asm __volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (0) );
+	__asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (0) );
 	/* read the arm v7 cache control register, is writhru is supported? */
-	__asm __volatile("mrc p15, 1, %0, c0, c0, 0"
+	__asm volatile("mrc p15, 1, %0, c0, c0, 0"
 		: "=r" (cachereg) :);
 
 	if ((cachereg & 0x80000000) == 0)
@@ -4902,9 +4902,9 @@ pmap_pte_init_xscale(void)
 	/*
 	 * Disable ECC protection of page table access, for now.
 	 */
-	__asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
+	__asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
 	auxctl &= ~XSCALE_AUXCTL_P;
-	__asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
+	__asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
 
 	pmap_needs_pte_sync = 1;
 }
@@ -4966,10 +4966,10 @@ xscale_setup_minidata(vaddr_t l1pt, vaddr_t va, paddr_t pa)
 	 */
 
 	/* Invalidate data and mini-data. */
-	__asm __volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
-	__asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
+	__asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
+	__asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (auxctl));
 	auxctl = (auxctl & ~XSCALE_AUXCTL_MD_MASK) | XSCALE_AUXCTL_MD_WB_RWA;
-	__asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
+	__asm volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl));
 }
 
 /*
diff --git a/sys/arch/arm/arm/pmap7.c b/sys/arch/arm/arm/pmap7.c
index 909406bb48a..14a4c3aae31 100644
--- a/sys/arch/arm/arm/pmap7.c
+++ b/sys/arch/arm/arm/pmap7.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pmap7.c,v 1.12 2013/11/04 00:35:30 dlg Exp $	*/
+/*	$OpenBSD: pmap7.c,v 1.13 2014/03/29 18:09:28 guenther Exp $	*/
 /*	$NetBSD: pmap.c,v 1.147 2004/01/18 13:03:50 scw Exp $	*/
 
 /*
@@ -735,7 +735,7 @@ pmap_free_l1(pmap_t pm)
 {
 	u_int cur_ttb;
 
-	__asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
+	__asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
 	cur_ttb &= ~(L1_TABLE_SIZE - 1);
 
 }
@@ -2241,8 +2241,8 @@ pmap_activate(struct proc *p)
 	if (p == curproc) {
 		u_int cur_dacr, cur_ttb;
 
-		__asm __volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
-		__asm __volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
+		__asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r"(cur_ttb));
+		__asm volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(cur_dacr));
 
 		cur_ttb &= ~(L1_TABLE_SIZE - 1);
 
@@ -3517,8 +3517,8 @@ pmap_pte_init_armv7(void)
 	pte_l2_s_proto = L2_S_PROTO_v7;
 
 	/* probe L1 dcache */
-	__asm __volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (0) );
-	__asm __volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (cachereg) );
+	__asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (0) );
+	__asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (cachereg) );
 	if ((cachereg & 0x80000000) == 0) {
 #if 0
 		/*
diff --git a/sys/arch/arm/include/atomic.h b/sys/arch/arm/include/atomic.h
index 5b2de71e43b..83f3a42c6d8 100644
--- a/sys/arch/arm/include/atomic.h
+++ b/sys/arch/arm/include/atomic.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: atomic.h,v 1.8 2011/03/23 16:54:34 pirofti Exp $	*/
+/*	$OpenBSD: atomic.h,v 1.9 2014/03/29 18:09:28 guenther Exp $	*/
 
 /* Public Domain */
 
@@ -12,8 +12,8 @@
  * in the kernel and atomic updates are necessary without full mutexes
  */
 
-void atomic_setbits_int(__volatile unsigned int *, unsigned int);
-void atomic_clearbits_int(__volatile unsigned int *, unsigned int);
+void atomic_setbits_int(volatile unsigned int *, unsigned int);
+void atomic_clearbits_int(volatile unsigned int *, unsigned int);
 
 #endif /* defined(_KERNEL) */
 #endif /* _ARM_ATOMIC_H_ */
diff --git a/sys/arch/arm/include/cpufunc.h b/sys/arch/arm/include/cpufunc.h
index d76f3de5786..43753ac52ab 100644
--- a/sys/arch/arm/include/cpufunc.h
+++ b/sys/arch/arm/include/cpufunc.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpufunc.h,v 1.14 2013/03/30 01:30:30 patrick Exp $	*/
+/*	$OpenBSD: cpufunc.h,v 1.15 2014/03/29 18:09:28 guenther Exp $	*/
 /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
 
 /*
@@ -479,7 +479,7 @@ __set_cpsr_c(u_int bic, u_int eor)
 {
 	u_int32_t	tmp, ret;
 
-	__asm __volatile(
+	__asm volatile(
 		"mrs	%0, cpsr\n\t"	/* Get the CPSR */
 		"bic	%1, %0, %2\n\t"	/* Clear bits */
 		"eor	%1, %1, %3\n\t"	/* XOR bits */
@@ -495,7 +495,7 @@ __get_cpsr()
 {
 	u_int32_t	ret;
 
-	__asm __volatile("mrs	%0, cpsr" : "=&r" (ret));
+	__asm volatile("mrs	%0, cpsr" : "=&r" (ret));
 
 	return ret;
 }
diff --git a/sys/arch/arm/include/lock.h b/sys/arch/arm/include/lock.h
index d8d581eb1c1..cf4b7e4ca38 100644
--- a/sys/arch/arm/include/lock.h
+++ b/sys/arch/arm/include/lock.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: lock.h,v 1.4 2010/04/21 03:03:25 deraadt Exp $	*/
+/*	$OpenBSD: lock.h,v 1.5 2014/03/29 18:09:28 guenther Exp $	*/
 /*	$NetBSD: lock.h,v 1.3 2002/10/07 23:19:49 bjh21 Exp $	*/
 
 /*-
@@ -44,16 +44,16 @@
 
 #include <arm/atomic.h>
 
-typedef __volatile int          __cpu_simple_lock_t;
+typedef volatile int		__cpu_simple_lock_t;
 
 #define __SIMPLELOCK_LOCKED     1
 #define __SIMPLELOCK_UNLOCKED   0
 
 static __inline int
-__swp(int __val, __volatile int *__ptr)
+__swp(int __val, volatile int *__ptr)
 {
 
-	__asm __volatile("swp %0, %1, [%2]"
+	__asm volatile("swp %0, %1, [%2]"
 	    : "=r" (__val) : "r" (__val), "r" (__ptr) : "memory");
 	return __val;
 }
diff --git a/sys/arch/arm/xscale/i80321_intr.c b/sys/arch/arm/xscale/i80321_intr.c
index 58e032074b7..d5e4f1f6417 100644
--- a/sys/arch/arm/xscale/i80321_intr.c
+++ b/sys/arch/arm/xscale/i80321_intr.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i80321_intr.c,v 1.14 2010/09/20 06:33:47 matthew Exp $ */
+/* $OpenBSD: i80321_intr.c,v 1.15 2014/03/29 18:09:28 guenther Exp $ */
 
 /*
  * Copyright (c) 2006 Dale Rahn <drahn@openbsd.org>
@@ -50,8 +50,8 @@ uint32_t	i80321intc_smask[NIPL];
 
 #define SI_TO_IRQBIT(x)	(1 << (x))
 
-__volatile int current_ipl_level;
-__volatile int softint_pending;
+volatile int current_ipl_level;
+volatile int softint_pending;
 
 struct cfattach i80321intc_ca = {
 	sizeof(struct device), i80321intc_match, i80321intc_attach
diff --git a/sys/arch/arm/xscale/pxa2x0.c b/sys/arch/arm/xscale/pxa2x0.c
index 9b9528c66c2..25b517de205 100644
--- a/sys/arch/arm/xscale/pxa2x0.c
+++ b/sys/arch/arm/xscale/pxa2x0.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0.c,v 1.17 2013/05/30 16:15:01 deraadt Exp $ */
+/*	$OpenBSD: pxa2x0.c,v 1.18 2014/03/29 18:09:28 guenther Exp $ */
 /*	$NetBSD: pxa2x0.c,v 1.5 2003/12/12 16:42:44 thorpej Exp $ */
 
 /*
@@ -272,7 +272,7 @@ static inline uint32_t
 read_clock_counter(void)
 {
   uint32_t x;
-  __asm __volatile("mrc	p14, 0, %0, c1, c1, 0" : "=r" (x));
+  __asm volatile("mrc	p14, 0, %0, c1, c1, 0" : "=r" (x));
 
   return x;
 }
@@ -288,9 +288,9 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc)
 	ioh = sc->sc_bush_rtc;
 	irq = disable_interrupts(I32_bit|F32_bit);
 
-	__asm __volatile( "mrc p14, 0, %0, c0, c1, 0" : "=r" (pmcr_save));
+	__asm volatile( "mrc p14, 0, %0, c0, c1, 0" : "=r" (pmcr_save));
 	/* Enable clock counter */
-	__asm __volatile( "mcr p14, 0, %0, c0, c1, 0" : : "r" (0x0001));
+	__asm volatile( "mcr p14, 0, %0, c0, c1, 0" : : "r" (0x0001));
 
 	rtc0 = bus_space_read_4(sc->sc_bust, ioh, RTC_RCNR);
 	/* Wait for next second starts */
@@ -301,7 +301,7 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc)
 		;		/* Wait for 1sec */
 	end = read_clock_counter();
 
-	__asm __volatile( "mcr p14, 0, %0, c0, c1, 0" : : "r" (pmcr_save));
+	__asm volatile( "mcr p14, 0, %0, c0, c1, 0" : : "r" (pmcr_save));
 	restore_interrupts(irq);
 
 	return end - start;
@@ -310,7 +310,7 @@ pxaip_measure_cpuclock(struct pxaip_softc *sc)
 void
 pxa2x0_turbo_mode(int f)
 {
-	__asm __volatile("mcr p14, 0, %0, c6, c0, 0" : : "r" (f));
+	__asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r" (f));
 }
 
 void
diff --git a/sys/arch/arm/xscale/pxa2x0_intr.c b/sys/arch/arm/xscale/pxa2x0_intr.c
index e438498515c..d1b0798cb9f 100644
--- a/sys/arch/arm/xscale/pxa2x0_intr.c
+++ b/sys/arch/arm/xscale/pxa2x0_intr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_intr.c,v 1.23 2012/12/05 23:20:11 deraadt Exp $ */
+/*	$OpenBSD: pxa2x0_intr.c,v 1.24 2014/03/29 18:09:28 guenther Exp $ */
 /*	$NetBSD: pxa2x0_intr.c,v 1.5 2003/07/15 00:24:55 lukem Exp $	*/
 
 /*
@@ -110,8 +110,8 @@ static struct intrhandler{
 #endif
 } handler[ICU_LEN];
 
-__volatile int softint_pending;
-__volatile int current_spl_level;
+volatile int softint_pending;
+volatile int current_spl_level;
 /* interrupt masks for each level */
 int pxa2x0_imask[NIPL];
 static int extirq_level[ICU_LEN];
diff --git a/sys/arch/arm/xscale/pxa2x0_intr.h b/sys/arch/arm/xscale/pxa2x0_intr.h
index d14a8a8ba59..71478df5872 100644
--- a/sys/arch/arm/xscale/pxa2x0_intr.h
+++ b/sys/arch/arm/xscale/pxa2x0_intr.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pxa2x0_intr.h,v 1.13 2009/08/26 20:31:43 deraadt Exp $ */
+/*	$OpenBSD: pxa2x0_intr.h,v 1.14 2014/03/29 18:09:28 guenther Exp $ */
 /*	$NetBSD: pxa2x0_intr.h,v 1.4 2003/07/05 06:53:08 dogcow Exp $ */
 
 /* Derived from i80321_intr.h */
@@ -54,8 +54,8 @@ extern vaddr_t pxaic_base;		/* Shared with pxa2x0_irq.S */
 #define write_icu(offset,value) \
  (*(volatile uint32_t *)(pxaic_base+(offset))=(value))
 
-extern __volatile int current_spl_level;
-extern __volatile int softint_pending;
+extern volatile int current_spl_level;
+extern volatile int softint_pending;
 extern int pxa2x0_imask[];
 void pxa2x0_do_pending(void);