Oops, correct import this time.

5 files changed, 1698 insertions, 0 deletions

diff --git a/sys/arch/aviion/aviion/av400_machdep.c b/sys/arch/aviion/aviion/av400_machdep.c
new file mode 100644
index 00000000000..0c1f0bc345a
--- /dev/null
+++ b/sys/arch/aviion/aviion/av400_machdep.c
@@ -0,0 +1,727 @@
+/*	$OpenBSD: av400_machdep.c,v 1.1 2006/05/09 18:25:34 miod Exp $	*/
+/*
+ * Copyright (c) 2006, Miodrag Vallat.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * Copyright (c) 1998, 1999, 2000, 2001 Steve Murphree, Jr.
+ * Copyright (c) 1996 Nivas Madhur
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Nivas Madhur.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Copyright (c) 1999 Steve Murphree, Jr.
+ * Copyright (c) 1995 Theo de Raadt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (c) 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ * Copyright (c) 1995 Nivas Madhur
+ * Copyright (c) 1994 Gordon W. Ross
+ * Copyright (c) 1993 Adam Glass
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ *	This product includes software developed by the University of
+ *	California, Lawrence Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)clock.c	8.1 (Berkeley) 6/11/93
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1993-1991 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/errno.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/asm_macro.h>
+#include <machine/cmmu.h>
+#include <machine/cpu.h>
+#include <machine/reg.h>
+#include <machine/trap.h>
+
+#include <machine/m88100.h>
+#include <machine/av400.h>
+#include <machine/prom.h>
+
+#include <aviion/dev/sysconreg.h>
+
+u_int	safe_level(u_int mask, u_int curlevel);
+
+void	av400_bootstrap(void);
+void	av400_ext_int(u_int, struct trapframe *);
+u_int	av400_getipl(void);
+void	av400_init_clocks(void);
+vaddr_t	av400_memsize(void);
+u_int	av400_raiseipl(u_int);
+u_int	av400_setipl(u_int);
+void	av400_startup(void);
+
+/*
+ * The MVME188 interrupt arbiter has 25 orthogonal interrupt sources.
+ * On the AViiON machines, there are even more interrupt sources in use,
+ * but differences are minimal.
+ * We fold this model in the 8-level spl model this port uses, enforcing
+ * priorities manually with the interrupt masks.
+ */
+
+/*
+ * Copy of the interrupt enable register for each CPU.
+ * Note that, on the AV400 design, the interrupt enable registers are
+ * write-only and read back as 0xffffffff.
+ */
+unsigned int int_mask_reg[] = { 0, 0, 0, 0 };
+
+unsigned int av400_curspl[] = {0, 0, 0, 0};
+
+/*
+ * external interrupt masks per spl.
+ */
+const unsigned int int_mask_val[INT_LEVEL] = {
+	MASK_LVL_0,
+	MASK_LVL_1,
+	MASK_LVL_2,
+	MASK_LVL_3,
+	MASK_LVL_4,
+	MASK_LVL_5,
+	MASK_LVL_6,
+	MASK_LVL_7
+};
+
+vaddr_t utilva;
+
+/*
+ * Figure out how much memory is available, by asking the PROM.
+ */
+vaddr_t
+av400_memsize()
+{
+	vaddr_t memsize;
+
+	memsize = scm_memsize();
+
+	/*
+	 * What we got is the ``top of memory'', i.e. the largest addressable
+	 * word address, ending in 0xffc. Round up to a multiple of a page.
+	 */
+	memsize = round_page(memsize);
+
+	/*
+	 * But then the PROM uses at least one full page for its own needs...
+	 */
+	memsize -= PAGE_SIZE;
+
+	return (memsize);
+}
+
+void
+av400_startup()
+{
+#if 0
+	/*
+	 * Supply the self-inflicted vector base. Note that since we don't
+	 * use this functionality, this is not really necessary.
+	 * Moreover, writing to this register in av400_bootstrap() causes
+	 * an exception (and at this point we can not handle it).
+	 * This might be a good way to tell 400s from 5000s!
+	 */
+	/* supply a vector base for av400ih */
+	*(volatile u_int8_t *)AV400_VIRQV = AV400_IVEC;
+#endif
+}
+
+int32_t cpuid, sysid;
+
+void
+av400_bootstrap()
+{
+	extern struct cmmu_p cmmu8820x;
+	extern u_char hostaddr[6];
+
+	cmmu = &cmmu8820x;
+	md_interrupt_func_ptr = av400_ext_int;
+	md_getipl = av400_getipl;
+	md_setipl = av400_setipl;
+	md_raiseipl = av400_raiseipl;
+	md_init_clocks = av400_init_clocks;
+
+	/* clear and disable all interrupts */
+	*(volatile u_int32_t *)AV400_IENALL = 0;
+
+	/*
+	 * Get all the information we'll need later from the PROM, while
+	 * we can still use it.
+	 */
+
+	scm_getenaddr(hostaddr);
+	cpuid = scm_cpuid();
+	sysid = scm_sysid();
+}
+
+/*
+ * return next safe spl to reenable interrupts.
+ */
+u_int
+safe_level(u_int mask, u_int curlevel)
+{
+	int i;
+
+	for (i = curlevel; i < INT_LEVEL; i++)
+		if ((int_mask_val[i] & mask) == 0)
+			return i;
+
+	return (INT_LEVEL - 1);
+}
+
+u_int
+av400_getipl(void)
+{
+	return av400_curspl[cpu_number()];
+}
+
+u_int
+av400_setipl(u_int level)
+{
+	u_int32_t mask, curspl;
+	u_int cpu = cpu_number();
+
+	curspl = av400_curspl[cpu];
+
+	mask = int_mask_val[level];
+#ifdef MULTIPROCESSOR
+	if (cpu != master_cpu)
+		mask &= ~SLAVE_MASK;
+#endif
+
+	*(u_int32_t *)AV400_IEN(cpu) = int_mask_reg[cpu] = mask;
+	av400_curspl[cpu] = level;
+
+	return curspl;
+}
+
+u_int
+av400_raiseipl(u_int level)
+{
+	u_int32_t mask, curspl;
+	u_int cpu = cpu_number();
+
+	curspl = av400_curspl[cpu];
+	if (curspl < level) {
+		mask = int_mask_val[level];
+#ifdef MULTIPROCESSOR
+		if (cpu != master_cpu)
+			mask &= ~SLAVE_MASK;
+#endif
+
+		*(u_int32_t *)AV400_IEN(cpu) = int_mask_reg[cpu] = mask;
+		av400_curspl[cpu] = level;
+	}
+	return curspl;
+}
+
+/*
+ * Device interrupt handler for AV400
+ */
+
+/*
+ * Hard coded vector table for onboard devices and hardware failure
+ * interrupts.
+ */
+const unsigned int obio_vec[32] = {
+	0,		/* SWI0 */
+	0,		/* SWI1 */
+	0,
+	0,
+	0,		/* VME1 */
+	SYSCV_SCSI,	/* SCI */
+	0,		/* VME2 */
+	0,
+	0,
+	0,		/* DVB */
+	0,		/* VME3 */
+	0,		/* DWP */
+	0,		/* VME4 */
+	0,		/* DTC */
+	0,		/* VME5 */
+	SYSCV_LE,	/* ECI */
+	SYSCV_SCC2,	/* DI2 */
+	SYSCV_SCC,	/* DI1 */
+	0,		/* PPI */
+	0,		/* VME6 */
+	SYSCV_SYSF,	/* SF */
+	SYSCV_TIMER2,	/* CIOI */
+	0,		/* KBD */
+	0,		/* VME7 */
+	0,		/* PAR */
+	0,		/* VID */
+	0,		/* ZBUF */
+	0,
+	0,
+	0,		/* ARBTO */	/* no vector, but always masked */
+	SYSCV_ACF,	/* ACF */
+	SYSCV_ABRT	/* ABORT */
+};
+
+#define VME_VECTOR_MASK		0x1ff 	/* mask into VIACK register */
+#define VME_BERR_MASK		0x100 	/* timeout during VME IACK cycle */
+
+void
+av400_ext_int(u_int v, struct trapframe *eframe)
+{
+	int cpu = cpu_number();
+	unsigned int cur_mask, ign_mask;
+	unsigned int level, old_spl;
+	struct intrhand *intr;
+	intrhand_t *list;
+	int ret, intbit;
+	vaddr_t ivec;
+	u_int vec;
+	int unmasked = 0;
+#ifdef DIAGNOSTIC
+	static int problems = 0;
+#endif
+
+	cur_mask = ISR_GET_CURRENT_MASK(cpu);
+	ign_mask = 0;
+	old_spl = av400_curspl[cpu];
+	eframe->tf_mask = old_spl;
+
+	if (cur_mask == 0) {
+		/*
+		 * Spurious interrupts - may be caused by debug output clearing
+		 * DUART interrupts.
+		 */
+		flush_pipeline();
+		goto out;
+	}
+
+	uvmexp.intrs++;
+
+	/*
+	 * We want to service all interrupts marked in the IST register
+	 * They are all valid because the mask would have prevented them
+	 * from being generated otherwise.  We will service them in order of
+	 * priority.
+	 */
+	do {
+		level = safe_level(cur_mask, old_spl);
+
+#ifdef DIAGNOSTIC
+		if (level != IPL_ABORT && level <= old_spl) {
+			int i;
+
+			printf("safe level %d <= old level %d\n", level, old_spl);
+			printf("cur_mask = 0x%b\n", cur_mask, IST_STRING);
+			for (i = 0; i < 4; i++)
+				printf("IEN%d = 0x%b\n", i, int_mask_reg[i], IST_STRING);
+			printf("\nCPU0 spl %d  CPU1 spl %d  CPU2 spl %d  CPU3 spl %d\n",
+			       av400_curspl[0], av400_curspl[1],
+			       av400_curspl[2], av400_curspl[3]);
+			for (i = 0; i < INT_LEVEL; i++)
+				printf("int_mask[%d] = 0x%08x\n", i, int_mask_val[i]);
+			printf("--CPU %d halted--\n", cpu_number());
+			setipl(IPL_ABORT);
+			for(;;) ;
+		}
+#endif
+
+		setipl(level);
+
+		/*
+		 * Do not enable interrupts yet if we know, from cur_mask,
+		 * that we have not cleared enough conditions yet.
+		 * For now, only the timer interrupt requires its condition
+		 * to be cleared before interrupts are enabled.
+		 */
+		if (unmasked == 0 /* && (cur_mask & whatever) == 0 */) {
+			set_psr(get_psr() & ~PSR_IND);
+			unmasked = 1;
+		}
+
+		/* find the first bit set in the current mask */
+		intbit = ff1(cur_mask);
+		if (OBIO_INTERRUPT_MASK & (1 << intbit)) {
+			vec = obio_vec[intbit];
+			if (vec == 0) {
+				panic("unknown onboard interrupt: mask = 0x%b",
+				    1 << intbit, IST_STRING);
+			}
+			vec += SYSCON_VECT;
+		} else if (HW_FAILURE_MASK & (1 << intbit)) {
+			vec = obio_vec[intbit];
+			if (vec == 0) {
+				panic("unknown hardware failure: mask = 0x%b",
+				    1 << intbit, IST_STRING);
+			}
+			vec += SYSCON_VECT;
+		} else if (VME_INTERRUPT_MASK & (1 << intbit)) {
+			ivec = AV400_VIRQLV + (level << 2);
+			vec = *(volatile u_int32_t *)ivec & VME_VECTOR_MASK;
+			if (vec & VME_BERR_MASK) {
+				/*
+				 * This could be a self-inflicted interrupt.
+				 * Except that we never write to VIRQV, so
+				 * such things do not happen.
+				 * Moreover, the AV400 design does not
+				 * implement this feature.
+
+				u_int src = 0x07 &
+				    *(volatile u_int32_t *)AV400_VIRQLV;
+				if (src == 0)
+					vec = 0xff &
+					    *(volatile u_int32_t *)AV400_VIRQV;
+				else
+
+				 */
+				{
+					printf("%s: timeout getting VME "
+					    "interrupt vector, "
+					    "level %d, mask 0x%b\n",
+					    __func__, level,
+					    cur_mask, IST_STRING);
+					ign_mask |= 1 << intbit;
+					continue;
+				}
+			}
+			if (vec == 0) {
+				panic("%s: invalid VME interrupt vector, "
+				    "level %d, mask 0x%b",
+				    __func__, level, cur_mask, IST_STRING);
+			}
+		} else {
+			panic("%s: unexpected interrupt source, "
+			    "level %d, mask 0x%b",
+			    __func__, level, cur_mask, IST_STRING);
+		}
+
+		list = &intr_handlers[vec];
+		if (SLIST_EMPTY(list)) {
+			printf("%s: spurious interrupt, "
+			    "level %d, vec 0x%x, mask 0x%b\n",
+			    __func__, level, vec, cur_mask, IST_STRING);
+			ign_mask |= 1 << intbit;
+		} else {
+			/*
+			 * Walk through all interrupt handlers in the chain
+			 * for the given vector, calling each handler in turn,
+			 * till some handler returns a value != 0.
+			 */
+			ret = 0;
+			SLIST_FOREACH(intr, list, ih_link) {
+				if (intr->ih_wantframe != 0)
+					ret = (*intr->ih_fn)((void *)eframe);
+				else
+					ret = (*intr->ih_fn)(intr->ih_arg);
+				if (ret != 0) {
+					intr->ih_count.ec_count++;
+					break;
+				}
+			}
+			if (ret == 0) {
+				panic("%s: unclaimed interrupt, "
+				    "level %d, vec %x, mask 0x%b"
+				    __func__, level, vec, cur_mask, IST_STRING);
+				ign_mask |= 1 << intbit;
+				break;
+			}
+		}
+	} while (((cur_mask = ISR_GET_CURRENT_MASK(cpu)) & ~ign_mask) != 0);
+
+#ifdef DIAGNOSTIC
+	if (ign_mask != 0) {
+		if (++problems >= 10)
+			panic("%s: broken interrupt behaviour", __func__);
+	} else
+		problems = 0;
+#endif
+
+	/*
+	 * process any remaining data access exceptions before
+	 * returning to assembler
+	 */
+	set_psr(get_psr() | PSR_IND);
+out:
+	if (eframe->tf_dmt0 & DMT_VALID)
+		m88100_trap(T_DATAFLT, eframe);
+
+	/*
+	 * Restore the mask level to what it was when the interrupt
+	 * was taken.
+	 */
+	av400_setipl(eframe->tf_mask);
+}
+
+/*
+ * Clock routines
+ */
+
+void	av400_cio_init(unsigned);
+u_int	read_cio(int);
+void	write_cio(int, u_int);
+
+struct intrhand	clock_ih;
+
+int	av400_clockintr(void *);
+
+struct simplelock av400_cio_lock;
+
+#define	CIO_LOCK	simple_lock(&av400_cio_lock)
+#define	CIO_UNLOCK	simple_unlock(&av400_cio_lock)
+
+/*
+ * Statistics clock interval and variance, in usec.  Variance must be a
+ * power of two.  Since this gives us an even number, not an odd number,
+ * we discard one case and compensate.  That is, a variance of 4096 would
+ * give us offsets in [0..4095].  Instead, we take offsets in [1..4095].
+ * This is symmetric about the point 2048, or statvar/2, and thus averages
+ * to that value (assuming uniform random numbers).
+ */
+int statvar = 8192;
+int statmin;			/* statclock interval - 1/2*variance */
+
+/*
+ * Notes on the AV400 clock usage:
+ *
+ * Unlike the MVME188 design, we only have access to three counter/timers
+ * in the Zilog Z8536 (since we can not receive the DUART timer interrupts).
+ *
+ * Clock is run on a Z8536 counter, kept in counter mode and retriggered
+ * every interrupt (when using the Z8536 in timer mode, it _seems_ that it
+ * resets at 0xffff instead of the initial count value...)
+ *
+ * It should be possible to run statclock on the Z8536 counter #2, but
+ * this would make interrupt handling more tricky, in the case both
+ * counters interrupt at the same time...
+ */
+
+void
+av400_init_clocks(void)
+{
+
+	simple_lock_init(&av400_cio_lock);
+
+#ifdef DIAGNOSTIC
+	if (1000000 % hz) {
+		printf("cannot get %d Hz clock; using 100 Hz\n", hz);
+		hz = 100;
+	}
+#endif
+	tick = 1000000 / hz;
+
+	av400_cio_init(tick);
+
+	stathz = 0;
+
+	clock_ih.ih_fn = av400_clockintr;
+	clock_ih.ih_arg = 0;
+	clock_ih.ih_wantframe = 1;
+	clock_ih.ih_ipl = IPL_CLOCK;
+	sysconintr_establish(SYSCV_TIMER2, &clock_ih, "clock");
+}
+
+int
+av400_clockintr(void *eframe)
+{
+	CIO_LOCK;
+	write_cio(CIO_CSR1, CIO_GCB | CIO_CIP);  /* Ack the interrupt */
+
+	hardclock(eframe);
+
+	/* restart counter */
+	write_cio(CIO_CSR1, CIO_GCB | CIO_TCB | CIO_IE);
+	CIO_UNLOCK;
+
+	return (1);
+}
+
+/* Write CIO register */
+void
+write_cio(int reg, u_int val)
+{
+	int s;
+	volatile int i;
+	volatile u_int32_t * cio_ctrl = (volatile u_int32_t *)CIO_CTRL;
+
+	s = splclock();
+	CIO_LOCK;
+
+	i = *cio_ctrl;				/* goto state 1 */
+	*cio_ctrl = 0;				/* take CIO out of RESET */
+	i = *cio_ctrl;				/* reset CIO state machine */
+
+	*cio_ctrl = (reg & 0xff);		/* select register */
+	*cio_ctrl = (val & 0xff);		/* write the value */
+
+	CIO_UNLOCK;
+	splx(s);
+}
+
+/* Read CIO register */
+u_int
+read_cio(int reg)
+{
+	int c, s;
+	volatile int i;
+	volatile u_int32_t * cio_ctrl = (volatile u_int32_t *)CIO_CTRL;
+
+	s = splclock();
+	CIO_LOCK;
+
+	/* select register */
+	*cio_ctrl = (reg & 0xff);
+	/* delay for a short time to allow 8536 to settle */
+	for (i = 0; i < 100; i++)
+		;
+	/* read the value */
+	c = *cio_ctrl;
+	CIO_UNLOCK;
+	splx(s);
+	return (c & 0xff);
+}
+
+/*
+ * Initialize the CTC (8536)
+ * Only the counter/timers are used - the IO ports are un-comitted.
+ */
+void
+av400_cio_init(unsigned period)
+{
+	volatile int i;
+
+	CIO_LOCK;
+
+	/* Start by forcing chip into known state */
+	read_cio(CIO_MICR);
+	write_cio(CIO_MICR, CIO_MICR_RESET);	/* Reset the CTC */
+	for (i = 0; i < 1000; i++)	 	/* Loop to delay */
+		;
+
+	/* Clear reset and start init seq. */
+	write_cio(CIO_MICR, 0x00);
+
+	/* Wait for chip to come ready */
+	while ((read_cio(CIO_MICR) & CIO_MICR_RJA) == 0)
+		;
+
+	/* Initialize the 8536 for real */
+	write_cio(CIO_MICR,
+	    CIO_MICR_MIE /* | CIO_MICR_NV */ | CIO_MICR_RJA | CIO_MICR_DLC);
+	write_cio(CIO_CTMS1, CIO_CTMS_CSC);	/* Continuous count */
+	write_cio(CIO_PDCB, 0xff);		/* set port B to input */
+
+	period <<= 1;	/* CT#1 runs at PCLK/2, hence 2MHz */
+	write_cio(CIO_CT1MSB, period >> 8);
+	write_cio(CIO_CT1LSB, period);
+	/* enable counter #1 */
+	write_cio(CIO_MCCR, CIO_MCCR_CT1E | CIO_MCCR_PBE);
+	write_cio(CIO_CSR1, CIO_GCB | CIO_TCB | CIO_IE);
+
+	CIO_UNLOCK;
+}
diff --git a/sys/arch/aviion/dev/dartreg.h b/sys/arch/aviion/dev/dartreg.h
new file mode 100644
index 00000000000..6218b9e91af
--- /dev/null
+++ b/sys/arch/aviion/dev/dartreg.h
@@ -0,0 +1,181 @@
+/*	$OpenBSD: dartreg.h,v 1.1.1.1 2006/05/09 18:24:15 miod Exp $	*/
+
+#define MAXPORTS	2		/* max count of PORTS/DUART */
+
+#define  A_PORT   0  /* flag for port a */
+#define  B_PORT   1  /* flag for port b */
+
+/* the access to the same command register must be delayed,
+   because the chip has some hardware problems in this case */
+#define DELAY_CR   do { volatile int i; for (i = 0; i < 250; ++i); } while (0)
+
+/*********************** MC68681 DEFINITIONS ************************/
+
+/* mode register 1: MR1x operations */
+#define RXRTS        0x80  /* enable receiver RTS */
+#define PAREN        0x00  /* with parity */
+#define PARDIS       0x10  /* no parity */
+#define EVENPAR      0x00  /* even parity */
+#define ODDPAR       0x04  /* odd parity */
+#define CL5          0x00  /* 5 bits per char */
+#define CL6          0x01  /* 6 bits per char */
+#define CL7          0x02  /* 7 bits per char */
+#define CL8          0x03  /* 8 bits per char */
+#define PARMODEMASK  0x18  /* parity mode mask */
+#define PARTYPEMASK  0x04  /* parity type mask */
+#define CLMASK       0x03  /* character length mask */
+
+/* mode register 2: MR2x operations */
+#define TXRTS        0x20  /* enable transmitter RTS */
+#define TXCTS        0x10  /* enable transmitter CTS */
+#define SB2          0x0f  /* 2 stop bits */
+#define SB1          0x07  /* 1 stop bit */
+#define SB1L5        0x00  /* 1 stop bit at 5 bits per character */
+
+#define SBMASK       0x0f  /* stop bit mask */
+
+/* clock-select register: CSRx operations */
+#define NOBAUD       -1    /* 50 and 200 baud are not possible */
+/* they are not in Baud register set 2 */
+#define BD75         0x00  /* 75 baud */
+#define BD110        0x11  /* 110 baud */
+#define BD134        0x22  /* 134.5 baud */
+#define BD150        0x33  /* 150 baud */
+#define BD300        0x44  /* 300 baud */
+#define BD600        0x55  /* 600 baud */
+#define BD1200       0x66  /* 1200 baud */
+#define BD1800       0xaa  /* 1800 baud */
+#define BD2400       0x88  /* 2400 baud */
+#define BD4800       0x99  /* 4800 baud */
+#define BD9600       0xbb  /* 9600 baud */
+#define BD19200      0xcc  /* 19200 baud */
+
+#define DEFBAUD      BD9600   /* default value if baudrate is not possible */
+
+
+/* channel command register: CRx operations */
+#define MRRESET      0x10  /* reset mr pointer to mr1 */
+#define RXRESET      0x20  /* reset receiver */
+#define TXRESET      0x30  /* reset transmitter */
+#define ERRRESET     0x40  /* reset error status */
+#define BRKINTRESET  0x50  /* reset channel's break interrupt */
+#define BRKSTART     0x60  /* start break */
+#define BRKSTOP      0x70  /* stop break */
+#define TXDIS        0x08  /* disable transmitter */
+#define TXEN         0x04  /* enable transmitter */
+#define RXDIS        0x02  /* disable receiver */
+#define RXEN         0x01  /* enable receiver */
+
+/* status register: SRx status */
+#define RBRK         0x80  /* received break */
+#define FRERR        0x40  /* frame error */
+#define PERR         0x20  /* parity error */
+#define ROVRN        0x10  /* receiver overrun error */
+#define TXEMT        0x08  /* transmitter empty */
+#define TXRDY        0x04  /* transmitter ready */
+#define FFULL        0x02  /* receiver FIFO full */
+#define RXRDY        0x01  /* receiver ready */
+
+/* output port configuration register: OPCR operations */
+#define OPSET        0x00  /* set all op lines to op function */
+#define OPSETTO      0x04  /* use OP3 for timer output */
+
+/* output port register: OP operations */
+#define OPDTRB       0x20  /* DTR line output b on the VME188, 181, 141 */
+#define OPDTRA       0x04  /* DTR line output a */
+#define OPRTSB       0x02  /* RTS line output b */
+#define OPRTSA       0x01  /* RTS line output a */
+
+/* auxiliary control register: ACR operations */
+#define BDSET1       0x00  /* baudrate generator set 1 */
+#define BDSET2       0x80  /* baudrate generator set 2 */
+#define CCLK1        0x60  /* timer clock: external rate.  TA */
+#define CCLK16       0x30  /* counter clock: x1 clk divided by 16 */
+#define SLCTIM       0x7800/* timer count to get 60 Hz time slice (16.6ms ticks) */
+#define IPDCDIB      0x08  /* IP3 change == DCD input on port B */
+#define IPDCDIA      0x04  /* IP2 change == DCD input on port A */
+
+/* input port change register: IPCR operations */
+#define IPCRDCDB     0x80  /* IP3 change == DCD change on port B */
+#define IPCRDCDA     0x40  /* IP2 change == DCD change on port A */
+
+/* Defines for mvme335 */
+#define IPDCDB       0x20  /* DCD line input b */
+#define IPDCDA       0x10  /* DCD line input a */
+
+#define IPDSRB       0x08  /* DSR line input b */
+#define IPDSRA       0x04  /* DSR line input a */
+#define IPCTSB       0x02  /* CTS line input b */
+#define IPCTSA       0x01  /* CTS line input a */
+
+/* interrupt status and mask register: ISR status and IMR mask */
+#define IIPCHG       0x80  /* input port change */
+#define IBRKB        0x40  /* delta break b */
+#define IRXRDYB      0x20  /* receiver ready b */
+#define ITXRDYB      0x10  /* transmitter ready b */
+#define ITIMER       0x08  /* Enable timer interrupts. */
+#define IBRKA        0x04  /* delta break a */
+#define IRXRDYA      0x02  /* receiver ready a */
+#define ITXRDYA      0x01  /* transmitter ready a */
+
+/* interrupts from port a or b */
+#define AINTPORT  ( IRXRDYA | ITXRDYA )
+#define BINTPORT  ( IRXRDYB | ITXRDYB )
+
+/* HW write register index for ut_wr_regs[] */
+#define MR1A         0  /* mode register 1 a */
+#define CSRA         1  /* clock-select register a*/
+#define CRA          2  /* command register a */
+#define TBA          3  /* transmitter buffer a */
+#define ACR          4  /* auxiliary control register*/
+#define IMR          5  /* interrupt mask register */
+#define CTUR         6  /* counter/timer upper reg */
+#define CTLR         7  /* counter/timer lower reg */
+#define MR1B         8  /* mode register 1 b */
+#define CSRB         9  /* clock-select register b*/
+#define CRB          10 /* command register b */
+#define TBB          11 /* transmitter buffer b */
+#define IVR          12 /* interrupt vector register */
+#define OPCR         13 /* output port config reg */
+#define OPRSET       14 /* output port: bit set cmd */
+#define OPRRESET     15 /* output port: bit reset cmd */
+#define MR2A         16 /* mode register 2 a */
+#define MR2B         17 /* mode register 2 b */
+#define MAXREG       18 /* max count of registers */
+
+/*
+ *	MC68681 hardware registers.
+ */
+
+#define	DART_MR1A	0x00	/* RW: mode register A */
+#define	DART_MR2A	0x00	/* RW: mode register A */
+#define	DART_SRA	0x01	/* R: status register A */
+#define	DART_CSRA	0x01	/* W: clock select register A */
+#define	DART_CRA	0x02	/* W: command register A */
+#define	DART_RBA	0x03	/* R: receiver buffer A */
+#define	DART_TBA	0x03	/* W: transmit buffer A */
+#define	DART_IPCR	0x04	/* R: input port change register */
+#define	DART_ACR	0x04	/* W: auxiliary control register */
+#define	DART_ISR	0x05	/* R: interrupt status register */
+#define	DART_IMR	0x05	/* W: interrupt mask register */
+#define	DART_CUR	0x06	/* R: count upper register */
+#define	DART_CTUR	0x06	/* W: counter/timer upper register */
+#define	DART_CLR	0x07	/* R: count lower register */
+#define	DART_CTLR	0x07	/* W: counter/timer lower register */
+#define	DART_MR1B	0x08	/* RW: mode register B */
+#define	DART_MR2B	0x08	/* RW: mode register B */
+#define	DART_SRB	0x09	/* R: status register B */
+#define	DART_CSRB	0x09	/* W: clock select register B */
+#define	DART_CRB	0x0a	/* W: command register B */
+#define	DART_RBB	0x0b	/* R: receiver buffer B */
+#define	DART_TBB	0x0b	/* W: transmit buffer B */
+#define	DART_IVR	0x0c	/* RW: interrupt vector register */
+#define	DART_IP		0x0d	/* R: input port (unlatched) */
+#define	DART_OPCR	0x0d	/* W: output port configuration register */
+#define	DART_CTSTART	0x0e	/* R: start counter command */
+#define	DART_OPRS	0x0e	/* W: output port bit set */
+#define	DART_CTSTOP	0x0f	/* R: stop counter command */
+#define	DART_OPRR	0x0f	/* W: output port bit reset */
+
+#define	DART_A_BASE	0x00
+#define	DART_B_BASE	0x08
diff --git a/sys/arch/aviion/dev/if_le_vme.c b/sys/arch/aviion/dev/if_le_vme.c
new file mode 100644
index 00000000000..658ec2ddd16
--- /dev/null
+++ b/sys/arch/aviion/dev/if_le_vme.c
@@ -0,0 +1,382 @@
+/*	$OpenBSD: if_le_vme.c,v 1.1 2006/05/09 18:24:32 miod Exp $	*/
+
+/*-
+ * Copyright (c) 1982, 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)if_le.c	8.2 (Berkeley) 10/30/93
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/mbuf.h>
+#include <sys/syslog.h>
+#include <sys/socket.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+
+#include <net/if.h>
+
+#ifdef INET
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#endif
+
+#include <net/if_media.h>
+
+#include <machine/autoconf.h>
+#include <machine/bus.h>
+#include <machine/cpu.h>
+
+#include <dev/ic/am7990reg.h>
+#include <dev/ic/am7990var.h>
+
+#include <aviion/dev/if_le_vmereg.h>
+#include <aviion/dev/vmevar.h>
+
+struct	le_softc {
+	struct am7990_softc	sc_am7990;	/* glue to MI code */
+
+	bus_space_tag_t		sc_memt;	/* dual-ported memory access */
+	bus_space_handle_t	sc_memh;
+
+	bus_space_tag_t		sc_iot;		/* short io access */
+	bus_space_handle_t	sc_ioh;
+
+	struct intrhand		sc_ih;		/* interrupt vectoring */
+	u_int			sc_csr;		/* CSR image */
+	u_int			sc_ipl;
+	u_int			sc_vec;
+};
+
+void  le_vme_attach(struct device *, struct device *, void *);
+int   le_vme_match(struct device *, void *, void *);
+
+struct cfattach le_vme_ca = {
+	sizeof(struct le_softc), le_vme_match, le_vme_attach
+};
+
+void	le_vme_wrcsr(struct am7990_softc *, u_int16_t, u_int16_t);
+u_int16_t le_vme_rdcsr(struct am7990_softc *, u_int16_t);
+void	nvram_cmd(struct am7990_softc *, u_int, u_int);
+u_int16_t nvram_read(struct am7990_softc *, u_int);
+void	le_vme_etheraddr(struct am7990_softc *);
+void	le_vme_init(struct am7990_softc *);
+void	le_vme_reset(struct am7990_softc *);
+int	le_vme_intr(void *);
+#if 0
+void	le_vme_copyfrombuf_contig(struct am7990_softc *, void *, int, int);
+void	le_vme_copytobuf_contig(struct am7990_softc *, void *, int, int);
+void	le_vme_zerobuf_contig(struct am7990_softc *, int, int);
+#endif
+
+/* send command to the nvram controller */
+void
+nvram_cmd(sc, cmd, addr)
+	struct am7990_softc *sc;
+	u_int cmd;
+	u_int addr;
+{
+	struct le_softc *lesc = (void *)sc;
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_EAR,
+		    (cmd | (addr << 1)) >> i);
+		CDELAY; 
+	} 
+}
+
+/* read nvram one bit at a time */
+u_int16_t
+nvram_read(sc, nvram_addr)
+	struct am7990_softc *sc;
+	u_int nvram_addr;
+{
+	struct le_softc *lesc = (void *)sc;
+	u_int val = 0, mask = 0x04000;
+	u_int16_t wbit;
+
+	lesc->sc_csr = HW_RS | NVRAM_EN | 0x07;
+	ENABLE_NVRAM;
+	nvram_cmd(sc, NVRAM_RCL, 0);
+	DISABLE_NVRAM;
+	CDELAY;
+	ENABLE_NVRAM;
+	nvram_cmd(sc, NVRAM_READ, nvram_addr);
+	for (wbit = 0; wbit < 15; wbit++) {
+		if (bus_space_read_2(lesc->sc_iot, lesc->sc_ioh,
+		    LEREG_EAR) & 0x01)
+			val |= mask;
+		else
+			val &= ~mask;
+		mask = mask >> 1;
+		CDELAY;
+	}
+	if (bus_space_read_2(lesc->sc_iot, lesc->sc_ioh, LEREG_EAR) & 0x01)
+		val |= 0x8000;
+	else
+		val &= 0x7fff;
+	CDELAY;
+	DISABLE_NVRAM;
+	return (val);
+}
+
+void
+le_vme_etheraddr(sc)
+	struct am7990_softc *sc;
+{
+	u_char *cp = sc->sc_arpcom.ac_enaddr;
+	u_int16_t ival[3];
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		ival[i] = nvram_read(sc, i);
+	}
+	memcpy(cp, &ival[0], 6);
+}
+
+void
+le_vme_wrcsr(sc, port, val)
+	struct am7990_softc *sc;
+	u_int16_t port, val;
+{
+	struct le_softc *lesc = (void *)sc;
+
+	bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RAP, port);
+	bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RDP, val);
+}
+
+u_int16_t
+le_vme_rdcsr(sc, port)
+	struct am7990_softc *sc;
+	u_int16_t port;
+{
+	struct le_softc *lesc = (void *)sc;
+
+	bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RAP, port);
+	return (bus_space_read_2(lesc->sc_iot, lesc->sc_ioh, LEREG_RDP));
+}
+
+/* init board, set ipl and vec */
+void
+le_vme_init(sc)
+	struct am7990_softc *sc;
+{
+	struct le_softc *lesc = (void *)sc;
+
+	lesc->sc_csr = 0x4f;
+	WRITE_CSR_AND(lesc->sc_ipl);
+	SET_VEC(lesc->sc_vec);
+	return;
+}
+
+/* board reset */
+void
+le_vme_reset(sc)
+	struct am7990_softc *sc;
+{
+	struct le_softc *lesc = (void *)sc;
+
+	RESET_HW;
+#ifdef LEDEBUG
+	if (sc->sc_debug)
+		printf("%s: hardware reset\n", sc->sc_dev.dv_xname);
+#endif
+	SYSFAIL_CL;
+}
+
+int
+le_vme_intr(sc)
+	void *sc;
+{
+	struct le_softc *lesc = (void *)sc;
+	int rc;
+
+	rc = am7990_intr(sc);
+	ENABLE_INTR;
+	return (rc);
+}
+
+#if 0
+void
+le_vme_copytobuf_contig(sc, from, boff, len)
+	struct am7990_softc *sc;
+	void *from;
+	int boff, len;
+{
+	struct le_softc *lesc = (void *)sc;
+
+	bus_space_write_region_1(lesc->sc_memt, lesc->sc_memh, boff, from, len);
+}
+
+void
+le_vme_copyfrombuf_contig(sc, to, boff, len)
+	struct am7990_softc *sc;
+	void *to;
+	int boff, len;
+{
+	struct le_softc *lesc = (void *)sc;
+
+	bus_space_read_region_1(lesc->sc_memt, lesc->sc_memh, boff, to, len);
+}
+
+void
+le_vme_zerobuf_contig(sc, boff, len)
+	struct am7990_softc *sc;
+	int boff, len;
+{
+	struct le_softc *lesc = (void *)sc;
+
+	bus_space_set_region_1(lesc->sc_memt, lesc->sc_memh, boff, 0, len);
+}
+#endif
+
+int
+le_vme_match(parent, vcf, args)
+	struct device *parent;
+	void *vcf, *args;
+{
+	struct vme_attach_args *vaa = args;
+	bus_space_tag_t iot, memt;
+	bus_space_handle_t ioh;
+	int rc;
+
+	/* we expect a32 and a16 locators */
+	if (vaa->vaa_addr_a16 == (vme_addr_t)-1 ||
+	    vaa->vaa_addr_a32 == (vme_addr_t)-1)
+		return (0);
+
+	/* check the dual ported memory */
+	if (vmebus_get_bst(parent, VME_A32, VME_D32, &memt) != 0)
+		return (0);
+	if (bus_space_map(memt, vaa->vaa_addr_a32, PAGE_SIZE, 0, &ioh) != 0)
+		return (0);
+	rc = badaddr((vaddr_t)bus_space_vaddr(memt, ioh), 2);
+	bus_space_unmap(memt, ioh, PAGE_SIZE);
+	vmebus_release_bst(parent, memt);
+
+	/* check the control space */
+	if (vmebus_get_bst(parent, VME_A16, VME_D16, &iot) != 0)
+		return (0);
+	if (bus_space_map(iot, vaa->vaa_addr_a16, PAGE_SIZE, 0, &ioh) != 0)
+		return (0);
+	rc |= badaddr((vaddr_t)bus_space_vaddr(iot, ioh), 2);
+	bus_space_unmap(iot, ioh, PAGE_SIZE);
+	vmebus_release_bst(parent, iot);
+
+	return (rc == 0);
+}
+
+void
+le_vme_attach(parent, self, aux)
+	struct device *parent;
+	struct device *self;
+	void *aux;
+{
+	struct le_softc *lesc = (struct le_softc *)self;
+	struct am7990_softc *sc = &lesc->sc_am7990;
+	struct vme_attach_args *vaa = aux;
+
+	/*
+	 * Allocate an interrupt vector.
+	 */
+	if (vmeintr_allocate(1, VMEINTR_ANY, &lesc->sc_vec) != 0) {
+		printf(": no more interrupts!\n");
+		return;
+	}
+	lesc->sc_ipl = vaa->vaa_ipl == 0 ? IPL_NET : vaa->vaa_ipl;
+
+	/*
+	 * Map the dual-ported memory.
+	 */
+	if (vmebus_get_bst(parent, VME_A32, VME_D32, &lesc->sc_memt) != 0) {
+		printf(": can't map memory\n");
+		return;
+	}
+	if (bus_space_map(lesc->sc_memt, vaa->vaa_addr_a32, VLEMEMSIZE,
+	    BUS_SPACE_MAP_LINEAR, &lesc->sc_memh) != 0) {
+		printf(": can't map memory\n");
+		goto fail3;
+	}
+
+	/*
+	 * Map the control space.
+	 */
+	if (vmebus_get_bst(parent, VME_A16, VME_D16, &lesc->sc_iot) != 0) {
+		printf(": can't map registers\n");
+		goto fail2;
+	}
+	if (bus_space_map(lesc->sc_iot, vaa->vaa_addr_a16, PAGE_SIZE,
+	    0, &lesc->sc_ioh) != 0) {
+		printf(": can't map registers\n");
+		goto fail1;
+	}
+
+	sc->sc_mem = (void *)bus_space_vaddr(lesc->sc_memt, lesc->sc_memh);
+	sc->sc_memsize = VLEMEMSIZE;
+	sc->sc_addr = vaa->vaa_addr_a32 & 0x00ffffff;
+	sc->sc_conf3 = LE_C3_BSWP;
+	sc->sc_hwreset = le_vme_reset;
+	sc->sc_rdcsr = le_vme_rdcsr;
+	sc->sc_wrcsr = le_vme_wrcsr;
+	sc->sc_hwinit = le_vme_init;
+#if 0
+	sc->sc_copytodesc = le_vme_copytobuf_contig;
+	sc->sc_copyfromdesc = le_vme_copyfrombuf_contig;
+	sc->sc_copytobuf = le_vme_copytobuf_contig;
+	sc->sc_copyfrombuf = le_vme_copyfrombuf_contig;
+	sc->sc_zerobuf = le_vme_zerobuf_contig;
+#else
+	sc->sc_copytodesc = am7990_copytobuf_contig;
+	sc->sc_copyfromdesc = am7990_copyfrombuf_contig;
+	sc->sc_copytobuf = am7990_copytobuf_contig;
+	sc->sc_copyfrombuf = am7990_copyfrombuf_contig;
+	sc->sc_zerobuf = am7990_zerobuf_contig;
+#endif
+
+	/* get Ethernet address */
+	le_vme_etheraddr(sc);
+
+	am7990_config(sc);
+
+	/* connect the interrupt */
+	lesc->sc_ih.ih_fn = le_vme_intr;
+	lesc->sc_ih.ih_arg = sc;
+	lesc->sc_ih.ih_wantframe = 0;
+	lesc->sc_ih.ih_ipl = lesc->sc_ipl;
+	vmeintr_establish(lesc->sc_vec, &lesc->sc_ih, self->dv_xname);
+
+	return;
+
+fail1:
+	vmebus_release_bst(parent, lesc->sc_iot);
+fail2:
+	bus_space_unmap(lesc->sc_memt, lesc->sc_memh, VLEMEMSIZE);
+fail3:
+	vmebus_release_bst(parent, lesc->sc_memt);
+}
diff --git a/sys/arch/aviion/dev/if_le_vmereg.h b/sys/arch/aviion/dev/if_le_vmereg.h
new file mode 100644
index 00000000000..f006b23edba
--- /dev/null
+++ b/sys/arch/aviion/dev/if_le_vmereg.h
@@ -0,0 +1,85 @@
+/*	$OpenBSD: if_le_vmereg.h,v 1.1.1.1 2006/05/09 18:25:00 miod Exp $ */
+
+/*-
+ * Copyright (c) 1982, 1992, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)if_lereg.h	8.2 (Berkeley) 10/30/93
+ */
+
+#define	VLEMEMSIZE	0x00040000	/* 256 KB */
+
+/*
+ * LANCE registers for Interphase 3207 Hawk
+ */
+
+#define	LEREG_CSR	0x00
+#define	LEREG_VEC	0x02
+#define	LEREG_RDP	0x04
+#define	LEREG_RAP	0x06
+#define	LEREG_EAR	0x08
+
+/* CSR bits */
+#define	NVRAM_EN	0x0008	/* NVRAM enable bit (active low) */
+#define	INTR_EN		0x0010	/* interrupt enable bit (active low) */
+#define	PARITYB		0x0020	/* parity error clear bit */
+#define	HW_RS		0x0040	/* hardware reset bit (active low) */
+#define	SYSFAILB	0x0080	/* SYSFAIL bit */
+
+#define	NVRAM_RWEL	0xe0	/* Reset write enable latch      */
+#define	NVRAM_STO	0x60	/* Store ram to eeprom           */
+#define	NVRAM_SLP	0xa0	/* Novram into low power mode    */
+#define	NVRAM_WRITE	0x20	/* Writes word from location x   */
+#define	NVRAM_SWEL	0xc0	/* Set write enable latch        */
+#define	NVRAM_RCL	0x40	/* Recall eeprom data into ram   */
+#define	NVRAM_READ	0x00	/* Reads word from location x    */
+
+#define	CDELAY		delay(10000)
+#define	WRITE_CSR_OR(x) \
+	do { \
+		lesc->sc_csr |= (x); \
+		bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, \
+		    LEREG_CSR, lesc->sc_csr); \
+	} while (0)
+#define	WRITE_CSR_AND(x) \
+	do { \
+		lesc->sc_csr &= ~(x); \
+		bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, \
+		    LEREG_CSR, lesc->sc_csr); \
+	} while (0)
+#define	ENABLE_NVRAM	WRITE_CSR_AND(NVRAM_EN)
+#define	DISABLE_NVRAM	WRITE_CSR_OR(NVRAM_EN)
+#define	ENABLE_INTR	WRITE_CSR_AND(INTR_EN)
+#define	DISABLE_INTR	WRITE_CSR_OR(INTR_EN)
+#define	RESET_HW \
+	do { \
+		WRITE_CSR_AND(HW_RS); \
+		CDELAY; \
+	} while (0)
+#define	SET_VEC(x) \
+	bus_space_write_2(lesc->sc_iot, lesc->sc_ioh, LEREG_VEC, (x))
+#define	SYSFAIL_CL	WRITE_CSR_AND(SYSFAILB)
diff --git a/sys/arch/aviion/include/av400.h b/sys/arch/aviion/include/av400.h
new file mode 100644
index 00000000000..dd654b4a602
--- /dev/null
+++ b/sys/arch/aviion/include/av400.h
@@ -0,0 +1,323 @@
+/*	$OpenBSD: av400.h,v 1.1 2006/05/09 18:23:59 miod Exp $	*/
+/*
+ * Copyright (c) 1999 Steve Murphree, Jr.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Steve Murphree, Jr.
+ * 4. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/*
+ * Mach Operating System
+ * Copyright (c) 1991 Carnegie Mellon University
+ * Copyright (c) 1991 OMRON Corporation
+ * All Rights Reserved.
+ *
+ * Permission to use, copy, modify and distribute this software and its
+ * documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ */
+
+#ifndef	__MACHINE_AV400_H__
+#define	__MACHINE_AV400_H__
+
+#define	AV400_PROM		0xffc00000
+#define	AV400_PROM_SIZE		0x00200000	/* was 020000 */
+#define	AV400_SRAM		0xffe00000
+#define	AV400_SRAM_SIZE		0x00020000
+#define	AV400_UTILITY		0xfff00000
+#define	AV400_UTILITY_SIZE	0x00100000
+#define	PROM_VBR		0xffc00000
+
+/*
+ * AV400 VME mappings
+ */
+
+#define	AV400_VME32_START1	0x10000000
+#define	AV400_VME32_END1	0x7fffffff
+#define	AV400_VME32_START2	0x90000000
+#define	AV400_VME32_END2	0xfdffffff
+#define	AV400_VME24_START	0xfe000000
+#define	AV400_VME24_END		0xfeffffff
+#define	AV400_VME16_START	0xffff0000
+#define	AV400_VME16_END		0xffffffff
+
+#define	AV400_ISVMEA32(addr) \
+	(((addr) >= AV400_VME32_START1 && (addr) < AV400_VME32_END1 + 1U) || \
+	 ((addr) >= AV400_VME32_START2 && (addr) < AV400_VME32_END2 + 1U))
+#define	AV400_ISVMEA24(addr) \
+	((addr) >= AV400_VME24_START && (addr) < AV400_VME24_END + 1U)
+#define	AV400_ISVMEA16(addr) \
+	((addr) >= AV400_VME16_START /* && (addr) <= AV400_VME16_END */)
+
+/*
+ * AV400 declarations for hardware level device registers and such.
+ */
+
+/* per-processor interrupt enable registers */
+#define	AV400_IEN0	0xfff84004	/* interrupt enable CPU 0 */
+#define	AV400_IEN1	0xfff84008	/* interrupt enable CPU 1 */
+#define	AV400_IEN2	0xfff84010	/* interrupt enable CPU 2 */
+#define	AV400_IEN3	0xfff84020	/* interrupt enable CPU 3 */
+#define	AV400_IENALL	0xfff8403c	/* simultaneous write */
+#define	AV400_IEN(cpu)	(AV400_IEN0 + ((cpu) << 2))
+
+#define	AV400_IST	0xfff84040 	/* interrupt status register */
+
+#define	AV400_SETSWI	0xfff84080 	/* generate soft interrupt */
+#define	AV400_CLRSWI	0xfff84084 	/* reset soft interrupt */
+#define	AV400_ISTATE	0xfff84088 	/* HW interrupt status */
+#define	AV400_CLRINT	0xfff8408c 	/* reset HW interrupt */
+
+#define	AV400_VIRQLV	0xfff85000
+#define	AV400_VIACK1V	0xfff85004
+#define	AV400_VIACK2V	0xfff85008
+#define	AV400_VIACK3V	0xfff8500c
+#define	AV400_VIACK4V	0xfff85010
+#define	AV400_VIACK5V	0xfff85014
+#define	AV400_VIACK6V	0xfff85018
+#define	AV400_VIACK7V	0xfff8501c
+#define	AV400_VIRQV	0xfff85020
+#define	AV400_IVEC		0x40	/* vector returned upon AV400 int */
+
+#define	AV400_GCSR	0xfff86000	/* global control and status reg */
+#define	AV400_UCSR	0xfff87000	/* utility control and status reg */
+#define	AV400_BASAD	0xfff87004	/* base address reg */
+#define	AV400_GLBRES	0xfff8700c	/* global reset reg */
+
+#define AV400_GLOBAL0	0xfff86001	/* global control and status regs */
+#define AV400_GLOBAL1	0xfff86003
+#define	AV400_LRST		0x80
+#define	AV400_SYSCON		0x40
+#define AV400_BRDID	0xfff86005
+#define AV400_CGCSR0	0xfff86007
+#define AV400_CGCSR1	0xfff86009
+#define AV400_CGCSR2	0xfff8600b
+#define AV400_CGCSR3	0xfff8600d
+#define AV400_CGCSR4	0xfff8600f
+#define	AV400_UCSR	0xfff87000	/* utility control and status reg */
+#define	AV400_BASAD	0xfff87004	/* base address reg */
+#define	AV400_GLBRES	0xfff8700c	/* global reset reg */
+
+#define	AV400_CCSR	0xfff88000	/* CPU board control status reg */
+#define	AV400_ERROR	0xfff88004	/* Mbus fault reg */
+#define	AV400_PCNFA	0xfff88008	/* Pbus A decoder reg */
+#define	AV400_PCNFB	0xfff8800c	/* Pbus B decoder reg */
+#define	AV400_EXTAD	0xfff88010	/* A24 master A24-A31 addr reg */
+#define	AV400_EXTAM	0xfff88014	/* AM3-AM0 addr modifiers reg */
+#define	AV400_WHOAMI	0xfff88018	/* whoami reg */
+#define	AV400_WMAD	0xfff88020	/* write mbus addr decoder reg */
+#define	AV400_RMAD	0xfff88024	/* read mbus addr decoder reg */
+#define	AV400_WVAD	0xfff88028	/* write vmebus addr decoder reg */
+#define	AV400_RVAD	0xfff8802c	/* read vmebus adds decoder reg */
+
+/*
+ * IEN and IST register bits
+ * See ``Programming System control and I/O registers for the 100, 200, 300,
+ * 400, 3000 and 4000 series'', section 3 (Interrupts).
+ */
+
+#define	IRQ_RESERVED	0x1800018c	/* all reserved bits */
+#define IRQ_ABORT	0x80000000	/* 31 - Abort */
+#define IRQ_ACF		0x40000000	/* 30 - AC Fail */
+#define IRQ_ARBTO	0x20000000	/* 29 - VME Arbiter Timeout */
+#define IRQ_ZBUF	0x04000000	/* 26 - Z Buffer */
+#define IRQ_VID		0x02000000	/* 25 - Video */
+#define IRQ_PAR		0x01000000	/* 24 - Parity Error */
+#define IRQ_VME7	0x00800000	/* 23 - VMEBus level 7 */
+#define IRQ_KBD		0x00400000	/* 22 - Keyboard */
+#define IRQ_CIOI	0x00200000	/* 21 - CIO */
+#define IRQ_SF		0x00100000	/* 20 - System Failure */
+#define IRQ_VME6	0x00080000	/* 19 - VMEBus level 6 */
+#define IRQ_PPI		0x00040000	/* 18 - Parallel Port */
+#define IRQ_DI1		0x00020000	/* 17 - DUART1 */
+#define IRQ_DI2		0x00010000	/* 16 - DUART2 */
+#define IRQ_ECI		0x00008000	/* 15 - Ethernet Controller */
+#define IRQ_VME5	0x00004000	/* 14 - VMEBus level 5 */
+#define IRQ_DTC		0x00002000	/* 13 - DMA Terminal Count */
+#define IRQ_VME4	0x00001000	/* 12 - VMEBus level 4 */
+#define IRQ_DWP		0x00000800	/* 11 - DMA Write Protect */
+#define IRQ_VME3	0x00000400	/* 10 - VMEBus level 3 */
+#define IRQ_DVB		0x00000200	/* 09 - DMA Valid Bit */
+#define IRQ_VME2	0x00000040	/* 06 - VMEBus level 2 */
+#define IRQ_SCI		0x00000020	/* 05 - SCSI Controller */
+#define IRQ_VME1	0x00000010	/* 04 - VMEBus level 1 */
+#define IRQ_SWI1	0x00000002	/* 01 - SW Interrupt level 1 */
+#define IRQ_SWI0	0x00000001	/* 00 - SW Interrupt level 0 */
+
+#define IST_STRING	"\20" \
+	"\40ABRT\37ACF\36ARBTO\33ZBUF\32VID\31PAR" \
+	"\30IRQ7\27KBD\26CIOI\25SF\24IRQ6\23PPI\22DI1\21DI2" \
+	"\20ECI\17IRQ5\16DTC\15IRQ4\14DWP\13IRQ3\12DVB" \
+	"\7IRQ2\6SCI\5IRQ1\2SWI1\1SWI0"
+
+/* groups by function */
+
+/* hardware irq bits */
+#define HW_FAILURE_MASK		(IRQ_ABORT | IRQ_ACF | IRQ_ARBTO | IRQ_SF | \
+				 IRQ_PAR)
+/* software irq bits */
+#define SOFT_INTERRUPT_MASK	(IRQ_SWI1 | IRQ_SWI0)
+/* VME irq bits */
+#define VME_INTERRUPT_MASK	(IRQ_VME7 | IRQ_VME6 | IRQ_VME5 | IRQ_VME4 | \
+				 IRQ_VME3 | IRQ_VME2 | IRQ_VME1)
+/* on-board irq bits */
+#define OBIO_INTERRUPT_MASK	(IRQ_ZBUF | IRQ_VID | IRQ_KBD | IRQ_CIOI | \
+				 IRQ_PPI | IRQ_DI1 | IRQ_DI2 | IRQ_ECI | \
+				 IRQ_DTC | IRQ_DWP | IRQ_DVB | IRQ_SCI)
+
+/* groups by interrupt levels */
+/* we do not enable and define levels yet for: ZBUF, VID, KBD, PPI, SCI, DMA */
+
+#define LVL7			(IRQ_ABORT | IRQ_ACF | IRQ_VME7 | IRQ_SF)
+#define LVL6			(IRQ_VME6)
+#define LVL5			(IRQ_VME5 | IRQ_CIOI)
+#define LVL4			(IRQ_VME4)
+#define LVL3			(IRQ_VME3 | IRQ_DI1 | IRQ_DI2)
+#define LVL2			(IRQ_VME2) /* | IRQ_SCI */
+#define LVL1			(IRQ_VME1 | IRQ_ECI )
+#define LVL0			(0x0)
+
+/* interrupts we want to process on the master CPU only */
+#define SLAVE_MASK		(HW_FAILURE_MASK | OBIO_INTERRUPT_MASK)
+
+#define MASK_LVL_0		(LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2 | LVL1)
+#define MASK_LVL_1		(LVL7 | LVL6 | LVL5 | LVL4 | LVL3 | LVL2)
+#define MASK_LVL_2		(LVL7 | LVL6 | LVL5 | LVL4 | LVL3)
+#define MASK_LVL_3		(LVL7 | LVL6 | LVL5 | LVL4)
+#define MASK_LVL_4		(LVL7 | LVL6 | LVL5)
+#define MASK_LVL_5		(LVL7 | LVL6)
+#define MASK_LVL_6		(LVL7)
+#define MASK_LVL_7		(IRQ_ABORT)
+
+#define INT_LEVEL	        8		/* # of interrupt level + 1 */
+#define ISR_GET_CURRENT_MASK(cpu) \
+	(*(volatile u_int *)AV400_IST & int_mask_reg[cpu])
+
+/*
+ * ISTATE and CLRINT register bits
+ */
+
+#define ISTATE_ABORT		0x04
+#define	ISTATE_ACFAIL		0x02
+#define	ISTATE_SYSFAIL		0x01
+
+/*
+ * UCSR register bits
+ */
+
+#define UCSR_PWRUPBIT 	0x00004000	/* powerup indicator */
+#define UCSR_DRVSFBIT 	0x00002000	/* Board system fail */
+#define UCSR_BRIRQBIT 	0x00001000	/* drives VME IRQ1 broadcast int */
+#define UCSR_ROBINBIT 	0x00000800	/* sel round robin VME arbiter mode */
+#define UCSR_BRLVBITS 	0x00000600	/* VME bus request level 0-3 */
+#define UCSR_RNEVERBIT  0x00000100	/* VME bus never release once req'd */
+#define UCSR_RONRBIT	0x00000080	/* VME bus req release on no request */
+#define UCSR_RWDBIT	0x00000040	/* VME bus request release when done */
+#define UCSR_EARBTOBIT  0x00000020	/* enable VME arbiter bus timeout */
+#define VTOSELBITS	0x00000018	/* VMEbus timeout select bits */
+#define VTO32US			0x00	/* 32 usec */
+#define VTO64US			0x01	/* 64 usec */
+#define VTO128US		0x10	/* 128 usec */
+#define VTODISABLE		0x18	/* disabled */
+
+/* these are the various Z8536 CIO counter/timer registers */
+#define CIO_BASE		0xfff83000
+#define CIO_PORTC		0xfff83000
+#define CIO_PORTB		0xfff83004
+#define CIO_PORTA		0xfff83008
+#define CIO_CTRL		0xfff8300c
+
+#define CIO_MICR		0x00	/* Master interrupt control register */
+#define CIO_MICR_MIE		0x80
+#define CIO_MICR_DLC		0x40
+#define CIO_MICR_NV		0x20
+#define CIO_MICR_PAVIS		0x10
+#define CIO_MICR_PBVIS		0x08
+#define CIO_MICR_CTVIS		0x04
+#define CIO_MICR_RJA		0x02
+#define CIO_MICR_RESET		0x01
+
+#define CIO_MCCR		0x01	/* Master config control register */
+#define CIO_MCCR_PBE		0x80
+#define CIO_MCCR_CT1E		0x40
+#define CIO_MCCR_CT2E		0x20
+#define CIO_MCCR_CT3E		0x10
+#define CIO_MCCR_PLC		0x08
+#define CIO_MCCR_PAE		0x04
+
+#define CIO_CTMS1		0x1c	/* Counter/timer mode specification #1 */
+#define CIO_CTMS2		0x1d	/* Counter/timer mode specification #2 */
+#define CIO_CTMS3		0x1e	/* Counter/timer mode specification #3 */
+#define CIO_CTMS_CSC		0x80	/* Continuous Single Cycle */
+#define CIO_CTMS_EOE		0x40	/* External Output Enable  */
+#define CIO_CTMS_ECE		0x20	/* External Count Enable   */
+#define CIO_CTMS_ETE		0x10	/* External Trigger Enable */
+#define CIO_CTMS_EGE		0x08	/* External Gate Enable    */
+#define CIO_CTMS_REB		0x04	/* Retrigger Enable Bit    */
+#define CIO_CTMS_PO		0x00	/* Pulse Output            */
+#define CIO_CTMS_OSO		0x01	/* One Shot Output         */
+#define CIO_CTMS_SWO		0x02	/* Square Wave Output      */
+
+#define CIO_IVR			0x04	/* Interrupt vector register */
+
+#define CIO_CSR1		0x0a	/* Command and status register CTC #1 */
+#define CIO_CSR2		0x0b	/* Command and status register CTC #2 */
+#define CIO_CSR3		0x0c	/* Command and status register CTC #3 */
+
+#define CIO_CT1MSB		0x16	/* CTC #1 Timer constant - MSB */
+#define CIO_CT1LSB		0x17	/* CTC #1 Timer constant - LSB */
+#define CIO_CT2MSB		0x18	/* CTC #2 Timer constant - MSB */
+#define CIO_CT2LSB		0x19	/* CTC #2 Timer constant - LSB */
+#define CIO_CT3MSB		0x1a	/* CTC #3 Timer constant - MSB */
+#define CIO_CT3LSB		0x1b	/* CTC #3 Timer constant - LSB */
+#define CIO_PDCA		0x23	/* Port A data direction control */
+#define CIO_PDCB		0x2b	/* Port B data direction control */
+
+#define CIO_GCB			0x04	/* CTC Gate command bit */
+#define CIO_TCB			0x02	/* CTC Trigger command bit */
+#define CIO_IE			0xc0	/* CTC Interrupt enable (set) */
+#define CIO_CIP			0x20	/* CTC Clear interrupt pending */
+#define CIO_IP			0x20	/* CTC Interrupt pending */
+
+#define DART_BASE		0xfff82000
+
+/*
+ * CMMU addresses
+ */
+
+#define AV400_CMMU_D0	0xfff00000
+#define AV400_CMMU_I0	0xfff01000
+#define AV400_CMMU_D1	0xfff02000
+#define AV400_CMMU_I1	0xfff03000
+#define AV400_CMMU_D2	0xfff04000
+#define AV400_CMMU_I2	0xfff05000
+#define AV400_CMMU_D3	0xfff06000
+#define AV400_CMMU_I3	0xfff07000
+
+#endif	/* __MACHINE_AV400_H__ */