diff options
| author | Daniel Dickman <daniel@cvs.openbsd.org> | 2022-08-20 23:33:54 +0000 |
|---|---|---|
| committer | Daniel Dickman <daniel@cvs.openbsd.org> | 2022-08-20 23:33:54 +0000 |
| commit | 645a3a4b5060642d99ad9e7574c8014c6f1dfc27 (patch) | |
| tree | 879db0fbacc8e2810da98ee7d8a430cea4bf99ee /sys/arch/i386/include | |
| parent | fa7641bf34000db0a3c5840a6384b2bec162c1c0 (diff) | |
drop detection code for Cyrix CPUs older than the Cyrix M2
The 486DLC is a 486-class CPU which we no longer support on i386.
The 6x86 (also known as the M1) did not support CPUID by default[*]
so extra support code is needed to differentiate between these early
Cyrix processors in order to apply some errata that the M1 needs.
However the 6x86 doesn't implement the RDTSC instruction so we can
remove support code for this CPU at this point.
Cyrix implemented RDTSC in the 6x86MX (also known as the M2). So
this is likely the earliest Cyrix CPU that we can support on i386.
We keep the support code in "cyrix6x86_cpu_setup" because early
6x86MX CPUs would continue to benefit from this fixup code.
[*]: CPUID can be enabled on the Cyrix 6x86 by setting bit 7 of
CCR4
ok mlarkin@, jsg@
Diffstat (limited to 'sys/arch/i386/include')
| -rw-r--r-- | sys/arch/i386/include/cputypes.h | 15 | ||||
| -rw-r--r-- | sys/arch/i386/include/specialreg.h | 19 |
2 files changed, 4 insertions, 30 deletions
diff --git a/sys/arch/i386/include/cputypes.h b/sys/arch/i386/include/cputypes.h index 26f50e8230d..fd7c6b0bd3d 100644 --- a/sys/arch/i386/include/cputypes.h +++ b/sys/arch/i386/include/cputypes.h @@ -1,4 +1,4 @@ -/* $OpenBSD: cputypes.h,v 1.13 2022/08/15 04:17:51 daniel Exp $ */ +/* $OpenBSD: cputypes.h,v 1.14 2022/08/20 23:33:53 daniel Exp $ */ /* $NetBSD: cputypes.h,v 1.10 1997/10/18 04:51:03 mikel Exp $ */ /* @@ -37,19 +37,10 @@ #define CPUCLASS_686 3 /* - * Kinds of Processor. Only the first 7 are used, as they are processors - * that might not have a cpuid instruction. + * Kind of Processor. */ -#define CPU_486SX 2 /* Intel 80486SX */ -#define CPU_486 3 /* Intel 80486DX */ -#define CPU_486DLC 4 /* Cyrix 486DLC */ -#define CPU_6x86 5 /* Cyrix/IBM 6x86 */ -#define CPU_586 7 /* Intel P.....m (I hate lawyers; it's TM) */ -#define CPU_AM586 8 /* AMD Am486 and Am5x86 */ -#define CPU_K5 9 /* AMD K5 */ -#define CPU_K6 10 /* AMD K6 */ -#define CPU_686 11 /* Intel P.....m Pro */ +#define CPU_486 0 /* Intel 80486DX */ /* * CPU vendors diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index 3e6db64a69e..392b4ff412e 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.79 2022/02/21 10:06:35 jsg Exp $ */ +/* $OpenBSD: specialreg.h,v 1.80 2022/08/20 23:33:53 daniel Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -52,23 +52,6 @@ #define CR0_CD 0x40000000 /* Cache Disable */ /* - * Cyrix 486 DLC special registers, accessible as IO ports. - */ -#define CCR0 0xc0 /* configuration control register 0 */ -#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ -#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ -#define CCR0_A20M 0x04 /* enables A20M# input pin */ -#define CCR0_KEN 0x08 /* enables KEN# input pin */ -#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ -#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ -#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ -#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ - -#define CCR1 0xc1 /* configuration control register 1 */ -#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ -/* the remaining 7 bits of this register are reserved */ - -/* * bits in CR3 */ #define CR3_PWT (1ULL << 3) |