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authorJonathan Gray <jsg@cvs.openbsd.org>2005-08-20 00:27:09 +0000
committerJonathan Gray <jsg@cvs.openbsd.org>2005-08-20 00:27:09 +0000
commit7cfd9446092e192a85a3ea0d5b1a3103b751739f (patch)
tree763413ad5cb00672ca9eff5f61d363d832009bf0 /sys/arch/i386/include
parent44ee25d2d27e0d2ea43f0db770fb71b53a7ad9cf (diff)
PNI was changed to be known as SSE3 by Intel so make
a similiar change when reporting CPU features here. ok deraadt@
Diffstat (limited to 'sys/arch/i386/include')
-rw-r--r--sys/arch/i386/include/specialreg.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index b3c90521454..beabfb23cdb 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: specialreg.h,v 1.25 2005/06/26 19:24:22 deraadt Exp $ */
+/* $OpenBSD: specialreg.h,v 1.26 2005/08/20 00:27:08 jsg Exp $ */
/* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
/*-
@@ -131,7 +131,7 @@
#define CPUID_3DNOW 0x40000000 /* has 3DNow! instructions (AMD) */
#define CPUID_LONG 0x20000000 /* long mode (AMD64, ext cpuid) */
-#define CPUIDECX_PNI 0x00000001 /* Prescott New Instructions */
+#define CPUIDECX_SSE3 0x00000001 /* has SSE3 instructions */
#define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */
#define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */
#define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */