diff options
| author | Jonathan Gray <jsg@cvs.openbsd.org> | 2020-09-13 05:57:29 +0000 |
|---|---|---|
| committer | Jonathan Gray <jsg@cvs.openbsd.org> | 2020-09-13 05:57:29 +0000 |
| commit | 416e42d56fd48dfd4ff048b7a75cda5fa59f48b5 (patch) | |
| tree | 40a3ed758f7070b36e0719b3a29076ad360de22c /sys/arch/i386 | |
| parent | 8b9e77ff3022195be642f703dc747a407fce2b4d (diff) | |
add SRBDS cpuid bits
Diffstat (limited to 'sys/arch/i386')
| -rw-r--r-- | sys/arch/i386/i386/machdep.c | 5 | ||||
| -rw-r--r-- | sys/arch/i386/include/specialreg.h | 7 |
2 files changed, 10 insertions, 2 deletions
diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c index 64e8db2ce12..a8b8529437e 100644 --- a/sys/arch/i386/i386/machdep.c +++ b/sys/arch/i386/i386/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.638 2020/08/23 01:12:04 gnezdo Exp $ */ +/* $OpenBSD: machdep.c,v 1.639 2020/09/13 05:57:28 jsg Exp $ */ /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ /*- @@ -1099,6 +1099,9 @@ const struct cpu_cpuid_feature cpu_seff0_ecxfeatures[] = { const struct cpu_cpuid_feature cpu_seff0_edxfeatures[] = { { SEFF0EDX_AVX512_4FNNIW, "AVX512FNNIW" }, { SEFF0EDX_AVX512_4FMAPS, "AVX512FMAPS" }, + { SEFF0EDX_SRBDS_CTRL, "SRBDS_CTRL" }, + { SEFF0EDX_MD_CLEAR, "MD_CLEAR" }, + { SEFF0EDX_TSXFA, "TSXFA" }, { SEFF0EDX_IBRS, "IBRS,IBPB" }, { SEFF0EDX_STIBP, "STIBP" }, { SEFF0EDX_L1DF, "L1DF" }, diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h index c100f75fe4b..06cdc2bf811 100644 --- a/sys/arch/i386/include/specialreg.h +++ b/sys/arch/i386/include/specialreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: specialreg.h,v 1.75 2019/12/20 07:55:30 jsg Exp $ */ +/* $OpenBSD: specialreg.h,v 1.76 2020/09/13 05:57:28 jsg Exp $ */ /* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */ /*- @@ -210,6 +210,9 @@ /* SEFF EDX bits */ #define SEFF0EDX_AVX512_4FNNIW 0x00000004 /* AVX-512 neural network insns */ #define SEFF0EDX_AVX512_4FMAPS 0x00000008 /* AVX-512 mult accum single prec */ +#define SEFF0EDX_SRBDS_CTRL 0x00000200 /* MCU_OPT_CTRL MSR */ +#define SEFF0EDX_MD_CLEAR 0x00000400 /* Microarch Data Clear */ +#define SEFF0EDX_TSXFA 0x00002000 /* TSX Forced Abort */ #define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ #define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ #define SEFF0EDX_L1DF 0x10000000 /* L1D_FLUSH */ @@ -380,6 +383,8 @@ #define MSR_TSX_CTRL 0x122 #define TSX_CTRL_RTM_DISABLE (1ULL << 0) #define TSX_CTRL_TSX_CPUID_CLEAR (1ULL << 1) +#define MSR_MCU_OPT_CTRL 0x123 +#define RNGDS_MITG_DIS (1ULL << 0) #define MSR_SYSENTER_CS 0x174 #define MSR_SYSENTER_ESP 0x175 #define MSR_SYSENTER_EIP 0x176 |