Convert some magic numbers into #defines - this is needed for some MTRR

decoding code I'm working on for vmm(4) debugging. No functional change.

2 files changed, 14 insertions, 7 deletions

diff --git a/sys/arch/i386/i386/i686_mem.c b/sys/arch/i386/i386/i686_mem.c
index 3f7cbb531be..f83ab39c805 100644
--- a/sys/arch/i386/i386/i686_mem.c
+++ b/sys/arch/i386/i386/i686_mem.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: i686_mem.c,v 1.17 2014/12/09 06:58:28 doug Exp $ */
+/* $OpenBSD: i686_mem.c,v 1.18 2016/04/26 15:27:32 mlarkin Exp $ */
 /*
  * Copyright (c) 1999 Michael Smith <msmith@freebsd.org>
  * All rights reserved.
@@ -305,7 +305,7 @@ mrstoreone(struct mem_range_softc *sc)
 	/* Flush caches, then disable caches, then disable MTRRs */
 	wbinvd();
 	lcr0((rcr0() & ~CR0_NW) | CR0_CD);
-	wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~0x800);
+	wrmsr(MSR_MTRRdefType, rdmsr(MSR_MTRRdefType) & ~MTRRdefType_ENABLE);
 	
 	/* Set fixed-range MTRRs */
 	if (sc->mr_cap & MR_FIXMTRR) {
@@ -362,7 +362,7 @@ mrstoreone(struct mem_range_softc *sc)
 	}
 
 	/* Re-enable caches and MTRRs */
-	wrmsr(MSR_MTRRdefType, mtrrdef | 0x800);
+	wrmsr(MSR_MTRRdefType, mtrrdef | MTRRdefType_ENABLE);
 	lcr0(rcr0() & ~(CR0_CD | CR0_NW));
 	lcr4(cr4save);
 }
@@ -535,7 +535,7 @@ mrinit(struct mem_range_softc *sc)
 	mtrrdef = rdmsr(MSR_MTRRdefType);
 	
 	/* For now, bail out if MTRRs are not enabled */
-	if (!(mtrrdef & 0x800)) {
+	if (!(mtrrdef & MTRRdefType_ENABLE)) {
 		printf("mtrr: CPU supports MTRRs but not enabled by BIOS\n");
 		return;
 	}
@@ -543,7 +543,8 @@ mrinit(struct mem_range_softc *sc)
 	printf("mtrr: Pentium Pro MTRR support, %d var ranges", nmdesc);
 	
 	/* If fixed MTRRs supported and enabled */
-	if ((mtrrcap & 0x100) && (mtrrdef & 0x400)) {
+	if ((mtrrcap & MTRRcap_FIXED) && 
+	    (mtrrdef & MTRRdefType_FIXED_ENABLE)) {
 		sc->mr_cap = MR_FIXMTRR;
 		nmdesc += MTRR_N64K + MTRR_N16K + MTRR_N4K;
 		printf(", %d fixed ranges", MTRR_N64K + MTRR_N16K + MTRR_N4K);
@@ -582,7 +583,7 @@ mrinit(struct mem_range_softc *sc)
 	 * Fetch maximum physical address size supported by the
 	 * processor as supported by CPUID leaf function 0x80000008.
 	 * If CPUID does not support leaf function 0x80000008, use the
-	 * default a 36-bit address size.
+	 * default 36-bit address size.
 	 */
 	CPUID(0x80000000, regs[0], regs[1], regs[2], regs[3]);
 	if (regs[0] >= 0x80000008) {
diff --git a/sys/arch/i386/include/specialreg.h b/sys/arch/i386/include/specialreg.h
index 31bd5c5bc57..11d2ba3c384 100644
--- a/sys/arch/i386/include/specialreg.h
+++ b/sys/arch/i386/include/specialreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: specialreg.h,v 1.53 2015/12/07 06:34:14 jsg Exp $	*/
+/*	$OpenBSD: specialreg.h,v 1.54 2016/04/26 15:27:32 mlarkin Exp $	*/
 /*	$NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $	*/
 
 /*-
@@ -318,6 +318,9 @@
 #define MSR_TEMPERATURE_TARGET_UNDOCUMENTED	0x0ee
 #define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED	0x40000000
 #define MSR_MTRRcap		0x0fe
+#define MTRRcap_FIXED		0x100	/* bit 8 - fixed MTRRs supported */
+#define MTRRcap_WC		0x400	/* bit 10 - WC type supported */
+#define MTRRcap_SMRR		0x800	/* bit 11 - SMM range reg supported */
 #define	MSR_BBL_CR_ADDR		0x116	/* PII+ only */
 #define	MSR_BBL_CR_DECC		0x118	/* PII+ only */
 #define	MSR_BBL_CR_CTL		0x119	/* PII+ only */
@@ -334,6 +337,7 @@
 #define P6MSR_CTRSEL1		0x187
 #define MSR_PERF_STATUS		0x198	/* Pentium M */
 #define MSR_PERF_CTL		0x199	/* Pentium M */
+#define PERF_CTL_TURBO		0x100000000ULL /* bit 32 - turbo mode */
 #define MSR_THERM_CONTROL	0x19a
 #define MSR_THERM_INTERRUPT	0x19b
 #define MSR_THERM_STATUS	0x19c
@@ -353,6 +357,8 @@
 #define MSR_MTRRfix4K_C0000	0x268
 #define MSR_CR_PAT		0x277
 #define MSR_MTRRdefType		0x2ff
+#define MTRRdefType_FIXED_ENABLE	0x400 /* bit 10 - fixed MTRR enabled */
+#define MTRRdefType_ENABLE	0x800 /* bit 11 - MTRRs enabled */
 #define MSR_PERF_FIXED_CTR1	0x30a	/* CPU_CLK_Unhalted.Core */
 #define MSR_PERF_FIXED_CTR2	0x30b	/* CPU_CLK.Unhalted.Ref */
 #define MSR_PERF_FIXED_CTR_CTRL	0x38d